KR20070063944A - Display device - Google Patents

Abstract

A display apparatus for reducing brightness difference is provided to broaden material selection range of a data line and to simplify the manufacturing process, by determining and applying the polarity of a data voltage from a data driving unit in a column inversion method. A plurality of pixel row groups is arranged in a matrix form, and includes at least one of pixel rows composed of a plurality of pixels having switching devices. A plurality of gate lines(G1~G9) is connected to the switching devices and transfers gate-on voltages for turning on the switching devices. A plurality of data lines(D1~Dm) is connected to the switching devices and transfers data voltages. A dummy line(DL) is connected to the switching device and transfers a predetermined voltage. The switching devices of neighboring pixel row groups are connected to the data lines at different sides. The dummy line is connected to the switching devices arranged at a first pixel column or the last pixel column.

Description

Display device {DISPLAY DEVICE}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a diagram illustrating a pixel array according to an exemplary embodiment of the present invention.

The present invention relates to a display device.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto.

In such a liquid crystal display, a voltage is applied to two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. In this case, in order to prevent degradation caused by an electric field applied to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row by pixel, or pixel by pixel.

Among the data voltage inversion methods, when the polarity of the data voltage is inverted for each pixel (hereinafter referred to as point inversion), the vertical flicker phenomenon due to the kickback voltage or the vertical crosstalk phenomenon is reduced, thereby reducing the image quality. This is improved. However, since the polarities of the data voltages must be inverted for each predetermined row and predetermined column, the operation of applying the data voltage to the data line becomes complicated and the problem due to the signal delay of the data line becomes serious. As a result, manufacturing processes are complicated and manufacturing costs are increased, such as making data lines with low resistance materials to reduce signal delay.

On the other hand, if the polarity of the data voltage is inverted for each predetermined column (hereinafter referred to as column inversion), the polarity of the data voltage flowing through one data line is inverted only for each frame, thereby greatly reducing the signal delay problem of the data line.

However, since thermal inversion does not maintain the advantages of dot inversion, the image quality of the liquid crystal display deteriorates due to vertical flicker and vertical crosstalk.

Accordingly, an object of the present invention is to provide a liquid crystal display having both the advantages of thermal inversion and the advantages of dot inversion.

Another object of the present invention is to improve the image quality of a liquid crystal display device.

A display device according to an aspect of the present invention includes a plurality of pixel row groups arranged in a matrix form, each pixel row group including at least one pixel row including a plurality of pixels including switching elements, and connected to the switching element. And a plurality of gate lines transferring a gate-on voltage for turning on the switching element, a plurality of data lines connected to the switching element, and a plurality of data lines transferring a data voltage, and connected to the switching element, and transmitting a predetermined voltage. The dummy line includes a dummy line, and the switching elements of adjacent pixel row groups are connected to different data lines, and the dummy lines are connected to switching elements arranged in the first pixel column or the last pixel column.

The dummy line may be connected to a switching element positioned in the even or odd pixel row of the first or last pixel column.

Each switching element of the pixel row group is connected to the same data line, and each switching element of the adjacent pixel row group is connected to a data line different from the data line.

The data voltage of the pixel row group may have a different polarity from that of the adjacent pixel row group.

The data voltages of the pixel rows in the pixel row group may be the same polarity.

The predetermined voltage may be a common voltage.

Inverting the driving unit of the display device may be thermal inversion.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display and a driving method thereof according to an exemplary embodiment of the display device and the driving method thereof according to the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention. 3 is a diagram illustrating a pixel array according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300, when viewed as an equivalent circuit, includes a plurality of signal lines G ₁ -G _n , D ₁ -D _m, DL, and a plurality of pixels PX connected thereto and arranged in a substantially matrix form. ). On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n , D ₁ -D _m , DL are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a plurality of data for transmitting a data signal. The line D ₁ -D _m and the dummy line DL are included. The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m and the dummy line DL extend substantially in the column direction and are substantially parallel to each other. The dummy line DL is formed at the leftmost edge of the liquid crystal panel assembly 300 in front of the first data line D ₁ , and is connected to a pad to which a predetermined voltage, for example, the common voltage Vcom, is applied. The voltage Vcom may be applied.

Each pixel PX, for example, the i-th (i = 1, 2, ..., n) gate line G _i and the j-th (j = 1, 2, ..., m) data line D _j or the pixel PX connected to the dummy line DL includes a switching element Q connected to the signal line G _i , D _j or DL, a liquid crystal capacitor Clc and a storage capacitor connected thereto. capacitor) (Cst). Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

As shown in FIG. 3, one switching element Q and one in one region partitioned by two adjacent gate lines G ₁ -G _n and two adjacent data lines D ₁ -D _m . One pixel including the pixel electrode 191 is allocated, and the switching element Q of each pixel is one of the upper and lower gate lines G ₁ -G _n and the left and right data lines D ₁ -D _m . Can be connected to one. However, in the case of the first pixel column, pixels are allocated to an area partitioned by two adjacent gate lines G ₁ -G _n , one dummy line DL, and the first data line D ₁ , and the first pixel row In this case, the pixel is allocated to a region partitioned by one gate line G ₁ and two adjacent data lines D ₁ -D _m . However, in the case of the last pixel row, a pixel may be allocated to an area partitioned by one gate line G _n and two adjacent data lines D ₁ -D _m .

The connection between the gate lines G ₁ -G _n and the data lines D ₁ -D _m or the dummy line DL and the pixel electrode 191 will be described in more detail.

As illustrated in FIG. 3, the switching elements Q of all the pixels PX are formed below the pixel electrode 191, and are disposed on the gate lines G ₁ -G _n formed below the pixel electrode 191. The gate line and the pixel electrode 191 are connected to each other. However, the pixel electrode 191 may be connected to the gate lines G ₁ -G _n formed above the pixel electrode 191, in which case the switching element Q is formed above the pixel electrode 191 and the pixel The gate line is formed above the electrode 191 to connect the gate line and the pixel electrode 191.

In addition, the switching elements Q in the same pixel row are formed in the same direction and connected to the data lines D ₁ -D _m in the same direction, and the switching elements Q in adjacent pixel rows are formed in different directions. It is connected to the data lines D ₁ -D _{m in} different directions. For example, the switching elements Q of odd-numbered pixel rows are formed on the right side of the pixel electrode 191 and connected to the data lines D ₁ -D _m positioned on the right side of the pixel electrode 191. As a result, the pixel electrodes 191 of the odd-numbered pixel rows are connected to the data lines D ₁ -D _m located at the right through the switching element Q. On the other hand, the switching elements Q of the even-numbered pixel rows are formed on the left side of the pixel electrode 191 and are connected to the data lines D ₁ -D _m positioned on the left side of the pixel electrode 191. As a result, the pixel electrodes 191 of the even-numbered pixel rows are connected to the data lines D ₁ -D _m located on the left side through the switching element Q. FIG.

As such, the direction of the switching element Q connected to the one data line D ₁ -D _m is changed in units of one pixel row. In this case, as shown in FIG. 3, since the pixel PX is formed on the left side around the data lines D ₁ -D _m , the pixel electrode of the pixel PX located in the even-numbered pixel row of the first pixel column. 191 is connected to the dummy line DL located on its left side through the corresponding switching element Q. FIG. On the other hand, when the pixel PX is formed on the right side of the data line D ₁ -D _m , the dummy line DL is the maximum of the liquid crystal panel assembly 300 after the last data line D _m . The pixel electrode 191 of the pixel PX formed at the right edge and positioned in the even-numbered pixel row of the last pixel column is connected to the pixel electrode 191 through a corresponding switching element Q.

As described above, the switching element Q formed in each pixel can be more easily connected to the connected data line D ₁ -D _m or the dummy line DL, that is, at a position where the connection length can be as short as possible. Is formed.

The arrangement shown in FIG. 3 is just one example, and the connection of the pixel electrodes 191 and the data lines D ₁ -D _m and the gate lines G ₁ -G _{2n in the} odd and even rows are mutually different. It can be changed and can also have other connections. For example, the position of the switching element Q may be changed in units of two or more consecutive pixel rows (referred to as pixel row sets) to change the connection direction between the pixel electrode 191 and the data line.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

3, the color filters 230 are arranged in the order of red, green, and blue in the row direction, and each pixel column forms a stripe arrangement including only the color filter 230 of one color.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ).

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 are connected to the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m , DL and the thin film transistor switching element Q. It may be integrated. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

The display operation of such a liquid crystal display device will now be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external device (not shown). The input video signals R, G, and B contain luminance information of each pixel PX, and the luminance is a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ), or 64 (= 2 ⁶ ) It has gray. Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling the output of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is a load signal LOAD for applying a data signal to the horizontal synchronization start signal STH indicating the start of the transmission of the image signal for one row of pixels PX and the data lines D ₁ -D _m . ) And a data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal for the common voltage ") RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixel PX in one row and corresponds to each digital image signal DAT. The gradation voltage is selected to convert the digital image signal DAT into an analog data signal and then apply it to the data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. Then, the data signal applied to the data lines D ₁ -D _m or the common voltage Vcom applied to the dummy line DL is applied to the pixel PX through the turned-on switching element Q.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented as a change in transmittance of light by a polarizer attached to the display panel assembly 300, and thus a desired image may be displayed.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all the gate lines G ₁ -G _n. ), The gate-on voltage Von is sequentially applied to the data signal to all the pixels PX, thereby displaying an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame").

In addition to the frame inversion, the data driver 500 changes the polarity of the data voltage descending each data line D ₁ -D _m in one frame, and thus also changes the polarity of the pixel voltage to which the data voltage is applied. However, as shown in FIG. 3, since the connection between the pixels and the data lines D ₁ -D _m varies, the polarity inversion pattern of the data driver 500 and the pixel voltage appearing on the screen of the liquid crystal panel assembly 300 are reversed. The pattern looks different. In the following, the inversion in the data driver 500 is referred to as driver inversion, and the inversion that appears on the screen is called an inversion.

Next, the inversion form according to the embodiment of the present invention will be described in detail with reference to FIG. 3.

3 is a case where the driver inversion is a column inversion, in which the polarities of the data voltages applied to the respective data lines are the same and the polarities of the data voltages applied to the neighboring data lines are opposite.

In the case of Fig. 3, since the position of the switching element Q is changed every pixel row, the apparent inversion is 1 × 1 dot inversion. In contrast, when the position of the switching element Q changes every M pixel rows, the apparent inversion may be M × 1 dot inversion.

As such, when the apparent inversion causes the dot inversion, the difference in luminance due to the kickback voltage appears when the pixel voltage is positive and negative, so that vertical line defects are reduced.

In addition, the dummy line DL is formed to apply a predetermined voltage to the even-numbered pixels of the first pixel column, thereby charging the corresponding pixels, thereby reducing the luminance difference due to interference between adjacent pixels.

That is, when the dummy line DL is not formed, since no data voltage is applied to the even-numbered pixels of the first pixel column, the charging operation of the pixel electrode 191 is not performed, and thus, the data line D ₁ is used. Luminance differences occur between adjacent pixels in the column direction to which the data voltage is normally applied.

In addition, the pixels of the second pixel column adjacent to the pixels of the first pixel column to which the data voltage is normally applied from the first data line D ₁ are affected by the pixel voltages charged in the pixels arranged on the left and right sides. The pixels of the second pixel column adjacent to the pixels of the first pixel column to which no voltage is applied are only affected by the pixel voltage charged in the pixels arranged on the right side. For this reason, the degree of interference due to the left and right pixels is not constant between the pixels of the second pixel column, so that a luminance difference occurs.

However, as in the exemplary embodiment of the present invention, a predetermined voltage is also applied through the dummy line DL to a pixel that does not normally receive the data voltage through the data line D ₁ , so that luminance difference between pixels adjacent in the column direction is also eliminated. In addition, since the data voltage is applied to all the pixels of the first pixel column through the data line D ₁ or the dummy line DL, the pixel voltages of all the pixels of the second pixel column are equal to the pixel voltages of the pixels arranged on the left and right sides. Will be affected. As a result, the luminance difference caused by the deviation of the interference of adjacent pixels is reduced.

As described above, when the switching elements of the pixels are arranged, the apparent inversion may be M × 1 dot inversion even though the driving unit inversion is a thermal inversion scheme. Therefore, since the polarity of the data voltage is determined and applied from the data driver by the column inversion method, the material selection width of the data line is increased, and the manufacturing process is easily simplified. In addition, the response time of the liquid crystal display is improved due to an increase in the time that the data voltage is charged in the pixel, and even if the wiring resistance is increased by reducing the width of the data line, the signal delay problem is not large. Therefore, the aperture ratio of the liquid crystal display may be increased. .

In addition, since a dummy line is added so that the data voltages can be charged in all the pixels, the interference between pixels adjacent in the row direction or the column direction is almost uniform, so that the luminance difference between the pixels adjacent in the row direction or the column direction due to the luminance difference is achieved. Image quality defects are reduced.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (7)

A plurality of pixel row groups arranged in the form of a matrix, each pixel row group including at least one pixel row composed of a plurality of pixels including switching elements, A plurality of gate lines connected to the switching element and transferring a gate on voltage for turning on the switching element, A plurality of data lines connected to the switching element and transferring data voltages; A dummy line connected to the switching element and transferring a predetermined voltage Including, Switching elements in adjacent pixel row groups are connected to data lines on the other side, The dummy line is connected to a switching element disposed in the first pixel column or the last pixel column. Display device. In claim 1, And the dummy line is connected to a switching element positioned in an even pixel row or an odd pixel row of a first pixel column or a last pixel column. In claim 1, Each switching element of the pixel row group is connected to the same data line, And each switching element of an adjacent pixel row group is connected to a data line different from the data line. In claim 3, The data voltage of the pixel row group has a different polarity from that of the adjacent pixel row group. In claim 3, And a data voltage of each pixel row in the pixel row group is the same polarity. In claim 1, And the predetermined voltage is a common voltage. In claim 1, The driving unit inversion of the display device is a column inversion.

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