KR101272338B1 - Liquid crystal display - Google Patents

Liquid crystal display Download PDF

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KR101272338B1
KR101272338B1 KR1020120070920A KR20120070920A KR101272338B1 KR 101272338 B1 KR101272338 B1 KR 101272338B1 KR 1020120070920 A KR1020120070920 A KR 1020120070920A KR 20120070920 A KR20120070920 A KR 20120070920A KR 101272338 B1 KR101272338 B1 KR 101272338B1
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subpixel
data
data line
pixel
liquid crystal
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KR1020120070920A
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Korean (ko)
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KR20120090888A (en
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백승수
김동규
이백원
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삼성디스플레이 주식회사
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Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an arrangement of pixels of a liquid crystal display device capable of preventing coupling defects and vertical line defects during high speed driving.
The liquid crystal display includes a plurality of pixels arranged in a matrix, a so-called switching element connected to the pixels, a data line and a gate line connected thereto, and data to generate and apply a data voltage to the data line. And a driver, wherein the data lines are arranged in pairs on the left and right sides of the pixel, and data voltages of different polarities having the same magnitude are applied to the pair of data lines.
In this manner, high speed driving can be performed while preventing coupling defects and vertical string defects.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in the form of a matrix and connected to a switching element such as a thin film transistor (TFT), and are supplied with a data voltage one row at a time. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer between the pixel electrode and the common electrode form a liquid crystal capacitor in a circuit view, and the liquid crystal capacitor together with the switching device connected thereto constitutes a pixel unit.

In such a liquid crystal display device, a voltage is applied to the two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. In this case, in order to prevent degradation caused by an electric field applied to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row by pixel, or pixel by pixel.

On the other hand, in such a liquid crystal display, various methods have been tried to improve moving picture display characteristics. For example, high-speed driving that drives at a speed of 120 frames per second is being developed. For high-speed driving, the liquid crystal should have twice the response speed compared to the speed of 60 frames per second, and it is currently considered possible.

In addition, since high power consumption consumes a lot of power as the frame rate is high, the inversion driving scheme attempts to minimize power consumption by introducing column inversion.

Thermal inversion is to change the polarity of the data voltage flowing through the same data line in one frame unit, which is very advantageous in terms of power consumption because the number of data voltage inversions is once per frame.

However, thermal reversal has two major problems: one with coupling defects and the other with stripe defects.

The coupling defect refers to the luminance of the upper and lower parts of the liquid crystal panel assembly as the data voltage of the same polarity is continuously applied for one frame due to the parasitic capacitance caused by the overlap of the data line and the pixel electrode. In particular, when a box of higher gradation is displayed on the low gradation desktop in the middle of the screen, a vertical crosstalk phenomenon may appear at the top and bottom of the box having a different gradation than the desktop. In order to solve such coupling defects fairly, there is a difficulty in that parasitic capacitance due to overlapping of the data line and the pixel electrode should be less than or equal to 1% of the total capacitance.

The vertical line defect is a phenomenon in which vertical lines appear when data voltages of the same polarity are applied in the vertical direction and data voltages of positive and negative polarities are different.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of preventing a coupling defect or a vertical string defect during high speed driving.

According to an embodiment of the present invention, a liquid crystal display device includes a plurality of pixels arranged in a matrix, a switching element connected to the pixels, a data line and a gate connected to the switching element. And a data driver for generating a data voltage and applying the data voltage to the data line, wherein the data lines are arranged in pairs on the left and right sides of the pixel, and the pair of data lines have different polarities having the same size. The data voltage is applied.

In this case, the switching elements of the pixel may be connected to only one data line of the pair of data lines, and the switching elements of two pixels vertically adjacent to the pixel column may be alternately connected to the pair of data lines. Can be.

Herein, the data driver may perform N × 2 inversion driving.

The pixel arrangement of the even-numbered columns of the pixel columns may be mirror symmetrical about the odd-numbered pixel columns and the data lines therebetween, and the data driver may perform N × 1 inversion driving.

Meanwhile, a liquid crystal display according to another exemplary embodiment of the present invention may include a plurality of pixels arranged in a matrix form and connected to the first and second subpixels, the plurality of pixels including first and second subpixels, respectively. A first and second switching elements, a data line and a gate line connected to the first and second subpixels, and a data driver for generating a data voltage and applying the data voltage to the data line, wherein the data line is formed of the pixel. They are arranged in pairs on the left and right, and data voltages of different polarities having the same magnitude are applied to the pair of data lines.

In this case, the first and second switching elements of the pixel may be connected to different data lines of the pair of data lines, respectively, and the data driver may perform N × 2 inversion driving.

Alternatively, the data driver may perform Nx1 inversion driving.

Further, pixel arrangements of even-numbered columns of the pixel columns may be mirror symmetric about odd-numbered pixel columns and data lines therebetween.

Further, the first and second switching elements of the adjacent first and second subpixels of the pixels adjacent in the column direction may be connected to the same data line.

On the other hand, the pixel arrangement of the even-numbered columns of the pixel columns may be mirror symmetric about the odd-numbered pixel columns and the data lines therebetween.

In this manner, high speed driving can be performed while preventing coupling defects and vertical string defects.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.
2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.
3 is a diagram illustrating a pixel arrangement of a liquid crystal display according to an exemplary embodiment of the present invention.
4 is a diagram illustrating an example of pixel arrangement of a liquid crystal display according to another exemplary embodiment of the present invention.
FIG. 5 is a diagram for describing a principle of eliminating coupling defects in the pixel arrangement illustrated in FIG. 4.
6A and 6B are views showing a modification of the pixel arrangement shown in FIG. 4.
7 is a diagram illustrating a pixel arrangement of a liquid crystal display according to another exemplary embodiment of the present invention.
8A to 8D are diagrams showing a modification of the pixel arrangement shown in FIG. 7.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: FIG.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

First, a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2. FIG.

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a pixel of a liquid crystal display device according to an embodiment of the present invention.

1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400 connected to the liquid crystal panel assembly 300, a data driver 500, a data driver A gradation voltage generator 800 connected to the gradation voltage generator 500, and a signal controller 600 for controlling the gradation voltage generator 800 and the gradation voltage generator 800.

The liquid crystal panel assembly 300 includes a plurality of signal lines G 1 -G n and D 1 -D m and a plurality of pixels PX connected to the signal lines G 1 -G n and D 1 -D m arranged in the form of a matrix . 2, the liquid crystal display panel assembly 300 includes lower and upper display panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G 1 -G n and D 1 -D m include a plurality of gate lines G 1 -G n for transferring gate signals (also referred to as "scan signals") and a plurality of data lines D 1 -D m ). The gate lines G 1 to G n extend in a substantially row direction and are substantially parallel to each other, and the data lines D 1 to D m extend in a substantially column direction and are substantially parallel to each other.

The pixel PX connected to each pixel PX, for example, the i-th (i = 1, 2, n) gate line G i and the j- Includes a switching element Q connected to a signal line G i D j and a liquid crystal capacitor Clc and a storage capacitor Cst connected thereto. The storage capacitor Cst can be omitted if necessary.

The switching element Q is a three terminal element such as a thin film transistor provided in the lower panel 100. The control terminal is connected to the gate line G i and the input terminal is connected to the data line D j And the output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200 as two terminals and the liquid crystal layer 3 between the two electrodes 191 and 270, . The pixel electrode 191 is connected to the switching element Q and the common electrode 270 is formed on the entire surface of the upper panel 200 to receive the common voltage Vcom. 2, the common electrode 270 may be provided on the lower panel 100. At this time, at least one of the two electrodes 191 and 270 may be linear or bar-shaped.

The storage capacitor Cst serving as an auxiliary capacitor of the liquid crystal capacitor Clc is formed by superimposing a separate signal line (not shown) and a pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween, A predetermined voltage such as the common voltage Vcom is applied to the separate signal lines. However, the storage capacitor Cst may be formed by overlapping the pixel electrode 191 with the previous gate line immediately above via an insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of primary colors (space division), or each pixel PX alternately displays a basic color (time division) So that the desired color is recognized by the spatial and temporal sum of these basic colors. Examples of basic colors include red, green, and blue. 2 shows that each pixel PX has a color filter 230 indicating one of the basic colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of space division. 2, the color filter 230 may be formed on or below the pixel electrode 191 of the lower panel 100. [

At least one polarizer (not shown) for polarizing light is attached to the outer surface of the liquid crystal panel assembly 300.

Referring again to FIG. 1, the gradation voltage generator 800 generates two sets of gradation voltages (or a set of reference gradation voltages) related to the transmittance of the pixel PX. One of the two has a positive value for the common voltage (Vcom) and the other has a negative value.

The gate driver 400 is connected to the gate lines G 1 -G n of the liquid crystal panel assembly 300 and supplies a gate signal composed of a combination of the gate-on voltage Von and the gate-off voltage Voff to the gate line G 1 -G n .

The data driver 500 is connected to the data lines D 1 -D m of the liquid crystal panel assembly 300 and selects the gradation voltage from the gradation voltage generator 800 and supplies it as a data signal to the data line D 1 -D m . However, when the gradation voltage generator 800 provides only a predetermined number of reference gradation voltages instead of providing all the voltages for all gradations, the data driver 500 divides the reference gradation voltage and supplies the gradation voltage And selects a data signal among them.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be directly mounted on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown) Or may be attached to the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP), or may be mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G 1 -G n , D 1 -D m and the thin film transistor switching element Q. It may be. In addition, the drivers 400, 500, 600, 800 may be integrated into a single chip, in which case at least one of them, or at least one circuit element constituting them, may be outside of a single chip.

The operation of the liquid crystal display device will now be described in detail.

The signal controller 600 receives an input control signal for controlling the display of the input image signals R, G, and B from an external graphic controller (not shown). Examples of the input control signal include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes at least one clock signal for controlling the output period of the scan start signal STV indicating the start of scanning and the gate-on voltage Von. The gate control signal CONT1 may further include an output enable signal OE that defines the duration of the gate on voltage Von.

The data control signal CONT2 includes a horizontal synchronization start signal STH for notifying the start of transmission of video data to the pixel PX of one row and a load for applying a data signal to the data lines D 1 to D m Signal LOAD and a data clock signal HCLK. The data control signal CONT2 is also an inverted signal which inverts the voltage polarity of the data signal with respect to the common voltage Vcom (hereinafter referred to as "the polarity of the data signal by reducing the voltage polarity of the data signal with respect to the common voltage" RVS).

The data driver 500 receives the digital video signal DAT for the pixel PX of one row and outputs the digital video signal DAT for the pixel PX in accordance with the data control signal CONT2 from the signal controller 600. [ ) To convert the digital video signal DAT into an analog data signal, and then applies the analog data signal to the corresponding data lines D 1 -D m .

Gate driver 400 is a signal control gate lines (G 1 -G n) is applied to the gate line of the gate-on voltage (Von), (G 1 -G n) in accordance with the gate control signal (CONT1) of from 600 The switching element Q is turned on. Then, the data signal applied to the data lines D 1 -D m is applied to the corresponding pixel PX through the turned-on switching element Q.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom appears as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The liquid crystal molecules have different arrangements according to the magnitude of the pixel voltage, and thus the polarization of light passing through the liquid crystal layer 3 changes. Such a change in polarization is caused by a change in the transmittance of light by the polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H ", which is the same as one cycle of the horizontal synchronization signal Hsync and the data enable signal DE), so that all the gate lines G 1 -G n On voltage Von is sequentially applied to all the pixels PX to display an image of one frame by applying a data signal to all the pixels PX.

At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled such that the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame ( "Frame inversion"). At this time, the polarity of the data signal flowing through one data line changes (for example, row inversion and dot inversion) depending on the characteristics of the inversion signal RVS in one frame, or the polarity of the data signal applied to one pixel row is different (For example, thermal inversion, dot inversion).

Next, the pixel arrangement of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 to 8B.

3 is a diagram illustrating a pixel arrangement of a liquid crystal display according to an exemplary embodiment of the present invention.

For convenience of description, a portion of the data line D 1 -D 7 and a portion of the gate line G j -1 -G j +2 are shown, and the data driver 500 includes the data line D 1 -D 7. The thermal reversal is performed as if the polarity is indicated above, and the thermal reversal at this time includes not only the positive and negative polarities alternately but also the case where the same polarity is repeated once. For example, two polarities alternately appear (+,-, +,-, +,-, ..), such as '+,-, +,-, +,-..' and '+, +,-,-'. It also includes cases where the polarity changes (N × 2 inversion) after the same polarity is repeated once, such as, +, +,-,-, +, +, .. '. Furthermore, even when a separate voltage is applied to only the leftmost data line to perform 1 + N × 2 inversion driving, the following description is simply referred to as N × 2 inversion driving. In addition, although the switching element Q of the pixel PX is connected to the data lines D 1 -D 7 and the gate lines D 1 -D 7 , G j-1 -G j + 2 , the pixel PX Will be described as being connected to two signal lines D 1 -D 7 and G j-1 -G j + 2 .

Referring to FIG. 3, one row of pixels PX is connected to right or left data lines D 1 -D 7 , and one column of pixels PX is right and left data lines D 1 -D 7 . Are alternately connected to. Accordingly, the polarity of the data voltage (hereinafter, referred to as 'pixel polarity') in the pixel PX alternates between positive and negative polarities, and thus causes dot inversion. Results. Accordingly, it is possible to prevent vertical line defects that appear when the polarities of the pixels PX in one column are the same.

4 is a diagram illustrating a pixel arrangement of a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 4, unlike FIG. 3, a pair of data lines D 1a , D 1b , D 2a , D 2b , D 3a , D 3b , D 4a , D 4b , and D on the left and right sides of each pixel PX. 5a , D 5b , D 6a , and D 6b are arranged, and the pixels PX are all connected to the data lines D 1b , D 2b , D 3b , D 4b , D 5b , and D 6b located on the right side. .

Accordingly, the polarities of the pixels PX in one row are alternately changed, and the polarities of the pixels PX in one column are the same. In this case, the pixel PX of the pair of data lines D 1a , D 1b , D 2a , D 2b , D 3a , D 3b , D 4a , D 4b , D 5a , D 5b , D 6a , and D 6b The polarity of the unconnected data lines D 1a , D 1b , D 2a , D 2b , D 3a , D 3b , D 4a , D 4b , D 5a , D 5b , D 6a , and D 6b is the pixel PX. The polarity of the data lines D 1a , D 1b , D 2a , D 2b , D 3a , D 3b , D 4a , D 4b , D 5a , D 5b , D 6a , and D 6b to which the is connected is opposite.

This is for example first data that belongs to a column line (D 1a, D 1b) to look, the right data line (D 1b), the data voltage (Vdtb) of negative polarity, on the left, the data lines (D 1a) of the positive The data voltage Vdta is applied, and this is shown in FIG. 5 when it is expressed based on the common voltage Vcom. That is, a data voltage having the same magnitude as that of the data voltage applied to the right data line D 1b and having the opposite polarity is applied to the left data line D 1a . In this way, the voltages applied to the parasitic capacitors cancel each other in each pixel PX so that a coupling defect does not occur.

6A and 6B illustrate modified examples of the pixel arrangement illustrated in FIG. 4.

In the pixel arrangement shown in FIG. 6A, the pixels PX in the same row have the same data lines D 1a , D 1b , D 2a , D 2b , D 3a , D 3b , D 4a , D 4b , D 5a , D 5b , Are connected to D 6a and D 6b , and the pixels PX in the same column have a pair of data lines D 1a , D 1b , D 2a , D 2b , D 3a , D 3b , D 4a , D 4b , and D 5a , D 5b , D 6a , D 6b ) in turn. In the pixel arrangement shown in FIG. 6B, the pixel arrangement of the odd-numbered columns is the same as the pixel arrangement shown in FIG. 8A, and the pixel arrangement of the even-numbered columns is mirror symmetric about the odd-numbered column and the data lines therebetween. For example, the pixel arrangement of the second column is mirror symmetric with the pixel arrangement of the first column about the data lines D 1b and D 2a .

In the pixel arrangement illustrated in FIG. 4, vertical line defects may occur due to the same polarity of the data voltages applied to the pixels PX in one column. In the pixel arrangement illustrated in FIGS. 6A and 6B, not only the coupling defect but also the vertical line defect Can also be prevented.

7 is a diagram illustrating a pixel arrangement of a liquid crystal display according to another exemplary embodiment, and FIGS. 8A to 8D are modified examples of the pixel arrangement illustrated in FIG. 7.

Referring to FIG. 7, in the pixel structures illustrated in FIGS. 4, 6A, and 6B, one pixel PX is formed around two subpixels PXa and PXb around the gate lines G j-1 to G j + 2 . Structure divided by) This is a structure currently being developed to improve side visibility, and is mainly used in a liquid crystal display device having a vertical alignment.

Two sub-pixels PXa and PXb constituting one pixel PX have different data lines D 1a , D 1b , D 2a , D 2b , D 3a , D 3b , D 4a , D 4b , D 5a , and D 5b , D 6a , and D 6b ), and this structure is repeated in the row direction and the column direction, so that the polarity of the pixel PX appears as shown.

Therefore, a pair of data lines D 1a , D 1b , D 2a , D 2b , D 3a , D 3b , D 4a , D 4b , D 5a , D 5b , D 6a , and D intersect the pixel PX. Since the polarities of 6b ) are opposite to each other, no coupling defects are generated, and since the polarities of the columns of pixels PX are alternately repeated, no vertical line defects occur.

8A is the same as the pixel arrangement shown in FIG. 7. However, the polarities of the applied data voltages are different, and therefore, the polarities of the pixels PX are different in the same structure. That is, in the pixel arrangement shown in FIG. 7, the polarity of the pixels PX is positive and negative in the row direction and the column direction, but in the pixel arrangement shown in FIG. 8A, the polarity is the same in the row direction. However, even in this case, a coupling defect or a vertical line defect can be prevented.

In the case of FIG. 8B, the two subpixels PXa and PXb constituting one pixel PX have different data lines D 1a , D 1b , D 2a , D 2b , D 3a , D 3b , D 4a , D 4b , D 5a , D 5b , D 6a , D 6b ). However, two adjacent subpixels of pixels adjacent in the column direction have the same data lines D 1a , D 1b , D 2a , D 2b , D 3a , D 3b , D 4a , D 4b , D 5a , D 5b , D 6a , D 6b ). For example, the lower subpixel PXb of the first column (j-1) and the upper subpixel PXa of the adjacent j row are connected to the same data line D 1a , and the lower part of the j row is The pixel PXb and the upper subpixel PXa of the (j + 1) row adjacent thereto are connected to the same data line D 1b .

In the case of FIG. 8C, the pixel arrangement of the odd-numbered columns is the same as the pixel arrangement shown in FIG. 8B, and the pixel arrangement of the even-numbered columns is mirror symmetric about the odd-numbered columns and the data lines therebetween. For example, the pixel arrangement of the second column is mirror symmetric with the pixel arrangement of the first column about the data lines D 1b and D 2a .

In the case of FIG. 8D, the pixel arrangement of the odd-numbered columns is the same as that shown in FIG. 7A. That is, the two subpixels PXa and PXb constituting one pixel PX may have different data lines D 1a , D 1b , D 2a , D 2b , D 3a , D 3b , D 4a , D 4b , and D 5a. , D 5b , D 6a , D 6b ), and this structure is repeated in the column direction. The pixel arrangement of the even-numbered columns is mirror symmetric about the odd-numbered columns and the data lines therebetween as shown in FIG. 8C.

As described above, the pair of data lines D 1a , D 1b , D 2a , D 2b , D 3a , D 3b , D 4a , D 4b , D 5a , D 5b , D 6a , and D 6b have the same size. It can be seen that coupling defects and vertical stripe defects are prevented by applying data voltages of different polarities and by alternately repeating polarities of the pixels in the column direction.

3: liquid crystal layer 100: lower panel
191: pixel electrode 200: upper display panel
230: color filter 270: common electrode
300: liquid crystal panel assembly 400: gate driver
500: Data driver 600: Signal controller
800: gray voltage generator
R, G, B: Input image data DE: Data enable signal
MCLK: Main Clock Hsync: Horizontal Sync Signal
Vsync: Vertical Sync Signal CONT1: Gate Control Signal
CONT2: data control signal DAT: digital video signal
Clc: Liquid Crystal Capacitor Cst: Keeping Capacitor
Q: switching element PX: pixel
PXa, PXb: subpixel

Claims (19)

  1. A pixel including a first subpixel including a first subpixel electrode and a first thin film transistor, and a second subpixel including a second subpixel electrode and a second thin film transistor;
    A third subpixel, a fourth subpixel electrode, and a fourth subpixel electrode positioned adjacent to a lower side of the pixel including the first subpixel and the second subpixel and including a third subpixel electrode and a third thin film transistor; An adjacent pixel including a fourth subpixel including a thin film transistor;
    A first gate line electrically connected to the first subpixel and the second subpixel, extending in a first direction, and transmitting a gate signal;
    A second gate line electrically connected to the third subpixel and the fourth subpixel, extending in the first direction, and transmitting the gate signal;
    A first data line electrically connected to the first subpixel and the fourth subpixel, extending in a second direction, and transferring a first data voltage; And
    A second data line electrically connected to the second subpixel and the third subpixel, extending in the second direction, and transmitting a second data voltage;
    The first subpixel electrode is spaced apart from the second subpixel electrode in a plan view,
    The third subpixel electrode is spaced apart from the fourth subpixel electrode in a plan view,
    The first thin film transistor is connected to the first subpixel electrode positioned above the gate line, and the second thin film transistor is connected to the second subpixel electrode positioned below the gate line,
    The third thin film transistor is connected to the third subpixel electrode positioned above the second gate line, and the fourth thin film transistor is connected to the fourth subpixel electrode positioned below the second gate line. There is,
    The first gate line is positioned between the first subpixel and the second subpixel.
    The second gate line is positioned between the third subpixel and the fourth subpixel.
    And the first subpixel and the second subpixel are positioned to correspond to the first color filter.
  2. In claim 1,
    And the first data voltage is different from the second data voltage, and the first data voltage and the second data voltage are obtained from one image information.
  3. 3. The method of claim 2,
    The first data voltage has a polarity opposite to that of the second data voltage.
  4. 4. The method of claim 3,
    And one of the first data line and the second data line is located at the left side of the pixel, and the other is located at the right side of the pixel.
  5. 5. The method of claim 4,
    And the first subpixel and the second subpixel are positioned between the first data line and the second data line.
  6. 4. The method of claim 3,
    And the first subpixel and the second subpixel are positioned between the first data line and the second data line.
  7. 3. The method of claim 2,
    And one of the first data line and the second data line is located at the left side of the pixel, and the other is located at the right side of the pixel.
  8. In claim 7,
    And the first subpixel and the second subpixel are positioned between the first data line and the second data line.
  9. 3. The method of claim 2,
    And the first subpixel and the second subpixel are positioned between the first data line and the second data line.
  10. In claim 1,
    The first data voltage has a polarity opposite to that of the second data voltage.
  11. 11. The method of claim 10,
    And one of the first data line and the second data line is located at the left side of the pixel, and the other is located at the right side of the pixel.
  12. 12. The method of claim 11,
    And the first subpixel and the second subpixel are positioned between the first data line and the second data line.
  13. 11. The method of claim 10,
    And the first subpixel and the second subpixel are positioned between the first data line and the second data line.
  14. In claim 1,
    And one of the first data line and the second data line is located at the left side of the pixel, and the other is located at the right side of the pixel.
  15. The method of claim 14,
    And the first subpixel and the second subpixel are positioned between the first data line and the second data line.
  16. In claim 1,
    And the first subpixel and the second subpixel are positioned between the first data line and the second data line.
  17. delete
  18. delete
  19. delete
KR1020120070920A 2012-06-29 2012-06-29 Liquid crystal display KR101272338B1 (en)

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KR20050054858A (en) * 2003-12-05 2005-06-10 샤프 가부시키가이샤 Liquid crystal display
KR20050089298A (en) * 2004-03-04 2005-09-08 삼성전자주식회사 Thin film transistor array panel having reduced data lines

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KR20050054858A (en) * 2003-12-05 2005-06-10 샤프 가부시키가이샤 Liquid crystal display
KR20050089298A (en) * 2004-03-04 2005-09-08 삼성전자주식회사 Thin film transistor array panel having reduced data lines

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