KR20080046980A - Liquid crystal display - Google Patents

Abstract

An LCD device is provided to reduce power consumption of the LCD device by disabling a graphic controller when still images are inputted. An LCD(Liquid Crystal Display) device includes a display panel(300), an MPU(Micro Process Unit), a graphic controller(920), a signal controller(600), and a data driver(500). The display panel includes plural pixels connected to gate and data lines. The MPU receives image signals from outside. The graphic controller is connected to the MPU. The signal controller, which is connected to the graphic controller, includes a memory and a clock signal generator. The data driver generates data voltages and applies the generated data voltages. When the image signals are still images, the graphic controller is idle. The signal controller supplies the same image data to the data driver according to clock signals from the clock signal generator.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

With reference to the accompanying drawings will be described in detail the embodiments of the present invention to make the present invention clear.

1 is a schematic diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a waveform diagram of various signals used in a liquid crystal display according to an exemplary embodiment of the present invention.

<Description of Drawing>

3: liquid crystal layer 100: lower display panel

191: pixel electrode 200: upper display panel

230: color filter 270: common electrode

300: liquid crystal panel assembly 400: gate driver

500: data driver 600: signal controller

650: FPC 700: integrated chip

800: gray voltage generator

R, G, B: Input image data DE: Data enable signal

MCLK: main clock signal ZCLK: clock signal

Hsync: Horizontal Sync Signal Vsync: Vertical Sync Signal

CONT1: gate control signal

CONT2: data control signals DAT1, DAT2, DAT3: digital video signals

Clc: Liquid Crystal Capacitor Cst: Keeping Capacitor

Q: switching element PX: pixel

The present invention relates to a liquid crystal display device.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto.

In such a liquid crystal display, a voltage is applied to two electrodes to form an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to control the transmittance of light passing through the liquid crystal layer to obtain a desired image. At this time, in order to prevent deterioration caused by an electric field applied to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row, or dot, or the common voltage and the data voltage are reversed. Invert all

Among such liquid crystal display devices, small and medium sized display devices such as mobile phones receive an image signal from the outside and are connected to a micro process unit (MPU) corresponding to the central processing unit, a graphic controller connected thereto, and a graphic controller and drive the display panel. It includes a driving chip.

In this case, even when the liquid crystal display displays a still image, the graphic controller continuously transmits an image signal to the driving chip, thereby increasing power consumption.

Therefore, the technical problem to be achieved by the present invention is to provide a liquid crystal display device that can solve the problems of the prior art.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a display panel unit including a plurality of pixels connected to a gate line and a data line, and a micro process unit (MPU) that receives an image signal from an external source. A graphic controller connected to the MPU, a signal controller connected to the graphic controller and including a memory and a clock signal generator, and a data driver generating a data voltage and applying the data voltage to the data line;

When the image signal from the outside is a still image, the graphic controller is in an idle state, and the signal controller provides the same image data to the data driver in accordance with the clock signal generated by the clock signal generator.

In this case, the same image data may be output from the memory.

The liquid crystal display may further include a gate driver configured to generate a gate voltage and apply the gate voltage to the gate line, and may further include a driving circuit chip mounted on the display panel.

In this case, the driving circuit chip may include the signal controller, the data driver, and the gate driver.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a schematic diagram of a liquid crystal display according to an embodiment of the present invention, FIG. 2 is a block diagram of a liquid crystal display according to an embodiment of the present invention, and FIG. 3 is a liquid crystal display according to an embodiment of the present invention. 4 is an equivalent circuit diagram of one pixel of a device, and FIG. 4 is a waveform diagram of various signals used in a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention may include a display panel 300, a flexible printed circuit film (FPC) 650 attached to the display panel 300, and a display panel 300. An integrated chip 700 mounted.

The FPC 650 is attached near one side of the display panel 300. In addition, when the FPC 650 is folded in the assembled state, the display panel 300 has an opening 690 that exposes a part of the display panel 300. The lower part of the opening 690 is provided with an input unit 660 through which a signal from the outside is input, and a plurality of protrusions 660 for electrical connection between the protrusion 660, the integrated chip 700, the integrated chip 700, and the display panel unit 300. The signal lines SL1 and SL2 are provided, and the signal lines are substantially wider at points connected to the integrated chip 700 and attached to the display panel 300 to form pads (not shown). In this case, the signal line SL1 is connected to the input unit 900 to transmit various signals to the integrated chip 700.

The display panel 300 may include a display area 310 and a peripheral area 320 constituting a screen, and the peripheral area 320 may include a light blocking layer (not shown) (black matrix) for blocking light. have. FPCs 650 are attached to the light shielding regions 320, respectively.

As shown in FIG. 2, the display panel unit 300 is connected to a plurality of display signal lines including a plurality of gate lines G ₁ -G _n and a plurality of data lines D ₁ -D _m , and is approximately matrix. It includes a plurality of pixels arranged in the form of, most of the pixels and the display signal lines (G ₁ -G _n , D ₁ -D _m ) are located in the display area 310.

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n transmitting gate signals (also called scan signals) and data lines D ₁ transferring data signals. includes -D _m). gate lines (G ₁ -G _n) extend in a substantially row direction and are substantially parallel to the data lines (D ₁ -D _m) to each other and extending substantially in a column direction are substantially parallel to each other The display signal lines G ₁ -G _n and D ₁ -D _m are generally wide at a point connected to the FPC 650 to form a pad (not shown), and the display panel unit 300 and the FPC 650. Is attached with an anisotropic conductive film (not shown) for electrical connection of these pads.

Pixels connected to each pixel PX, for example, the i-th (i = 1, 2,, n) gate line G _i and the j-th (j = 1, 2,, m) data line D _j ( PX includes a switching element Q connected to the signal lines G _i and D _j , a liquid crystal capacitor Clc and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 3, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line G _i-1 directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 3 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike in FIG. 3, the color filter 230 may be disposed above or below the pixel electrode 191 of the lower panel 100.

The liquid crystal panel assembly 300 is provided with at least one polarizer (not shown).

Referring back to FIG. 2, the gray voltage generator 800 generates an entire gray voltage related to the transmittance of the pixel PX or a limited number of gray voltages (hereinafter referred to as a “reference gray voltage”). The reference gray level voltage may include a positive value and a negative value with respect to the common voltage Vcom.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ).

Data driver 500 is connected with the data lines (D ₁ -D _m) of the liquid crystal panel assembly 300, select a gray voltage from the gray voltage generator 800 and the data lines do this as a data voltage (D ₁ -D _m ). However, when the gray voltage generator 800 does not provide all the gray voltages but provides only a limited number of reference gray voltages, the data driver 500 divides the reference gray voltages to generate a desired data voltage.

The signal controller 600 includes a memory 650 and controls the gate driver 400, the data driver 500, and the like.

The integrated chip 700 receives a signal from the input unit 900 including the MPU 910 and the graphic controller 920 through the signal line SL1 and processes the signal in the peripheral area 320 of the display panel 300. These are controlled by supplying the display panel unit 300 through the wires, and includes the gate driver 400, the data driver 500, the gray voltage generator 800, the signal controller 600, and the like illustrated in FIG. 2. .

Next, the display operation of the liquid crystal display will be described in more detail.

The MPU 910 and the graphic controller 920 convert image data from the outside and provide the same to the signal controller 600. For example, the MPU 910 and the graphic controller 920 convert the external image data into 8-bit image data DAT1. In addition, the graphics controller 920 converts the 8-bit image data DAT1 into 6-bit image data DAT2 and then inputs various input control signals together with the image data DAT2 to the signal controller 600. Provides (DE, Hsync, Vsync, MCLK).

The signal controller 600 inputs an input control signal for controlling the input image signal DAT2 and its display from the graphic controller 920, for example, a vertical sync signal Vsync, a horizontal sync signal Hsync, and a main clock signal MCLK. ) And a data enable signal DE to generate a gate control signal CONT1 and a data control signal CONT2 based on the input control signal and the input image signal DAT2, and display the image signal DAT2. After appropriately processing according to the operating conditions of the unit 300, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT3 are transferred to the data driver 500. Export.

The gate control signal CONT1 includes a scan start signal STV for instructing the output of the gate-on voltage Von, a gate clock signal CPV for controlling the output timing of the gate-on voltage Von, and a gate-on voltage Von. Output enable signal (OE) or the like that defines the duration of the &lt; RTI ID = 0.0 &gt;

The data control signal CONT2 includes a horizontal synchronization start signal STH indicating the start of input of the image data DAT3, a load signal LOAD for applying a corresponding data voltage to the data lines D ₁ -D _m , and a common voltage ( And an inversion signal RVS and a data clock signal HCLK for inverting the polarity of the data voltage (hereinafter referred to as the polarity of the data voltage by reducing the polarity of the data voltage with respect to the common voltage). In the drawing, the data clock signal HCLK is separately shown.

The data driver 500 sequentially receives the image data DAT3 corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and among the gray voltages from the gray voltage generator 800. By selecting the gray scale voltage corresponding to each image data DAT3, the image data DAT3 is converted into the corresponding data voltage and applied to the data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

The difference between the data voltage applied to the pixel and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage. As a result, the polarization of light passing through the liquid crystal layer 3 changes. This change in polarization is represented by a change in transmittance of light by polarizers attached to the display panels 100 and 200.

After one horizontal period (or 1H &quot;) (one period of the horizontal synchronization signal Hsync, the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 move to the next row. The same operation is repeated for the pixels In this manner, the gate-on voltages Von are sequentially applied to all the gate lines G ₁ -G _n during one frame to apply the data voltages to all the pixels. In particular, when one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data voltage applied to each pixel is opposite to the polarity of the previous frame ("frame" Inversion "). In this case, the polarity of the data voltage flowing through one data line is changed according to the characteristics of the inversion signal RVS (eg, column inversion, point inversion), or the data voltage applied to one pixel row within one frame. polarity There can be different (eg row inversion, dot inversion).

On the other hand, when the image data DAT1 is a still image, the graphic controller 920 sends the control signal CONT3 to the signal controller 600 and enters an idle state at the same time. Accordingly, various control signals MCLK, Hsync, and Vsync output from the graphic controller 920 also change to a low state. At this time, since the data clock signal HCLK is made based on the main clock signal MCLK, the data clock signal HCLK is no longer generated. Therefore, the clock signal ZCLK, which replaces the same, is generated by itself, and the data DAT3 is transferred to the data driver 500.

The clock signal ZCLK may be generated by the clock signal generator 670 located in the signal controller 600. Of course, the clock signal generator 670 may be located outside the signal controller 600 as a separate chip.

The image data DAT3 may use the previous image data stored in the memory 650 as it is.

As such, when the still image is input, the graphics controller 920 is made idle, thereby lowering power consumption by making various signals MCLK, Hsync, and Vsync low.

As described above, in the case of a still image, the graphics controller may be idled to reduce power consumption of the liquid crystal display.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (5)

A display panel unit including a plurality of pixels connected to the gate line and the data line; MPU (micro process unit) receiving an image signal from the outside, A graphics controller connected to the MPU, A signal controller connected to the graphic controller and including a memory and a clock signal generator; and A data driver for generating a data voltage and applying the data voltage to the data line Including; When the image signal from the outside is a still image, the graphic controller is in an idle state, and the signal controller provides the same image data to the data driver according to the clock signal generated by the clock signal generator. Liquid crystal display. In claim 1, The same image data is output from the memory. In claim 2, And a gate driver configured to generate a gate voltage and apply the gate voltage to the gate line. In claim 3, And a driving circuit chip mounted on the display panel. In claim 4, The driving circuit chip includes the signal controller, the data driver, and the gate driver.

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