KR20080057442A - Liquid crystal display - Google Patents

Abstract

An LCD(Liquid Crystal Display) is provided to locate an inspection pad at a display panel portion, thereby securing a space in an FPC(Flexible Printed Circuit) and having the margin in design. A display panel member(300) includes plural pixels connected to a gate line and a data line. A driving chip(700) drives the display panel member and is mounted to the display panel member. An FPC(650) is connected with the display panel member. The first inspection pads(TP1,TP2) are arranged to the left and right sides of the display panel member by one pair. The inspection pad pair is connected with a pair of inspection lines(651,652) arranged at the display panel member and the FPC. The display panel member also includes the second inspection pad pair(TP3,TP4). The driving chip includes a gate driving member for generating a gate signal and for applying the gate signal to the gate line. A data driving member generates a data signal and applies the data signal to the data line.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

With reference to the accompanying drawings will be described in detail the embodiments of the present invention to make the present invention clear.

1 is a schematic diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

4 and 5 are enlarged views of a part of the liquid crystal display shown in FIG. 1.

<Description of Drawing>

3: liquid crystal layer 100: lower display panel

191: pixel electrode 200: upper display panel

230: color filter 270: common electrode

300: liquid crystal panel assembly 400: gate driver

500: data driver 600: signal controller

650: FPC 700: integrated chip

800: gray voltage generator

R, G, B: Input image data DE: Data enable signal

MCLK: main clock signal

Hsync: Horizontal Sync Signal Vsync: Vertical Sync Signal

CONT1: gate control signal

CONT2: data control signal DAT: digital video signal

Clc: Liquid Crystal Capacitor Cst: Keeping Capacitor

Q: switching element PX: pixel

The present invention relates to a liquid crystal display device.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto.

In such a liquid crystal display, a voltage is applied to two electrodes to form an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to control the transmittance of light passing through the liquid crystal layer to obtain a desired image. At this time, in order to prevent deterioration caused by an electric field applied to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row, or dot, or the common voltage and the data voltage are reversed. Invert all

Among such liquid crystal display devices, small and medium-sized liquid crystal display devices such as mobile phones control display panels such as liquid crystal panel assemblies, flexible printed circuit boards (FPCs) having wires for transmitting input signals from the outside, and controlling them. It includes an integrated chip (integrated chip) to.

The integrated chip generates a signal for controlling the display panel and a driving signal, and is mainly mounted in the form of a chip on glass (COG) on the display panel. The integrated chip includes a gate driver for generating a gate signal, a data driver for generating a data voltage, a signal controller for controlling them, and recently a DC / DC converter for generating a driving voltage.

As a result, the number of wires connected to the integrated chip has increased considerably compared to the past, which leads to some unexpected defects.

On the other hand, after manufacturing a liquid crystal display device, a pair of pads are put in FPC in order to measure resistance, such as FPC in which wiring is formed. That is, resistance is measured by applying voltage and current to one pad and measuring it at the other pad. If the resistance is too large, the signal cannot be delivered properly, so it is judged as bad.

By the way, the test pad for measuring this is arranged only on one side of the remaining FPC with increased wiring is inevitable to the test on the other side.

Therefore, the technical problem to be achieved by the present invention is to provide a liquid crystal display device that can solve the problems of the prior art.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a display panel unit including a plurality of pixels connected to a gate line and a data line, and a driving unit mounted on the display panel unit while driving the display panel unit. A chip, a flexible printed circuit board (FPC) connected to the display panel, and a pair of first test pads disposed on the left and right sides of the driving chip, wherein the pair of test pads are connected to the display panel. It is connected to the inspection line arrange | positioned over the said FPC.

In this case, the display panel may further include a pair of second test pads disposed near the first test pad, and the second test pad may be connected to a test line disposed on the display panel.

The driving chip may include a gate driver for generating a gate signal and applying the gate signal and a data driver for generating a data voltage and applying the data voltage to the data line.

A third test pad for measuring the gate signal and the data voltage may be disposed in the display panel.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a schematic diagram of a liquid crystal display according to an embodiment of the present invention, FIG. 2 is a block diagram of a liquid crystal display according to an embodiment of the present invention, and FIG. 3 is a liquid crystal display according to an embodiment of the present invention. An equivalent circuit diagram for one pixel of the device.

Reference numeral 300 denotes a liquid crystal panel assembly or a display panel unit.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention may include a display panel 300, a flexible printed circuit film (FPC) 650 attached to the display panel 300, and a display panel 300. An integrated chip 700 mounted.

The FPC 650 is attached near one side of the display panel 300. In addition, the FPC 650 has an opening 690 that exposes a part of the display panel 300 when the FPC 650 is folded backward. The lower part of the opening 690 is provided with an input unit 660 through which a signal from the outside is input, and a plurality of input units 660 for electrical connection between the input unit 660, the integrated chip 700, the integrated chip 700, and the display panel unit 300 are provided. The signal lines SL1 and SL2 are provided, and the signal lines are substantially wider at points connected to the integrated chip 700 and attached to the display panel 300 to form pads (not shown). In this case, the signal line SL1 is connected to the input unit 660 to transmit various signals to the integrated chip 700.

The display panel 300 may include a display area 310 and a peripheral area 320 constituting a screen, and the peripheral area 320 may include a light blocking layer (not shown) (black matrix) for blocking light. have. FPCs 650 are attached to the light shielding regions 320, respectively.

As shown in FIG. 2, the display panel unit 300 is connected to a plurality of display signal lines including a plurality of gate lines G ₁ -G _n and a plurality of data lines D ₁ -D _m , and is approximately matrix. And a plurality of pixels PX arranged in the form of, wherein most of the pixels PX and the display signal lines G ₁ -G _n and D ₁ -D _m are positioned in the display area 310.

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n transmitting gate signals (also called scan signals) and data lines D ₁ transferring data signals. includes -D _m). gate lines (G ₁ -G _n) extend in a substantially row direction and are substantially parallel to the data lines (D ₁ -D _m) to each other and extending substantially in a column direction are substantially parallel to each other The display signal lines G ₁ -G _n and D ₁ -D _m are generally wide at a point connected to the FPC 650 to form a pad (not shown), and the display panel unit 300 and the FPC 650. Is attached with an anisotropic conductive film (not shown) for electrical connection of these pads.

Pixels connected to each pixel PX, for example, the i-th (i = 1, 2,, n) gate line G _i and the j-th (j = 1, 2,, m) data line D _j ( PX includes a switching element Q connected to the signal lines G _i and D _j , a liquid crystal capacitor Clc and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 3, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line G _i-1 directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 3 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike in FIG. 3, the color filter 230 may be disposed above or below the pixel electrode 191 of the lower panel 100.

The liquid crystal panel assembly 300 is provided with at least one polarizer (not shown).

Referring back to FIG. 2, the gray voltage generator 800 generates an entire gray voltage related to the transmittance of the pixel PX or a limited number of gray voltages (hereinafter referred to as a “reference gray voltage”). The reference gray level voltage may include a positive value and a negative value with respect to the common voltage Vcom.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ).

Data driver 500 is connected with the data lines (D ₁ -D _m) of the liquid crystal panel assembly 300, select a gray voltage from the gray voltage generator 800 and the data lines do this as a data voltage (D ₁ -D _m ). However, when the gray voltage generator 800 does not provide all the gray voltages but provides only a limited number of reference gray voltages, the data driver 500 divides the reference gray voltages to generate a desired data voltage.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

The integrated chip 700 controls the signals by inputting and processing signals from the outside through the signal line SL1 to the display panel unit 300 through the wiring provided in the peripheral area 320 of the display panel unit 300. 2 includes a gate driver 400, a data driver 500, a gray voltage generator 800, a signal controller 600, and the like.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 is configured to control the input image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync and a horizontal synchronization signal ( The gate control signal CONT1 and the data control signal CONT2 based on the input control signal and the input image signals R, G, and B by receiving the Hsync, the main clock signal MCLK, and the data enable signal DE, etc. ), The image signals R, G, and B are appropriately processed according to the operating conditions of the display panel 300, and then the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 is generated. The processed image signal DAT is sent to the data driver 500.

The gate control signal CONT1 includes a scan start signal STV for instructing the output of the gate-on voltage Von, a gate clock signal CPV for controlling the output timing of the gate-on voltage Von, and a gate-on voltage Von. Output enable signal (OE) or the like that defines the duration of the &lt; RTI ID = 0.0 &gt;

The data control signal CONT2 includes a horizontal synchronization start signal STH indicating the start of input of the image data DAT, a load signal LOAD for applying a corresponding data voltage to the data lines D ₁ -D _m , and a common voltage ( And an inversion signal RVS and a data clock signal HCLK for inverting the polarity of the data voltage (hereinafter referred to as the polarity of the data voltage by reducing the polarity of the data voltage with respect to the common voltage). In the drawing, the data clock signal HCLK is separately shown.

The data driver 500 sequentially receives image data DAT corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and among the gray voltages from the gray voltage generator 800. By selecting the gray scale voltage corresponding to each image data DAT, the image data DAT is converted into a corresponding data voltage and applied to the data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

The difference between the data voltage applied to the pixel and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage. As a result, the polarization of light passing through the liquid crystal layer 3 changes. This change in polarization is represented by a change in transmittance of light by polarizers attached to the display panels 100 and 200.

After one horizontal period (or 1H &quot;) (one period of the horizontal synchronization signal Hsync, the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 move to the next row. The same operation is repeated for the pixels In this manner, the gate-on voltages Von are sequentially applied to all the gate lines G ₁ -G _n during one frame to apply the data voltages to all the pixels. In particular, when one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data voltage applied to each pixel is opposite to the polarity of the previous frame ("frame" Inversion "). In this case, the polarity of the data voltage flowing through one data line is changed according to the characteristics of the inversion signal RVS (eg, column inversion, point inversion), or the data voltage applied to one pixel row within one frame. polarity There can be different (eg row inversion, dot inversion).

Next, a liquid crystal display according to an exemplary embodiment of the present invention will be described in more detail with reference to FIGS. 4 and 5.

4 and 5 are enlarged views of a part of the liquid crystal display shown in FIG. 1, and are shown in an enlarged manner around the integrated chip 700.

4, a pair of test pads TP1, TP2, TP3, and TP4 are disposed on the left and right sides of the integrated chip 700, respectively. Each pair of test pads TP1, TP2, TP3, and TP4 are connected to each other through test lines 651 and 652. That is, the two test pads TP1 and TP2 are connected to each other through the test line 651 and the two test pads TP3 and TP4 are connected to each other through the test line 652.

In the drawing, these inspection lines 651 and 652 are connected as one at the connection portion of the display panel 300 and the FPC 650, but are actually connected through the connection pads described above.

In addition, other inspection lines together with the inspection lines 651 and 652 may be disposed only on the display panel unit 300, and in this case, only the resistance of the wiring disposed on the display panel unit 300 may be measured.

At this time, for example, a signal line SLL1 formed in the display panel 300 and the FPCC 650 by applying a current through the test pad TP1 and measuring a potential difference between the two pads TP1 and TP2 to obtain a resistance value. , SLL2) can be estimated.

Therefore, in the related art, since the test pad is disposed on the FPC 650 and only on one side, the space required for arranging the wiring is reduced, particularly in the case of the small and medium-sized liquid crystal display, and there is a design difficulty. In addition, since the resistance is measured by placing the test pad on only one side, the resistance on the opposite side cannot be measured, thereby reducing the reliability.

However, in the exemplary embodiment of the present invention, design constraints may be overcome by placing the test pads on the display panel 300, and by placing a pair of test pads TP1-TP4 on both sides of the integrated chip 700. Both can be measured to improve reliability.

Similarly, in FIG. 5, test pads TP5, TP6, and TP7 for measuring various signals exiting from the integrated chip 700 to the display panel unit 300, for example, a power supply, a gate signal, and a data signal, are disposed. It was shown that the abnormality of the signal can be confirmed. That is, these signals were also measured through the test pads disposed on the FPC 650, but when placed on the display panel 300 as in the embodiment according to the present invention, the space is secured in the FPC 650 to provide a design margin ( margin).

In this manner, the test pad may be provided on the display panel 300 to allow space in the FPC 650 to allow design margin.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (4)

A display panel unit including a plurality of pixels connected to the gate line and the data line; A driving chip which drives the display panel and is mounted on the display panel; A flexible printed circuit board (FPC) connected to the display panel; First inspection pads disposed on the left and right sides of the driving chip; Including, The pair of test pads are connected to a test line arranged over the display panel portion and the FPC. Liquid crystal display. In claim 1, The display panel further includes a pair of second test pads disposed near the first test pad, The second test pad is connected to a test line on the display panel. Liquid crystal display. In claim 2, The driving chip includes a gate driver for generating a gate signal and applying the gate signal and a data driver for generating a data voltage and applying the data voltage to the data line. Liquid crystal display. In claim 3, And a third test pad configured to measure the gate signal and the data voltage on the display panel.

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