KR20080048161A - Liquid crystal display and test method for the same - Google Patents

Abstract

An LCD(Liquid Crystal Display) and a test method thereof are provided to determine a fault or non-fault of a signal line exactly and quickly by simultaneously applying a test signal to a test pad and a data pad, thereby improving an yield by omitting a gross test. Plural data lines(DL) transmit data signals. A data pad unit(DPG) includes data pads(DP) respectively connected to the data lines. A signal line(SL) is connected to each data pad. Plural test lines(TL) are connected to the signal line in a predetermined unit. A test pad unit(TPG) includes test pads(TP) connected to each test line. To the test pad and the data pad, test signals are simultaneously and separately applied.

Description

Liquid crystal display and test method thereof {LIQUID CRYSTAL DISPLAY AND TEST METHOD FOR THE SAME}

With reference to the accompanying drawings will be described in detail the embodiments of the present invention to make the present invention clear.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a schematic diagram of the liquid crystal display shown in FIG. 1.

FIG. 4 is an enlarged view of a portion of the liquid crystal display shown in FIG. 3.

<Description of Drawing>

3: liquid crystal layer 100: lower display panel

191: pixel electrode 200: upper display panel

230: color filter 270: common electrode

300: liquid crystal panel assembly 400: gate driver

500: data driver 600: signal controller

800: gray voltage generator

R, G, B: Input image data DE: Data enable signal

MCLK: Main Clock Hsync: Horizontal Sync Signal

Vsync: Vertical Sync Signal CONT1: Gate Control Signal

CONT2: data control signal DAT: digital video signal

Clc: Liquid Crystal Capacitor Cst: Keeping Capacitor

Q: switching element TP: inspection pad

DP: data pad

The present invention relates to a liquid crystal display device and an inspection method thereof.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto.

In such a liquid crystal display, a voltage is applied to two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to control the transmittance of light passing through the liquid crystal layer to obtain a desired image. In this case, in order to prevent degradation caused by an electric field applied to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row by pixel, or pixel by pixel.

In the process of manufacturing the liquid crystal display, if there is a disconnection in the display signal lines such as the gate line or the data line, these are filtered in advance through a predetermined inspection. These types of inspections include array tests, visual inspection (VI) tests, gross tests, and module tests.

The array test is a test that applies a constant voltage before separating into individual cells and checks whether the display signal line is disconnected through the presence or absence of an output voltage. The VI test separates into individual cells and then applies a constant voltage. It is a test to check whether the signal line is disconnected while looking at the human eye. The gross test is a test that checks the quality and disconnection of the display signal line through the display state by applying a constant voltage before combining the upper panel and the lower panel and mounting the driving circuit. Finally, it is a test to find out whether the driving circuit works properly.

In this case, it is difficult to determine whether the test line is defective or the display signal line is defective because the test line is damaged due to a scratch or the like in the process of separating into individual cells in the VI test, thereby failing to properly transmit the test signal. More precise inspections are made during the gross test phase, which applies a test signal to all data pads to determine if the display signal lines are defective. This eliminates the need for gross testing, which increases production time and lowers yields.

Accordingly, an object of the present invention is to provide a liquid crystal display device and an inspection method thereof that can improve yield.

According to an embodiment of the present invention, a liquid crystal display device includes: a data pad unit including a plurality of data lines transferring data signals, a data pad connected to the data lines, and each data pad; And a test pad portion including a signal line connected to the test line, a plurality of test lines connected to the signal line in a predetermined unit, and test pads connected to the respective test lines, simultaneously with the test pad and the data pad. Separately, a test signal is applied.

The test pad part may be alternately positioned with the data pad part, and the test pad part may be one more than the number of the data pad part.

The liquid crystal display includes a gate line for transmitting a gate signal, a gate pad unit including a gate pad connected to the gate line, a signal line connected to each of the gate pads, and a signal unit connected to the signal line in a predetermined unit. The apparatus may further include a test pad unit including a plurality of test lines, and test pads connected to the test lines, and a test signal may be applied to the test pad and the gate pad simultaneously and separately.

In addition, the test pad part may be alternately positioned with the gate pad part, and the test pad part may be one more than the number of the gate pad part.

On the other hand, according to an embodiment of the present invention, a plurality of data lines for transmitting a data signal, a data pad including a data pad connected to each of the data line, a signal line connected to each of the data pad, the signal line An inspection method of a liquid crystal display device comprising: a test pad unit including a plurality of test lines connected to the test units in a predetermined unit, and a test pad connected to each test line, simultaneously and separately from the test pad and the data pad. The method may include applying a test signal.

In this case, the test pad part may be alternately positioned with the data pad part, and the test pad part may be one more than the number of the data pad part.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel in the liquid crystal display according to an exemplary embodiment of the present invention.

In the following, DL and GL are also used as data lines and gate lines, respectively.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, and a data driver 500. And a gray voltage generator 800 and a signal controller 600.

Referring to FIG. 1, the liquid crystal panel assembly 300 is connected to a plurality of signal lines G ₁ -G _n , D ₁ -D _m in an equivalent circuit and arranged in a substantially matrix form. A plurality of pixels PX is included. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a plurality of data lines for transmitting a data voltage ( D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Pixels connected to each pixel PX, for example, the i-th (i = 1, 2,, n) gate line G _i and the j-th (j = 1, 2,, m) data line D _j ( PX includes a switching element Q connected to the signal lines G _i and D _j , a liquid crystal capacitor Clc and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line G _i-1 directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike in FIG. 2, the color filter 230 may be disposed above or below the pixel electrode 191 of the lower panel 100.

The liquid crystal panel assembly 300 is provided with at least one polarizer (not shown).

Referring back to FIG. 1, the gray voltage generator 800 generates a total gray voltage related to the transmittance of the pixel PX or a limited number of gray voltages (hereinafter referred to as a “reference gray voltage”). The reference gray level voltage may include a positive value and a negative value with respect to the common voltage Vcom.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ).

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300, and selects a gray voltage from the gray voltage generator 800 and uses the data line D as the data voltage. ₁ -D _m ). However, when the gray voltage generator 800 does not provide all the gray voltages but provides only a limited number of reference gray voltages, the data driver 500 divides the reference gray voltages to generate a desired data voltage.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m and the thin film transistor switching element Q. It may be. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). The input image signals R, G, and B contain luminance information of each pixel PX, and the luminance is a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ), or 64 (= 2 ⁶ ) It has gray. Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock signal MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is analog data to the horizontal synchronization start signal STH and the data line D ₁ -D _m indicating the start of the transmission of the digital image signal DAT to the pixels PX of one row (bundling). The load signal LOAD and the data clock signal HCLK to apply a voltage are included. The data control signal CONT2 is also an inversion signal RVS which inverts the polarity of the data voltage with respect to the common voltage Vcom (hereinafter referred to as "polarity of the data voltage" by reducing the "polarity of the data voltage with respect to the common voltage"). ) May be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixels PX in one row (bundling), and each digital image signal DAT. By converting the digital image signal DAT into an analog data voltage by selecting the gray scale voltage corresponding to), it is applied to the corresponding data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. Then, the data voltage applied to the data lines D ₁ -D _m is applied to the pixel PX through the turned-on switching element Q.

The difference between the data voltage applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. This change in polarization is represented by a change in the transmittance of light by the polarizer, through which the pixel PX displays the luminance represented by the gray level of the image signal DAT.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all the gate lines G ₁ -G _n. ), The gate-on voltage Von is sequentially applied, and the data voltage is applied to all the pixels PX to display an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data voltage applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). At this time, even in one frame, the polarity of the data voltage flowing through one data line is periodically changed according to the characteristics of the inversion signal RVS (eg, row inversion and point inversion) or polarity of the data voltage applied to one pixel row. They can be different (eg invert columns, invert points).

A liquid crystal display and an inspection method thereof according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

3 is a schematic view of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 4 is an enlarged view of a portion A of the liquid crystal display shown in FIG. 3.

Referring to FIG. 3, a plurality of data pad groups DPG are disposed at upper and left edges of the liquid crystal panel assembly 300 where data driver ICs and gate driver ICs constituting the data driver 500 and the gate driver 400 are positioned. And a gate pad group GPG are arranged. Each pad group DPG and GPG includes a plurality of pads DP and GP, respectively.

Test pad groups TPG, in which a plurality of test pads TP for applying a test signal, are arranged on the left and right sides of the data pad group DPG, and similarly arranged on the left and right sides of the gate pad group GPG.

For convenience of explanation, the description will be made based on the data pad DP positioned above, and the description thereof also applies to the gate pad GP as it is.

Each test pad TP is connected to the data pads DP on the left and right sides through the test line TL and the signal line SL, except that the test pads TP are positioned at the left and right edges. Therefore, the test signal is applied to the left and right data pads DP and is applied to the data line DL connected to the data pad DP.

In addition, one test pad TP is connected to the data pad DP in a predetermined unit, and the drawing shows that the test pad TP is connected in six units.

At this time, a test signal is simultaneously applied to the test pad TP and the data pad DP.

As such, when the test signal is simultaneously applied, the signal is transmitted to the data line DL even when the test signal cannot be properly transmitted due to the scratching of the test line TL, compared to the case where the test signal is applied only to the test pad TP. Can be.

In addition, when the test signal is applied only to the data pad DP, a probe (not shown), such as a pointed needle, is contacted with the data pad DP to apply a test signal. It is not easy to determine whether the line DL is defective. However, since a signal is also applied to the test pad TP, a test signal is applied even when a contact is not properly made, thereby accurately determining whether or not a defect is present.

Accordingly, if the data line DL is correctly determined in the VI test, the module test can be performed without going through the gross test, thereby improving the yield.

In addition, the uniformity of the screen can be secured, and more accurate inspection can be performed. That is, there is a distance from the test pad TP to the data line DL, so the signal becomes weak due to resistance. In particular, a difference in brightness appears at the edge and the middle of the pad group DPG due to the distance difference. There may be difficulty in making the decision. However, by applying the test signal to the data pad DP, it is possible to make a more accurate determination by eliminating the unevenness of the screen due to the distance difference.

In this way, by simultaneously applying the test signal to the test pad TP and the data pad DP, it is possible to accurately and quickly determine whether the signal line is defective, thereby avoiding the gross test, thereby improving the yield.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (6)

A plurality of data lines carrying data signals, A data pad unit including data pads connected to the data lines, respectively; A signal line connected to each of the data pads, A plurality of inspection lines connected to the signal lines in predetermined units, and A test pad unit including test pads connected to the test lines Including, A test signal is applied to the test pad and the data pad simultaneously and separately. Liquid crystal display. In claim 1, Wherein the test pad part is alternately positioned with the data pad part, and the test pad part is one more than the number of the data pad part. In claim 1, A gate line for transmitting a gate signal, A gate pad part including gate pads connected to the gate lines, respectively; A signal line connected to each of the gate pads, A plurality of inspection lines connected to the signal lines in predetermined units, and A test pad unit including test pads connected to the test lines More, A test signal is applied to the test pad and the gate pad simultaneously and separately. Liquid crystal display. In claim 3, And the test pad portion is alternately disposed with the gate pad portion, and the test pad portion is one more than the number of the gate pad portion. A plurality of data lines for transmitting a data signal, a data pad unit including data pads respectively connected to the data lines, a signal line connected to each of the data pads, and a plurality of test lines connected to the signal lines in predetermined units And an inspection pad unit including an inspection pad connected to each of the inspection lines. Applying a test signal to the test pad and the data pad simultaneously and separately. Inspection method of liquid crystal display device. In claim 5, And the test pad part is alternately positioned with the data pad part, and the test pad part is one more than the number of the data pad part.

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