KR102296768B1 - Display panel and method for testing of display panel - Google Patents

Abstract

A display panel according to an embodiment of the present invention includes a display panel including a display area and a non-display area, which is disposed on the display area and is defined by intersections of a plurality of gate lines and a plurality of data lines in the display area. A plurality of sub-pixels disposed in a sub-pixel area to display the first to fourth colors, respectively, and a plurality of sub-pixels disposed in the non-display area, the plurality of data lines are grouped by eight, and each of the grouped data lines is 1: A display panel including a test data line mounting unit including first to eighth test data lines connected by 1. The inspection data line mounting unit applies the inspection data signal for expressing the first to fourth colors of positive polarity and the inspection data signal for expressing the first to fourth colors of the negative polarity, and performs inversion for each frame The data line for the 8-phase test may be included to make this possible.

Description

DISPLAY PANEL AND METHOD FOR TESTING OF DISPLAY PANEL

The present invention relates to a display panel and a method for inspecting the display panel.

With the development of various portable devices such as mobile phones, laptops, and computers, and information electronic devices that implement high-resolution and high-quality images such as HDTV, flat panel displays applied thereto device) is gradually increasing. Although LCD (Liquid Crystal Display), PDP (Plasma Display Panel), FED (Field Emission Display), and OLED (Organic Light Emitting Diodes) have been actively studied as such flat panel display devices, mass production technology, ease of driving means, and high quality Liquid crystal display (LCD) is currently in the spotlight due to the reason of realization and realization of a large-area screen.

The manufacturing process of a liquid crystal display device is divided into a substrate cleaning process, a substrate patterning process, an alignment film formation and rubbing process, a liquid crystal dropping process and a substrate bonding process, an inspection process, a repair process, a mounting process, and the like.

In the substrate cleaning process, foreign substances contaminated on the substrate surface of the liquid crystal display are removed with a cleaning solution. The substrate patterning process is divided into patterning of an upper substrate (color filter array substrate) and patterning of a lower substrate (TFT array substrate). A color filter, a common electrode, a black matrix, and the like are formed on the upper substrate. Signal wirings such as data lines and gate lines are formed on the lower substrate, TFTs are formed at intersections of data lines and gate lines, and pixel electrodes connected to TFTs are formed in a pixel region between the data lines and gate lines. In the alignment film formation and rubbing process, an alignment film is applied to each of the upper substrate and the lower substrate, and the alignment film is rubbed with a rubbing cloth or the like. In the liquid crystal dropping and substrate bonding process, the upper and lower substrates are bonded to each other using a sealant after liquid crystal and a spacer are dropped. The inspection process includes an electrical lighting inspection performed after various signal wirings and pixel electrodes are formed on the lower substrate and a defect inspection of each pixel. The repair process restores the board|substrate determined to be repairable by the inspection process. Meanwhile, defective substrates that cannot be repaired in the inspection process are discarded. In the mounting process, a tape carrier package (hereinafter referred to as "TCP") on which a drive IC (Integrated Circuit) is mounted is connected to a pad portion on a substrate. Such a drive IC may be directly mounted on a substrate using a Chip On Glass (COG) method other than the above-described Tape Automated Bonding method using TCP.

An auto probe is used in the inspection process. The auto probe applies an electrical signal to the completed display panel so that a desired screen can be visually viewed. The inspector determines whether the panel is good or bad by detecting point defects, line defects, and stains in the panel during the inspection process through the auto probe. The inspection method using the auto probe includes the Tr (Transistor) method, which performs inspection by applying a signal to the panel through switching of a transistor, and the actual driver IC by contacting the probe pin to the input pad of the panel 1:1. There is a needle method that can inspect the panel in a similar state, and a shorting bar method that shorts the signal wires of the display panel and tests with minimal pin contact.

Recently, a display panel in which luminance is increased by adding white sub-pixels is being developed. And with the addition of white sub-pixels, various pixel structures of display panels are being developed. In this case, there is a limit to precisely inspecting the display panel to which the white sub-pixel is added only by using the auto-probe method applied to the conventional display panel including the red, green, and blue sub-pixels. In addition, when a single color pattern is implemented on a display panel including a white sub-pixel for inspection, a mixed-color pattern occurs due to the structure of the display panel, so there is a limit in matching the inspection consistency.

An embodiment according to the present invention may provide a display panel to which a white sub-pixel is added to improve transmittance.

In addition, another embodiment according to the present invention may provide a display panel for reducing power consumption.

In addition, another embodiment according to the present invention may provide a display panel capable of adjusting the size of sub-pixels according to the luminance and color of each color.

In addition, another embodiment according to the present invention may provide a display panel inspection method capable of increasing the precision of inspection of a display panel including white sub-pixels.

A display panel according to an embodiment of the present invention includes a display panel including a display area and a non-display area, which is disposed on the display area and is defined by intersections of a plurality of gate lines and a plurality of data lines in the display area. A plurality of sub-pixels disposed in a sub-pixel area to display the first to fourth colors, respectively, and a plurality of sub-pixels disposed in the non-display area, the plurality of data lines are grouped by eight, and each of the grouped data lines is 1: A display panel including a test data line mounting unit including first to eighth test data lines connected by 1. The inspection data line mounting unit applies the inspection data signal for expressing the first to fourth colors of positive polarity and the inspection data signal for expressing the first to fourth colors of the negative polarity, and performs inversion for each frame The data line for the 8-phase test may be included to make this possible.

In addition, in the display panel according to another embodiment of the present invention, the gate lines are arranged in the non-display area, and the gate lines of the complement are grouped by m (m is a multiple of 4) and connected 1:1 to each of the grouped gate lines. The display panel further includes an inspection gate line mounting unit including first to m-th inspection gate lines. By arranging inspection lines that bind the plurality of data lines and the plurality of gate lines at once on the non-display area, there is an advantage in that the inspection signal can be applied even when the pitch between the lines is small.

In addition, in the display panel according to another embodiment of the present invention, the plurality of sub-pixels include a display including sub-pixels displaying red, green, blue, and white colors. it's a panel By including the white sub-pixel, the luminance can be increased, and power consumption caused by the increase of the luminance can be reduced.

In addition, in the display panel according to another embodiment of the present invention, the sub-pixel region includes a sub-pixel region for thin film transistors, and the sub-pixel region for thin film transistors includes a thin film transistor connected to a pixel electrode included in an adjacent sub-pixel. display panel including In the sub-pixel area for thin film transistors, the size of the surrounding sub-pixels can be adjusted by mounting a transistor related to a sub-pixel adjacent to one sub-pixel. Accordingly, it has the effect of adjusting the size of the sub-pixel according to the luminance and color of each color.

In addition, in the display panel according to another embodiment of the present invention, the sub-pixel area for thin film transistors includes thin film transistors connected to each of three adjacent sub-pixels, and the sub-pixel area for thin film transistors includes a white sub-pixel. is a display panel on which is placed. By disposing thin film transistors for sub-pixels of all colors adjacent to the sub-pixel area in which the white sub-pixel is formed, the size of the pixel electrode included in the red, blue, and green sub-pixels can be increased. Accordingly, it is possible to increase the color gamut. The asymmetric pixel electrode structure has an effect of reducing power consumption and increasing color gamut according to an increase in luminance.

In addition, in the display panel according to another embodiment of the present invention, in the sub-pixel region for thin film transistors, a first thin film transistor connected to a pixel electrode included in a sub-pixel region on the left or right side of the sub-pixel region for thin film transistors and the A second thin film transistor connected to a pixel electrode included in a sub-pixel region below the sub-pixel region for thin film transistors, and a third thin film transistor connected to a pixel electrode included in a sub-pixel region in a diagonal direction below the sub-pixel region for thin film transistors A display panel comprising In the display panel according to the embodiment of the present invention, luminance can be increased by including the white sub-pixel, and power consumption caused by the luminance increase can be reduced. In addition, by disposing thin film transistors for sub-pixels of all colors adjacent to the sub-pixel area in which the white sub-pixel is formed, the size of the pixel electrode included in the red, blue, and green sub-pixels can be increased. Accordingly, it is possible to increase the color gamut. The asymmetric pixel electrode structure has an effect of reducing power consumption and increasing color gamut according to an increase in luminance.

In the inspection method of a display panel according to an embodiment of the present invention, the first to eighth inspection data lines are divided and driven every 1/n frame to display at least one of the first to fourth colors. This is an inspection method of a display panel in which a pattern signal is supplied to a data line connected to a data line for inspection that is divided and driven. The first to eighth test data lines are dividedly driven during a frame, and a DC level inspection pattern signal is applied to the first to eighth test data lines to have the same effect as applying an AC signal for one frame. have. Thus, in order to solve the delay problem caused by the signal resistance, the same effect as when the AC signal is applied during one frame while the pattern for inspection, which is a DC signal, is applied.

In the inspection method of a display panel according to another embodiment of the present invention, n is 4, the inspection method of the display panel. In consideration of color luminance deterioration and flicker problems, it is preferable that n is 4 .

In the inspection method of a display panel according to another embodiment of the present invention, the n is 2 and the inspection pattern signal for displaying the first and second colors among the first to fourth colors for 1/2 frame In the first step of supplying to a data line connected to the inspection data line for dividing and driving, the inspection data line for dividing and driving the inspection pattern signal displaying the third and fourth colors for the remaining 1/2 frame; A method of inspecting a display panel including a second step of supplying the connected data line. A mixed color pattern can be implemented over two frames and defects can be detected from it. In this case, it may be possible to simultaneously drive the first and second colors to simultaneously detect defects in the first and second color patterns, and simultaneously drive the third and fourth colors to simultaneously detect defects in the third and fourth color patterns. In addition, by dividing and driving the data line within one frame, the effect of applying the AC signal while applying the pattern signal for inspection, which is a DC signal, can be seen.

An embodiment according to the present invention may provide a display panel in which a white sub-pixel is added to improve transmittance, a display panel to reduce power consumption may be provided, and the size of sub-pixels according to luminance and color for each color It is also possible to provide a display panel that can adjust

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.
2 is a diagram illustrating a pixel structure of a display panel according to an exemplary embodiment of the present invention.
3 is a diagram illustrating a structure of a sub-pixel of a display panel and colors thereof according to an exemplary embodiment of the present invention.
4 is a diagram illustrating a non-display area and a display area of a display panel according to an embodiment of the present invention, and is a view showing a data line mounting unit for inspection in the non-display area;
5 is a view showing a non-display area and a display area of a display panel according to an embodiment of the present invention, and is a view showing a gate line mounting unit for inspection in the non-display area;
6 is a view showing a non-display area and a display area of a display panel according to an embodiment of the present invention;
7 is a diagram illustrating a method of inspecting a display panel according to a first exemplary embodiment of the present invention.
8 is a diagram illustrating a method of inspecting a display panel according to a second exemplary embodiment of the present invention.
9 and 10 are views illustrating a method of inspecting a display panel according to a third exemplary embodiment of the present invention.

Hereinafter, a display panel and a method for inspecting a display panel according to an embodiment of the present invention will be described in detail with reference to the drawings. The embodiments introduced below are provided as examples so that the spirit of the present invention can be sufficiently conveyed to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. And, in the drawings, the size and thickness of the device may be exaggerated for convenience. Like reference numbers refer to like elements throughout.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout. The sizes and relative sizes of layers and regions in the drawings may be exaggerated for clarity of description.

The terminology used herein is for the purpose of describing the embodiments, and thus is not intended to limit the present invention. As used herein, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprise” and/or “comprising” refers to the presence of one or more other components, steps, operations, and/or elements mentioned. or addition is not excluded.

<Liquid crystal display device according to the embodiment>

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 1 , a liquid crystal display according to an embodiment of the present invention includes a display panel 100 , a timing controller 200 , a data driving circuit 300 , and a gate driving circuit 400 .

The display panel 100 includes liquid crystal molecules disposed between two glass substrates. In the display panel 100 , m × n (m, n is a positive integer) sub-pixel regions are defined in a matrix form by an intersecting structure of the data lines D1 to Dm and the gate lines G1 to Gn. and liquid crystal cells Clc are disposed in each of the sub-pixel areas.

In addition, the sub-pixel region defined by the intersection of the plurality of gate lines and the plurality of data lines includes a first sub-pixel displaying a first color, a second sub-pixel displaying a second color, and a third sub-pixel displaying a third color. It includes a pixel and a fourth sub-pixel displaying a fourth color.

In the lower glass substrate of the display panel 100, m data lines D1 to Dm, n gate lines G1 to Gn, TFT (Thin Film Transistor, T), and TFTs are respectively connected. A sub-pixel including the pixel electrode 110 of the liquid crystal cell Clc and the storage capacitor Cst is formed.

A black matrix, a color filter, and a common electrode 120 are formed on the upper glass substrate of the display panel 100 . The common electrode 120 is formed on the upper glass substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode and It can be formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving method.

A polarizing plate having an optical axis orthogonal to each other is attached to the upper glass substrate and the lower glass substrate of the display panel 100 , and an alignment layer for setting a pretilt angle of the liquid crystal may be formed on the inner surface in contact with the liquid crystal.

The data driving circuit 300 may include a plurality of data driver integrated circuits. The data driving circuit 300 latches digital video data RGBW under the control of the timing controller 200 and converts the digital video data into analog positive/negative gamma compensation voltages to generate positive/negative data voltages. do. Each of the plurality of data driver integrated circuits may provide a data signal to each of the plurality of grouped data lines D1 to Dm. Accordingly, the number of the data driver integrated circuits may vary according to the degree of grouping of the data driver integrated circuits according to the resolution of the liquid crystal display device.

The data driving circuit 300 supplies a data voltage to the data lines D1 to Dm during each horizontal period in which the source output enable signal SOE is maintained at a low logic level.

The data driver integrated circuits may be mounted on a tape carrier package (TCP) and bonded to the lower glass substrate of the display panel 100 by a tape automated bonding (TAB) process.

The gate driving circuit 400 includes a shift register, a level shifter for converting the output signal of the shift register into a swing width suitable for driving the TFT of the liquid crystal cell, and an output buffer connected between the level shifter and the gate lines G1 to Gn. includes The gate driving circuit 400 sequentially supplies gate signals having a pulse width of approximately one horizontal period to the gate lines G1 to Gn under the control of the timing controller 200 . The gate driving circuit 400 is mounted on the TCP and bonded to the lower glass substrate of the display panel 100 by the TAB process, or directly on the lower glass substrate simultaneously with the pixel array by the GIP (Gate driver In Panel) process. can be formed.

The timing controller 200 converts digital video data (RGB) inputted from a system board (not shown) into RGBW video data, rearranges it to fit the display panel 100 , and supplies it to the data driving circuit 300 . The timing controller 200 receives timing signals such as vertical/horizontal synchronization signals (Vsync, Hsync), data enable, and clock signal CLK from the system board, and receives the data driving circuit 300 and the gate driving circuit Control signals GCS and DCS for controlling the operation timing of 400 are generated.

The gate timing control signal GCS for controlling the gate driving circuit 400 includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE) and the like. The gate start pulse GSP is generated once during one frame period at the same time as the start of the frame period to generate the first gate pulse. The gate shift clock GSC is a clock signal commonly input to a plurality of stages constituting the shift register and shifts the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate driving circuit 400 .

The data timing control signal DCS for controlling the data driving circuit 300 includes a source start pulse (SSP), a source sampling clock (SSC), a vertical polarity control signal (Polarity, POL) and and a source output enable signal (Source Output Enable, SOE). The source start pulse SSP is a signal that controls the data sampling start timing of the data driving circuit 300 , and the source sampling clock SSC corresponds to a rising or falling edge in each IC constituting the data driving circuit 300 . A clock signal that controls the sampling timing of data. In addition, the vertical polarity control signal Polarity POL controls the vertical polarity inversion timing of the data voltage output from the data driving circuit 300 for each gate line G1 to Gn, and the source output enable signal SOE is It serves to control the output timing of the data driving circuit 300 .

The data driving circuit 300 latches RGBW DATA input under the control of the timing controller 200 . Then, the vertical polarity control signal (Polarity, POL) is converted into an analog positive or negative gamma compensation voltage (GAMMA) and simultaneously output to the display panel 100 through all data lines D1 to Dm.

Specifically, the data driving circuit 300 may set the polarity of the data voltage output from the data driving circuit 300 to a positive polarity when the vertical polarity control signal POL provided from the timing controller 200 is high logic. , when the logic is low, the polarity of the data voltage output from the data driving circuit 300 may be negative.

The polarity may be inverted in units of vertical lines by the vertical polarity control signal POL.

<The structure of pixels on the display area of the display panel>

2 is a diagram illustrating a pixel structure of a display area in a display panel according to an exemplary embodiment of the present invention.

Hereinafter, in (i, j), i denotes the i-th horizontal line, j denotes the j-th vertical line, and (i, j) denotes the sub-pixel area or sub-pixel corresponding to the i-th horizontal line and the j-th vertical line. can mean In addition, the horizontal line is defined as a region between two adjacent gate lines, and the vertical line is defined as a region between two adjacent data lines. Also, i and j are natural numbers.

Referring to FIG. 2 , the display area 100a of the display panel 100 according to an embodiment of the present invention includes a plurality of data lines m to m9 and a plurality of data lines m to m8 intersecting the plurality of data lines m to m8 . It may include gate lines n to n8 and a plurality of sub-pixel regions 110 defined by intersecting data lines and gate lines.

Referring to FIG. 2 , in the display area 100a of the display panel 100 according to the embodiment, in the pixel structure, the data lines m to m+7 in response to the gate signals on the gate lines n to n+8. The thin film transistor T that provides the upper-phase data signal to the pixel electrode 110 of the sub-pixel may be formed together in any one of the sub-pixel areas 101 , 102 , 103 , and 104 . That is, a sub-pixel region including a thin film transistor connected to an adjacent sub-pixel may be defined as the thin film transistor sub-pixel regions 101 , 102 , 103 , and 104 .

The thin-film transistor sub-pixel regions 101, 102, 103, and 104 are in the thin-film transistors T1, T2, T3 connected to the three adjacent sub-pixels and the thin-film transistor sub-pixel regions 101, 102, 103, 104. All of the thin film transistors T connected to the arranged sub-pixels may be included. That is, in the sub-pixel regions for thin film transistors 101 , 102 , 103 , and 104 , the first pixel electrode connected to the sub-pixel region on the left or right side of the sub-pixel regions 101 , 102 , 103 , 104 for thin film transistors is connected. 1 thin film transistor T1, a second thin film transistor T2 connected to a pixel electrode included in a sub-pixel region below the sub-pixel regions 101, 102, 103, and 104 for the thin film transistor, and the sub-pixel for the thin film transistor A third thin film transistor T3 connected to the pixel electrode included in the sub-pixel region in the diagonal direction below the region 102 may be included.

The sub-pixel regions for thin film transistors may include first to fourth type sub-pixel regions 101 , 102 , 103 , and 104 for thin film transistors.

<Sub-pixel area for first type thin film transistor according to the embodiment>

Assuming that the sub-pixel region for thin film transistors corresponds to the j-th vertical line and the i-th horizontal line, the sub-pixel region 101 for the first type thin film transistor includes sub-pixel regions corresponding to the j-th vertical line and the i-th horizontal line. The thin film transistor connected to the pixel, the thin film transistor connected to the sub-pixel corresponding to the j-1th vertical line and the i-th horizontal line, the thin film transistor connected to the sub-pixel corresponding to the j-1th vertical line and the i+1th horizontal line, and A thin film transistor connected to the sub-pixel corresponding to the j-th vertical line and the i+1-th horizontal line may be disposed.

<Sub-pixel area for second type thin film transistor according to the embodiment>

Assuming that the sub-pixel region for thin film transistors corresponds to the j-th vertical line and the i-th horizontal line, the sub-pixel region 102 for the second type thin film transistor includes sub-pixel regions corresponding to the j-th vertical line and the i-th horizontal line. The thin film transistor connected to the pixel, the thin film transistor connected to the sub-pixel corresponding to the j-1th vertical line and the i-th horizontal line, the thin film transistor connected to the sub-pixel corresponding to the j-th vertical line and the i+1th horizontal line, and j+ A thin film transistor connected to a sub-pixel corresponding to the first vertical line and the i+1-th horizontal line may be disposed.

<Sub-pixel area for third type thin film transistor according to the embodiment>

Assuming that the sub-pixel region for thin film transistors corresponds to the j-th vertical line and the i-th horizontal line, the sub-pixel region 103 for the third type thin film transistor includes sub-pixel regions corresponding to the j-th vertical line and the i-th horizontal line. The thin film transistor connected to the pixel, the thin film transistor connected to the sub-pixel corresponding to the j+1th vertical line and the i-th horizontal line, the thin film transistor connected to the sub-pixel corresponding to the j-1th vertical line and the i+1th horizontal line, and A thin film transistor connected to the sub-pixel corresponding to the j-th vertical line and the i+1-th horizontal line may be disposed.

<Sub-pixel area for the fourth type thin film transistor according to the embodiment>

Assuming that the sub-pixel region for thin film transistors corresponds to the j-th vertical line and the i-th horizontal line, the sub-pixel region 104 for the fourth type thin film transistor includes sub-pixel regions corresponding to the j-th vertical line and the i-th horizontal line. The thin film transistor connected to the pixel, the thin film transistor connected to the sub-pixel corresponding to the j+1th vertical line and the i-th horizontal line, the thin film transistor connected to the sub-pixel corresponding to the j-th vertical line and the i+1th horizontal line, and j+ A thin film transistor connected to a sub-pixel corresponding to the first vertical line and the i+1-th horizontal line may be disposed.

Specifically, referring to the drawings, in the (i+1, j+2) sub-pixel region 102 for thin film transistors, the j+1-th vertical line and the sub-pixel corresponding to the i+1-th horizontal line are connected. The thin film transistor T1, the thin film transistor T2 connected to the sub-pixel corresponding to the j + 2 th vertical line and the i + 2 th horizontal line, and the j + 3 th vertical line and corresponding to the i + 2 th horizontal line A thin film transistor T3 connected to the sub-pixel may be disposed. In addition, in the (i, j+4) thin film transistor sub-pixel region 101, the j + 3 th vertical line and the thin film transistor T1 connected to the sub pixel corresponding to the i th horizontal line, the j + 4 th vertical line and a thin film transistor T2 connected to the sub-pixel corresponding to the i+1th horizontal line and the thin film transistor T3 connected to the sub-pixel corresponding to the j+3th vertical line and the i+1th horizontal line are disposed. can In addition, in the (i+3, j+2) thin film transistor sub-pixel region 103, the thin film transistor T1 connected to the sub-pixel corresponding to the j+3 th vertical line and the i+3 th horizontal line, the j+ The thin film transistor T2 connected to the sub-pixel corresponding to the first vertical line and the i+4th horizontal line, and the thin film transistor T3 connected to the sub-pixel corresponding to the j+2th vertical line and the i+4th horizontal line ) can be placed. In addition, in the (i+2, j+4) sub-pixel region 104 for thin film transistors, the thin film transistor T1 connected to the sub-pixel corresponding to the j+5th vertical line and the i+2th horizontal line, the j+ The thin film transistor T2 connected to the sub-pixel corresponding to the fourth vertical line and the i+3th horizontal line, and the thin film transistor T3 connected to the sub-pixel corresponding to the j+5th vertical line and the i+3rd horizontal line ) can be placed.

As such, the sub-pixel region for thin film transistors corresponds to the j-th vertical line and the i-th horizontal line, and the sub-pixel region for the thin film transistor corresponds to the j-1th or j+1-th vertical line and the i-th horizontal line. The thin film transistor connected to the sub-pixel, the thin film transistor connected to the sub-pixel corresponding to the j-th vertical line and the i+1-th horizontal line, and the j-1th or j+1th vertical line and the i+1th horizontal line By disposing the thin film transistors connected to the corresponding sub-pixels, it is possible to have a zig-zag structure in units of two sub-pixels in the vertical direction, and accordingly, a vertical two-dot inversion and an inversion effect for each color may appear.

In addition, in the sub-pixel area for thin film transistors, the size of the surrounding sub-pixels can be adjusted by mounting a transistor related to a sub-pixel adjacent to one sub-pixel. Accordingly, it has the effect of adjusting the size of the sub-pixel according to the luminance and color of each color.

<Disposition relation of sub-pixels by color according to the embodiment>

3 is a diagram illustrating a structure of a sub-pixel of a display panel and colors thereof according to an exemplary embodiment of the present invention.

Referring to FIG. 3 , in the display panel according to the embodiment of the present invention, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are arranged in the order of the odd-numbered horizontal line, and the even-th horizontal line The third sub-pixel, the fourth sub-pixel, the first sub-pixel, and the second sub-pixel may be arranged in the following order, wherein the first sub-pixel displays a first color, and the first color is red. may be, the second sub-pixel may display a second color, the second color may be green, the third sub-pixel may display a third color, and the third color may be It may be blue, the fourth sub-pixel may display a fourth color, and the fourth color may be white.

That is, in the display panel according to the embodiment of the present invention, white, red, green, and blue sub-pixels are sequentially arranged in areas corresponding to the j-th vertical line, the j+1 to j+3 vertical lines, and the i-th horizontal line. and green, blue, white, and red sub-pixels sequentially disposed in regions corresponding to the j to j+3 th vertical line and the i+1 th horizontal line. The arrangement relationship of the sub-pixels for each color may be a relationship that is repeated in the horizontal and vertical directions.

and red, green, blue, and white sub-pixels sequentially arranged in regions corresponding to the j-th vertical line, the j+1 to j+3th vertical line, and the i-th horizontal line, wherein the j to j+3th vertical lines are included. It may include blue, white, red, and green sub-pixels sequentially arranged in regions corresponding to the line and the i+1-th horizontal line. Also, the k to k+3 th sub-pixels may be red, green, blue, and white sub-pixels.

Specifically, red, green, blue, and white sub-pixels may be sequentially disposed on the i-th horizontal line, and again, red, green, blue, and white sub-pixels may be repeatedly disposed. That is, the sub-pixels of (i, j), (i, j+1), (i, j+2), and (i, j+3) may be white, red, green, and blue sub-pixels in that order. , (i, j+4), (i, j+5), (i, j+6), (i, j+7) sub-pixels can be white, red, green, and blue sub-pixels in that order. have. Also, green, blue, white, and red sub-pixels may be sequentially disposed on the i+1th horizontal line, and again, green, blue, white, and red sub-pixels may be repeatedly disposed. That is, the sub-pixels of (i+1, j), (i+1, j+1), (i+1, j+2), and (i+1, j+3) are green, blue, and white in that order. and red sub-pixels, and sub-pixels of (i+1, j+4), (i+1, j+5), (i+1, j+6), (i+1, j+7). Pixels may be green, blue, white, and red sub-pixels in that order. In addition, white, red, green, and blue sub-pixels may be sequentially disposed on the i+2th horizontal line, and again, white, red, green, and blue sub-pixels may be repeatedly disposed. That is, the sub-pixels of (i+2, j), (i+2, j+1), (i+2, j+2), (i+2, j+3) are white, red, and green in that order. And it can be a blue sub-pixel, (i+2, j+4), (i+2, j+5), (i+2, j+6), (i+2, j+7) sub Pixels may be white, red, green, and blue sub-pixels in that order. In addition, green, blue, white, and red sub-pixels may be sequentially disposed on the i+3 th horizontal line, and again, blue, green, blue, white, and red sub-pixels may be repeatedly disposed. That is, the sub-pixels of (i+3, j), (i+3, j+1), (i+3, j+2), (i+3, j+3) are green, blue, and white in that order. and red sub-pixels, (i+3, j+4), (i+3, j+5), (i+3, j+6), (i+3, j+7) sub The pixels may be green, blue, white and red sub-pixels in that order. In addition, the remaining sub-pixels may be repeated in the vertical and horizontal directions like the above-described arrangement structure of the sub-pixels.

In addition, a white sub-pixel may be disposed in the sub-pixel areas 101 , 102 , 103 , and 104 for the thin film transistor.

As described above, as the white sub-pixels are formed in the sub-pixel regions 101, 102, 103, and 104 for the thin film transistor, the size of the pixel electrode included in the white sub-pixel may be smaller than the size of the pixel electrodes of other colors. Such a structure may be referred to as an asymmetric pixel electrode structure.

In the display panel 100 according to the embodiment of the present invention, luminance can be increased by including the white sub-pixel, and power consumption caused by the luminance increase can be reduced. In addition, by disposing thin film transistors for sub-pixels of all colors adjacent to the sub-pixel area in which the white sub-pixel is formed, the size of the pixel electrode included in the red, blue, and green sub-pixels can be increased. Accordingly, it is possible to increase the color gamut. The asymmetric pixel electrode structure has an effect of reducing power consumption and increasing color gamut according to an increase in luminance.

<Non-display area and display area of the display panel according to the first embodiment>

4 is a view showing a non-display area and a display area of a display panel according to an embodiment of the present invention. It is a view showing a display area and a display area, and is a view showing a gate line mounting unit for inspection in a non-display area.

Referring to FIG. 4 , an inspection data line mounting unit 610 may be disposed in the non-display area 100b of the display panel 100 according to an embodiment of the present invention, and the inspection data line mounting unit 610 may be disposed. ) may be connected to data lines on the display area 100a by the first connection control unit 510 .

The test data line mounting unit 610 may include 8-phase test data lines DS1 to DS8. Specifically, the inspection data line mounting unit 610 applies an inspection data signal for expressing positive first to fourth colors and an inspection data signal for expressing negative first to fourth colors, , the 8-phase test data lines DS1 to DS8 may be included to perform inversion for each frame.

The eight-phase inspection data lines DS1 to DS8 may be grouped by eight data lines and connected 1:1 with data lines in these groups.

Among the eight-phase inspection data lines, a first inspection data line DS1 is connected to an m-th data line, a second inspection data line DS2 is connected to an m+1-th data line, and a third inspection data line DS1 is connected to the m+1-th data line. The data line DS3 is connected to the m+2 th data line, the fourth inspection data line DS4 is connected to the m+3 th data line, and the fifth inspection data line DS5 is the m+4 th data line. connected to the data line, the sixth inspection data line DS6 is connected to the m+5th data line, the seventh inspection data line DS7 is connected to the m+6th data line, and the eighth inspection data line DS7 is connected to the m+6th data line The data line DS8 may be connected to an m+7th data line, and the first connection control unit 510 includes at least one switching element to connect the eight-phase test data lines DS1 to DS8 and the data lines. Each connection can be controlled.

The first connection control unit 510 may control whether or not to connect the data lines DS1 to DS8 and the data lines for 8-phase inspection according to a first control signal CS1 input from the outside.

The first connection control unit 510 may control whether the eight-phase inspection data lines DS1 to DS8 and the data lines are connected in a Tr method including a plurality of thin film transistors serving as switching.

The inspection pattern signal applied to at least one of the eight-phase inspection data lines DS1 to DS8 under the control of the first connection control unit 510 is connected to the inspection data line to which the inspection pattern signal is applied. It may be supplied to one data line.

On the other hand, if four data lines among the odd-numbered data lines are defined as one group, the data lines in one group are sequentially connected to each of the first to fourth test data lines DS1, DS2, DS3, and DS4, and , if four data lines among even-numbered data lines are defined as one group, the data lines in one group may be sequentially connected to each of the fifth to eighth test data lines DS5, DS6, DS7, and DS8. have.

Referring to FIG. 5 , an inspection gate line mounting unit 620 may be disposed in the non-display area 100b of the display panel 100 according to an embodiment of the present invention, and the inspection gate line mounting unit 620 may be disposed. ) may be connected to the gate lines on the display area 100a by the second connection control unit 520 .

The inspection gate line mounting unit 620 may include a gate line for m (m is a multiple of 4) channel inspection, for example, as shown in FIG. 5 , m may be 4, so that the inspection The gate line mounting unit 620 may include gate lines GS1 to GS4 for 4-channel inspection.

A plurality of gate lines may be grouped by four, and the four gate lines in the group may be connected 1:1 with the gate line for the 4-channel inspection. In this case, m may be 8 or 12, and in this case, a plurality of gate lines may be grouped by 8 or 12, and 8 or 12 gate lines in the group may be 1:1 connected to the inspection gate line. .

Among the four-channel inspection gate lines, the first inspection gate line GS1 is connected to the n-th gate line, the second inspection gate line GS2 is connected to the n+1-th gate line, and the third inspection gate line GS2 is connected to the n+1-th gate line. The gate line GS3 may be connected to an n+2 th gate line, the fourth inspection gate line GS4 may be connected to an n+3 th gate line, and the second connection control unit 520 may control at least one switching Each of the gate lines GS1 to GS4 for inspection and each of the gate lines may be controlled by including the device.

The second connection control unit 520 may control whether the gate lines are connected to the four-channel inspection gate lines GS1 to GS4 according to a second control signal CS2 input from the outside.

The inspection gate signal applied to at least one of the four-channel inspection gate lines GS1 to GS4 under the control of the first connection control unit 510 is connected to the inspection gate line to which the inspection gate signal is applied. It may be supplied to one gate line.

Meanwhile, the n-th to n+3-th gate lines are sequentially connected to each of the first to fourth inspection gate lines GS1 to GS4, and the n+4 to n+7-th gate lines are sequentially connected to the first to fourth gate lines. It may be connected to each of the inspection gate lines GS1 to GS4. That is, if four sequentially arranged gate lines are defined as one group, the gate lines in one group may be connected to each of the first to fourth inspection gate lines GS1 to GS4 .

A data line mounting unit 610 for inspection and a gate line mounting unit 620 for inspection are provided in the non-display area 100b of the display panel 100 according to the first embodiment, and the gate line mounting unit 620 for inspection is provided. ) when the thin film transistor of the display area 100a is turned on according to the inspection gate signal applied through the inspection gate line GS on An image for testing may be displayed while the pattern signal for inspection applied through the pixel electrode is applied to the pixel electrode. In addition, as the display panel 100 increases in resolution, the distance between the data lines and the distance between the gate lines becomes narrower, so it may be difficult to individually connect each of these lines to apply an individual inspection signal. As in the embodiment, by arranging inspection lines DS or GS that bind a plurality of data lines and a plurality of gate lines at once on the non-display area 100b, the inspection signal can be applied even when the pitch between the lines is small. There are advantages that can be

<Non-display area and display area of the display panel according to the second embodiment>

6 is a diagram illustrating a non-display area and a display area of a display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 6 , a data line mounting unit 610 for inspection and a gate pad unit 800 may be disposed in the non-display area 100b of the display panel 100 according to an embodiment of the present invention, and the inspection The data line mounting unit 610 for use may be connected to the data lines on the display area 100a by the first connection control unit 510 . In addition, the test data line mounting unit 610 may include 8-phase test data lines DS1 to DS8. A test gate driver 700 may be connected on the gate pad part 800 to supply a test gate signal to the gate line. A gate driving circuit of a gate in panel (GIP) type may be mounted between the gate pad part 800 and the display area 100a. A jig of the test gate driver 700 may be connected to each of the gate lines of the gate pad unit 800 to supply a scan signal to each of the gate lines to individually control them.

<Inspection method of display panel according to the first embodiment>

7 is a diagram illustrating a method of inspecting a display panel according to a first exemplary embodiment of the present invention.

Referring to FIG. 7 , in the inspection method of the display panel according to the first exemplary embodiment, the inspection gate lines GS1 to GS4 may be dividedly driven. That is, the display panel 100 may be inspected by driving any one of the inspection gate lines GS1 to GS4 and applying an inspection pattern signal through a corresponding data line to individually drive the sub-pixels.

For example, in the first step, the n, n+4, n+8th gate lines corresponding to the first inspection gate line GS1 are driven (solid arrow), and in the second step, the second inspection The n+1 and n+5th gate lines corresponding to the gate line GS2 are driven (dotted arrow), and as a first step, n+ which is the gate line corresponding to the third inspection gate line GS3. Driving the 2nd and n+6th gate lines (a dashed-dotted line arrow), and driving the n+3, n+7th gate lines, which are gate lines corresponding to the fourth inspection gate line GS4 in a fourth step, (Double-dotted arrow) A pattern signal for inspection may be applied to a corresponding sub-pixel.

<Inspection method of display panel according to the second embodiment>

8 is A diagram illustrating a method of inspecting a display panel according to a second exemplary embodiment of the present invention.

Referring to FIG. 8 , in the method of inspecting a display panel according to the second exemplary embodiment, data lines are individually separated over 1/n frames by a test gate signal individually applied to each of the gate lines from the test gate driver 700 . can drive

For example, FIG. 8 relates to a method of inspecting a monochromatic pattern of a red color by displaying a red color pattern on the display panel 100, and a test pattern on a data line corresponding to each red sub-pixel in the order of No. 1 to No. 4 A single color pattern check can be performed by applying a signal. At this time, two of the 8-phase test data lines DS1 to DS8 are driven together for every 1/4 frame, and all of the 8-phase test data lines DS1 to DS8 are driven during one frame. In this case, an inspection pattern signal for displaying a red color may be applied to a test data line driven every 1/4 frame, and a negative polarity signal remaining the positive polarity signal may be applied to one of the two test data lines.

Meanwhile, a method of driving one of the 8-phase test data lines DS1 to DS8 every 1/8 frame by setting n to 8 is also possible. However, if the value of n is too large, color luminance degradation and flicker problems Since there may be , it is preferable that n is 4.

The first to eighth test data lines DS1 to DS8 are dividedly driven for one frame, and a DC level inspection pattern signal is applied to the first to eighth test data lines DS1 to DS8 for one frame. It may have the same effect as applying an AC signal. Thus, in order to solve the problem of delay due to signal resistance, it is possible to see the same effect as when an AC signal is applied during one frame while applying a pattern for inspection, which is a DC signal.

<Inspection method of display panel according to the third embodiment>

9 and 10 are It is a view showing a method of inspecting a display panel according to a third embodiment of the present invention.

9 and 10 , in the method of inspecting a display panel according to the third exemplary embodiment, data lines are applied over 1/2 frame by a test gate signal individually applied to each of the gate lines from the test gate driver 700 . can be driven individually. In addition, a mixed color pattern inspection may be performed by implementing a mixed color pattern of green and white colors for 1/2 frame and a mixed color pattern of red and blue colors for 1/2 frame. At this time, it is not limited to the above color, and any two colors of RGBW may be implemented during 1/2 frame and the other two colors may be implemented during the remaining 1/2 frame.

In this way, it is possible to implement a color mixture pattern over two frames and detect a defect therefrom. In this case, it may be possible to simultaneously drive the first and second colors to simultaneously detect defects in the first and second color patterns, and simultaneously drive the third and fourth colors to simultaneously detect defects in the third and fourth color patterns. In addition, by dividing and driving the data line within one frame, the effect of applying the AC signal while applying the pattern signal for inspection, which is a DC signal, can be seen.

In the display panel 100 to which the white sub-pixel is added as described above, by applying the inspection method of the display panel according to the first to third embodiments, point defects, line defects, stains, etc. are detected to determine the quality of the panel. can be judged.

In the detailed description of the present invention described above, it has been described with reference to preferred embodiments of the present invention, but those skilled in the art or those having ordinary knowledge in the technical field of the present invention described in the claims to be described later It will be understood that various modifications and variations of the present invention can be made without departing from the spirit and scope of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100 display panel
100a display area
100b non-display area
101 Sub-pixel area for type 1 thin film transistor
102 Sub-pixel area for type 2 thin film transistor
103 Sub-pixel area for type 3 thin film transistor
104 Sub-pixel area for type 4 thin film transistor
110 pixel electrode
120 common electrode
200 timing controller
300 data drive circuit
400 gate driving circuit
510 first connection control unit
520 second connection control unit
610 Inspection Data Line Mounting Unit
620 Inspection Gate Line Mounting Unit
700 Inspection Gate Driver
800 gate pad

Claims (10)

A display panel comprising a display area and a non-display area, the display panel comprising:
placed on the display area
a plurality of pixels disposed in a sub-pixel area defined by intersections of a plurality of gate lines and a plurality of data lines of the display area and respectively displaying red, green, blue, and white colors sub-pixels; and
an inspection data line mounting unit disposed in the non-display area, the plurality of data lines grouped by eight, and first to eighth inspection data lines connected 1:1 to each of the grouped data lines; including,
The plurality of sub-pixels includes a plurality of sub-pixel areas for thin film transistors,
The sub-pixel area for each thin film transistor is
a first thin film transistor connected to a pixel electrode of a left or right sub-pixel area;
a second thin film transistor connected to the pixel electrode of the lower sub-pixel area;
a third thin film transistor connected to the pixel electrode of the lower left or lower right diagonal sub-pixel area;
The first thin film transistors arranged on the 4i-3 and 4i-2 horizontal lines are connected to the pixel electrode on the left side, and the first thin film transistors arranged on the 4i-1 th horizontal lines and the 4i th horizontal lines are on the right side. connected to the pixel electrode, wherein i is a natural number excluding 0,
The third thin film transistors disposed on the 4i-3 and 4i-th horizontal lines are connected to the lower left diagonal pixel electrodes, and the third thin-film transistors disposed on the 4i-1 and 4i-2 horizontal lines is connected to the lower right diagonal pixel electrode,
The red, green, blue, and white sub-pixels are repeatedly arranged in the order of the 4i-3 and 4i-1 horizontal lines, and the blue, white, red, and green sub-pixels are disposed on the 4i-2 and 4i horizontal lines. By repeatedly arranging sub-pixels in the order of color,
The plurality of sub-pixels are vertically 2 for each of two colors of the red, green, blue, and white colors according to the inspection pattern signals input with different polarities between odd-numbered and even-numbered data lines among the plurality of data lines. Dot-inverted display panel. According to claim 1,
Inspection including first to mth inspection gate lines disposed in the non-display area and connected 1:1 to each of the grouped gate lines by grouping the plurality of gate lines by m (m is a multiple of 4) A display panel further comprising a gate line mounting unit for use. delete delete delete According to claim 1,
A display panel in which a white sub-pixel is disposed in the sub-pixel area for the thin film transistor. delete The method of inspecting a display panel according to claim 1, comprising:
A data line connected to an inspection data line for dividingly driving the first to eighth inspection data lines every 1/n frame to divide and drive inspection pattern signals displaying at least one of the first to fourth colors Inspection method of the display panel supplied to 9. The method of claim 8,
wherein n is 4; a method of inspecting a display panel. 9. The method of claim 8,
wherein n is 2,
a first step of supplying an inspection pattern signal representing two of the red, green, blue and white to a data line connected to the inspection data line for dividing the driving during 1/2 frame; and
a second step of supplying an inspection pattern signal displaying the remaining two of the red, green, blue, and white during the remaining 1/2 frame to a data line connected to the inspection data line for dividing and driving; of the inspection method.

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