KR102153575B1 - Liquid Crystal Display Device and Driving Method the same - Google Patents

Abstract

In the liquid crystal display according to the exemplary embodiment of the present invention, first and second thin film transistors are allocated to each of the first and second gate lines and share one data line, and the first and second thin film transistors are connected to each of the first and second thin film transistors. And a liquid crystal display panel having a liquid crystal cell including a second pixel electrode and an auxiliary data line connecting the connection points of the data line and the first and second thin film transistors to each other.

Description

Liquid Crystal Display Device and Driving Method the same}

The present invention relates to a liquid crystal display device and a driving method thereof.

The liquid crystal display device displays an image by controlling the light transmittance of the liquid crystal layer through an electric field applied to the liquid crystal layer in response to a video signal.

Such a liquid crystal display device is a flat panel display device having advantages of small size and thickness and low power consumption, and is used as a portable computer such as a notebook PC, an office automation device, and an audio/video device.

In particular, an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell is advantageous for realizing a moving picture because it enables active control of the switching element.

As a switching element used in an active matrix type liquid crystal display device, a thin film transistor (hereinafter referred to as "TFT") is mainly used.

1 is a configuration diagram of a unit cell of a general liquid crystal display, and FIG. 2 is a configuration diagram of a conventional liquid crystal display driven by a DRD (double rate driving) method.

In the active matrix type liquid crystal display device, as shown in FIG. 1, digital video data is converted to an analog data voltage based on a gamma reference voltage and supplied to a data line DL and a scan pulse is transmitted to the gate line GL. To the liquid crystal cell Clc.

To this end, the gate electrode of the TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode of the TFT is the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst1. It is connected to one electrode.

The common voltage Vcom is supplied to the common electrode of the liquid crystal cell Clc. The storage capacitor Cst1 charges the data voltage applied from the data line DL when the TFT is turned on to maintain a constant voltage of the liquid crystal cell Clc.

When the scan pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source electrode and the drain electrode, so that the voltage on the data line DL is applied to the pixel electrode of the liquid crystal cell Clc. Supply.

At this time, the liquid crystal molecules of the liquid crystal cell Clc change the arrangement of the liquid crystal molecules by the electric field between the pixel electrode and the common electrode, thereby varying the incident light.

Such a liquid crystal display device includes a gate drive IC (Intergrated Circuit) for driving the gate lines GL and a data drive IC for driving the data lines DL, and is required as a liquid crystal display device becomes larger and higher resolution. The number of drive ICs is increasing. However, since the data drive IC is relatively very expensive compared to other devices, several methods have been proposed to reduce the number of data drive ICs recently.

As one of the above methods, as shown in FIG. 2, the number of gate lines is reduced by 1/2, instead of doubling the number of gate lines compared to the existing one, reducing the number of required data drive ICs by half, A DRD (Double Rate Driving) driving method that implements the same resolution has been proposed.

In the conventional liquid crystal display device driven by the DRD method, as shown in FIG. 2, d (d is a positive even number) liquid crystal cells arranged on one horizontal line are divided into two gate lines and d/2 data lines. It is driven by using

The conventional liquid crystal display of this DRD type drives a data drive IC in a vertical 2 dot inversion method to minimize flicker and reduce power consumption.

Accordingly, two liquid crystal cells adjacent to each other with a data line interposed therebetween are respectively connected to the two gate lines to charge a data voltage of the same polarity supplied through the data line.

In such a conventional liquid crystal display, since the polarity of the data voltage supplied to the specific data line DL is changed at any time, there is a problem in that power loss for changing the polarity of the data voltage is large.

In addition, by reducing the number of data lines DL, two liquid crystal cells are connected to one data line, and accordingly, there is a problem in that line resistance of each of the data lines DL is large.

This increase in line resistance increases the resistance and capacitor delay (RC Delay), resulting in a delay phenomenon of the data signal, there is a problem that the luminance decreases and color reduction difference occurs.

In addition, if the data line (DL) is opened due to a foreign object or daisy (damage) during the process, a data open (DO) defect occurs, and the liquid crystal connected to the data line (DL) that has become defective. There is a problem that the cell does not work.

A liquid crystal display device and a driving method thereof according to an embodiment of the present invention may provide a liquid crystal display device capable of reducing power consumption by using a Z inversion method and a driving method thereof.

In addition, a liquid crystal display device and a driving method thereof according to an exemplary embodiment of the present invention provide a liquid crystal display device and a driving method thereof capable of solving the problem of not driving a liquid crystal cell due to a defect in a data line DL due to a foreign object or daisy during a process. You can also provide.

In addition, the liquid crystal display device and the driving method thereof according to an exemplary embodiment of the present invention may provide a liquid crystal display device and a driving method thereof capable of solving a decrease in luminance and occurrence of a color difference due to an increase in resistance of a data line.

In the liquid crystal display according to the exemplary embodiment of the present invention, first and second thin film transistors are allocated to each of the first and second gate lines and share one data line, and the first and second thin film transistors are connected to each of the first and second thin film transistors. And a liquid crystal display panel having a liquid crystal cell including a second pixel electrode and an auxiliary data line connecting the connection points of the data line and the first and second thin film transistors to each other.

A liquid crystal display according to an exemplary embodiment of the present invention includes: d/2 (d is an even number) data lines and 2n (n is a natural number) gate lines intersecting the data lines; And a liquid crystal cell formed at an intersection between the data lines and the gate lines, wherein the liquid crystal cell includes first and second sub liquid crystal cells that share any one of the data lines, and the data lines In the vertical lines defined by two adjacent data lines and horizontal lines defined by two adjacent gate lines, the m (m is a natural number)-th vertical line among the vertical lines and the horizontal The liquid crystal cell in the crossing area of the n-1 (n is a natural number)-th horizontal line among the lines and the liquid crystal cell in the crossing area of the m-1th vertical line among the vertical lines and the n-th horizontal line of the horizontal lines are data A liquid crystal display that shares a line.

The liquid crystal display device and its driving method according to an embodiment of the present invention can reduce power consumption by using the Z inversion method, and the liquid crystal cell is not driven due to a defect in the data line DL due to a foreign object or daisy during the process. A liquid crystal display device capable of solving a problem and solving a decrease in luminance and occurrence of a color difference due to an increase in resistance of a data line and a driving method thereof can be provided.

1 is a block diagram of a unit cell of a general liquid crystal display.
FIG. 2 is a block diagram of a liquid crystal display device driven by a conventional DRD (Double Rate Driving) method, and a diagram showing RGB liquid crystal cells and a degree of charging of each liquid crystal cell.
3 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
4 is a diagram illustrating a pixel structure constituting a liquid crystal display panel according to an exemplary embodiment of the present invention.
5 is a diagram illustrating a structure of a liquid crystal cell corresponding to a first horizontal line and a first vertical line.
6 is a diagram showing a schematic diagram of a connection relationship between a data line and an auxiliary data line.
7 is a diagram illustrating a data line to which an auxiliary data line is not connected.
8 is a diagram illustrating a data line to which an auxiliary data line is connected.
9 is a diagram showing polarities of data signals applied to liquid crystal cells according to an embodiment of the present invention.
10 is a diagram illustrating a Z-inversion driving method according to polarities of data signals applied to liquid crystal cells according to an exemplary embodiment of the present invention.
11 is a view showing an electrode structure of a liquid crystal cell according to an embodiment of the present invention, and a view showing a liquid crystal cell in which an auxiliary data line is formed.
12 is a diagram illustrating a liquid crystal cell in which an auxiliary data line is not formed.
13 and 14 are views showing the operation of a liquid crystal cell according to an embodiment of the present invention.
15 is a diagram illustrating an operation of a liquid crystal cell when a data open failure occurs.

Hereinafter, a liquid crystal display device and a driving method thereof according to an embodiment of the present invention will be described in detail with reference to the drawings. The following embodiments are provided as examples in order to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In addition, in the drawings, the size and thickness of the device may be exaggerated for convenience. Throughout the specification, the same reference numbers indicate the same elements.

3 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a liquid crystal display according to an embodiment of the present invention may include a liquid crystal display panel 200, a timing controller 300, a data driving circuit 400, and a gate driving circuit 500.

The liquid crystal display panel 200 has a liquid crystal layer formed between two glass substrates.

개의 액정셀(Clc)들을 포함하여 DRD 방식으로 구동된다. The liquid crystal display panel 200 includes d/2 (d is an even number) data lines (D1 to Dm/2; m in Dm/2 is the same number as d in d/2) and 2n (n is a natural number). ) Arranged in a matrix form by the cross structure of the gate lines G1 to G2n

It includes three liquid crystal cells Clc and is driven by the DRD method.

Data lines D1 to Dm/2, gate lines G1 to G2n, TFTs, and a storage capacitor Cst are formed on the lower glass substrate of the liquid crystal display panel 200.

The liquid crystal cells Clc are connected to the TFT and driven by an electric field between the pixel electrodes 220 and the common electrode 210.

A black matrix, a color filter, and a common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 200. The common electrode 210 is formed on an upper glass substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, and the IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode In the same horizontal electric field driving method, it is formed on the lower glass substrate together with the pixel electrode 210.

A polarizing plate is attached to each of the upper and lower glass substrates of the liquid crystal display panel 200 and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

The timing controller 300 uses timing signals such as a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), a data enable signal (DE), and a dot clock (DCLK) supplied from a system (not shown). A data control signal for controlling the operation timing of the driving circuit 400 and a gate control signal for controlling the operation timing of the gate driving circuit 500 are generated.

The data control signal is a data driving circuit based on a source start pulse (SSP) indicating a sampling start point of digital video data (RGB) in the data driving circuit 400, a rising edge, or a falling edge. A source sampling clock (SSC) instructing the latching operation of digital video data (RGB) within 400, a source output enable signal (SOE) instructing the output of the data driving circuit 400, and a liquid crystal display panel 200 ) And a polarity control signal POL indicating the polarity of the data voltage to be supplied to the liquid crystal cells Clc.

The gate control signal is input to a gate start pulse (GSP) indicating a start horizontal line from which scanning starts during one vertical period in which one screen is displayed, and a shift register in the gate driving circuit 500 to sequentially generate the gate start pulse (GSP). A gate shift clock signal (GSC) generated with a pulse width corresponding to the ON period of the TFT, as a timing control signal for shifting to, and a gate output enable signal (GOE) instructing the output of the gate driving circuit 500 And the like.

In addition, the timing controller 300 rearranges the digital video data RGB supplied from the system according to the resolution of the liquid crystal display panel 200 and supplies it to the data driving circuit 400.

The data driving circuit 400 latches the digital video data RGB under the control of the timing controller 300. In addition, the data driving circuit 400 converts digital video data (RGB) into an analog positive/negative gamma voltage according to a polarity control signal (POL) to generate a positive/negative analog data voltage, and converts the data voltage to data. It is supplied to the lines D1 to Dm/2.

To this end, the data driving circuit 400 may include a plurality of data driving ICs.

The gate driving circuit 500 generates a scan pulse for selecting a horizontal line of the liquid crystal display panel 200 to which an analog data voltage is to be supplied under the control of the timing controller 300, and converts the scan pulse to the gate lines G1 to G2n) is supplied sequentially.

To this end, the gate driving circuit 500 includes a shift register, a level shifter for converting the output signal of the shift register into a swing width suitable for TFT driving of the liquid crystal cell Clc, and an output circuit connected between the level shifter and the gate line. It may include a plurality of gate drive ICs each including.

4 is a diagram illustrating a pixel structure constituting a liquid crystal display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 4, liquid crystal cells Clc of the liquid crystal display panel 200 may include red, green, blue, and white liquid crystal cells.

The liquid crystal cell includes first and second thin film transistors each of which first and second gate lines are allocated and sharing one data line, first and second pixel electrodes connected to each of the first and second thin film transistors, and the It may include an auxiliary data line connecting the data line and the connection points of the first and second thin film transistors to each other.

Specifically, the liquid crystal display panel 200 includes d/2 (d is an even number) data lines (Dm/2) and 2n (n is a natural number) gate lines crossing the data lines (Dm/2). In addition, a liquid crystal cell formed in a region at which the data lines Dm/2 and the gate lines G2n intersect may be formed.

The liquid crystal cell may include first and second sub liquid crystal cells that share any one of the data lines Dm/2.

In the vertical lines VL defined by two adjacent data lines among the data lines Dm/2 and the horizontal lines HL defined by two adjacent gate lines among the gate lines G2n. , A liquid crystal cell and the vertical lines at an intersection of an m (m is a natural number)-th vertical line among the vertical lines VL and an n-1 (n is a natural number)-th horizontal line among the horizontal lines HL A liquid crystal cell at an intersection of the m-1th vertical line of VL and the nth horizontal line of the horizontal lines HL may share a data line, and data shared by the first and second sub-LCD cells. An auxiliary data line connecting a line and a connection point of the first and second sub-LCD cells to each other may be further formed on the liquid crystal display panel 200.

<Structure of the liquid crystal cell corresponding to the first horizontal line HL1 and the first to third vertical lines VL1 to VL3>

Looking at the connection structure of the liquid crystal cells Clc, the liquid crystal cells corresponding to the first horizontal line HL1 and the first vertical line VL1 may include first and second sub liquid crystal cells.

As shown in the drawing, the liquid crystal cell formed in the crossing region of the horizontal line HL and the vertical line VL includes first and second sub-liquid crystal cells, and the thin film transistor and pixel electrode on the left are referred to as first sub-liquid crystal cells, The thin film transistor and pixel electrode on the right may be referred to as a second sub liquid crystal cell.

The pixel electrodes Pi-1 and j-1 connected to the first gate line Gj-1 in the first sub liquid crystal cell are pixel electrodes connected to the second gate line Gj in the second sub liquid crystal cell They may be adjacent to each other and may be commonly connected to the first data line Di-1. Further, the pixel electrodes Pi-1 and j-1 connected to the first gate line Gj-1 and the pixel electrodes Pi-1 and j connected to the second gate line Gj are first auxiliary. It may be commonly connected to the data lines Dx-1 and y-1.

In the liquid crystal cells corresponding to the first horizontal line HL1 and the second vertical line VL2, the pixel electrodes Pi and j-1 connected to the first gate line Gj-1 are the second gate lines Gj. The pixel electrodes Pi and j connected to) may be adjacent to each other and may be commonly connected to the second data line Di. In addition, the pixel electrodes Pi and j-1 connected to the first gate line Gj-1 and the pixel electrodes Pi and j connected to the second gate line Gj are a second auxiliary data line Dx. ,y-1) can be connected in common.

In the liquid crystal cells corresponding to the first horizontal line HL1 and the third vertical line VL3, the pixel electrodes Pi+1 and j-1 connected to the first gate line Gj-1 are the second gate lines. The pixel electrodes Pi+1 and j connected to Gj may be adjacent to each other and may be commonly connected to the second data line Di+1. In addition, the pixel electrodes Pi+1 and j-1 connected to the first gate line Gj-1 and the pixel electrodes Pi+1 and j connected to the second gate line Gj are third auxiliary. It may be commonly connected to the data lines Dx+1 and y-1.

<Structure of liquid crystal cells corresponding to the second horizontal line HL2 and the first to third vertical lines VL1 to VL3>

In the liquid crystal cells corresponding to the second horizontal line HL1 and the first vertical line VL1, the pixel electrodes Pi and j+1 connected to the third gate line Gj+1 are the fourth gate line Gj. The pixel electrodes Pi and j+2 connected to +2) may be adjacent to each other and may be commonly connected to the second data line Di. Further, the pixel electrodes Pi and j+1 connected to the third gate line Gj+1 and the pixel electrodes Pi and j+2 connected to the fourth gate line Gj+2 are fourth auxiliary. It may be commonly connected to the data lines Dx,y+1.

In the liquid crystal cells corresponding to the second horizontal line HL1 and the second vertical line VL2, the pixel electrodes Pi+1 and j+1 connected to the third gate line Gj+1 are the fourth gate lines. The pixel electrodes Pi+1 and j+2 connected to (Gj+2) may be adjacent to each other and may be commonly connected to the third data line Di+1. Further, pixel electrodes Pi+1 and j+1 connected to the third gate line Gj+1 and pixel electrodes Pi+1 and j+2 connected to the fourth gate line Gj+2 May be commonly connected to the fifth auxiliary data lines Dx+1 and y+1.

In the liquid crystal cells corresponding to the second horizontal line HL1 and the third vertical line VL3, the pixel electrodes Pi+2 and j+1 connected to the third gate line Gj+1 are the fourth gate lines. The pixel electrodes Pi+2 and j+2 connected to (Gj+2) may be adjacent to each other and may be commonly connected to the fourth data line Di+2. Further, pixel electrodes Pi+2 and j+1 connected to the third gate line Gj+1 and pixel electrodes Pi+2 and j+2 connected to the fourth gate line Gj+2 May be commonly connected to the sixth auxiliary data lines Dx+2 and y+1.

Meanwhile, the structure of the liquid crystal cell corresponding to the third horizontal line HL3 corresponds to the structure of the liquid crystal cell of the first horizontal line HL1, and the structure of the liquid crystal cell corresponding to the fourth horizontal line HL4 is the second horizontal line. It corresponds to the structure of the liquid crystal cell of line HL2.

5 is a diagram illustrating a structure of a liquid crystal cell corresponding to a first horizontal line and a first vertical line.

Referring to FIG. 5, in the liquid crystal cell corresponding to the first horizontal line HL1 and the first vertical line VL1, the first thin film transistor TFT1 is generated by a gate signal of the first gate line Gj-1. It is controlled and may be connected between the first node N1 and the i-1 and j-1th pixel electrodes Pi-1 and j-1.

The first thin film transistor TFT1 is turned on by a gate signal of the first gate line Gj-1, and receives a data signal provided from the first data line Di-1 on the first node N1. It may be provided as the i-1 and j-1th pixel electrodes Pi-1 and j-1.

In the pixel electrodes corresponding to the first horizontal line HL1 and the first vertical line VL1, the second thin film transistor TFT2 is controlled by the gate signal of the second gate line Gj and the second node N2 And i-1 and j-th pixel electrodes Pi-1 and j.

The second thin film transistor TFT2 is turned on by a gate signal of the second gate line Gj, and the data signal provided from the first data line Di-1 on the second node N2 is i- It may be provided as the first and j-th pixel electrodes Pi-1 and j.

Further, the first auxiliary data lines D-1 and y-1 may be connected between the first and second nodes N1 and N2.

6 is a diagram showing a schematic diagram of a connection relationship between a data line and an auxiliary data line. 7 is a diagram illustrating a data line to which an auxiliary data line is not connected, and FIG. 8 is a diagram illustrating a data line to which an auxiliary data line is connected.

Referring to FIG. 6, auxiliary data lines Dx and y may be connected to a data line Di corresponding to an arbitrary vertical line VL for each horizontal line HL1 to HLn.

The auxiliary data lines Dx,y may be connected between first and second nodes N1 and N2 on the data line Di.

7 and 8, if the total resistance of the data line Di is nRi ohms when there is no auxiliary data line Dx,y, the data line Di is formed when the auxiliary data line Dx,y is formed. The total resistance of can be nRi/2. Accordingly, the total resistance value on the data line Di can be reduced.

In this way, the DRD structure can have a large impact on the load as the number of data lines is reduced by half, but line resistance can be reduced by connecting the auxiliary data lines (Dx,y) in parallel with the data lines (Di). As a result, it is possible to solve the problem of lowering of luminance and occurrence of color difference due to RC delay.

<Z-inversion operation>

9 is a diagram showing polarities of data signals applied to liquid crystal cells according to an embodiment of the present invention. 10 is a diagram illustrating a Z-inversion driving method according to polarities of data signals applied to liquid crystal cells according to an exemplary embodiment of the present invention.

9 and 10, a positive data voltage is applied to the first data line Di-1 and the third data line Di+1, and the second data line Di and the fourth data line Di+2) may be applied with a negative data voltage. That is, a data voltage of positive polarity may be applied to an odd-numbered data line and a data voltage of negative polarity may be applied to an even-numbered data line. Further, the present invention is not limited thereto, and a data voltage having a negative polarity may be applied to an odd numbered data line and a data voltage having a positive polarity may be applied to an even numbered data line.

When a positive data voltage is applied to the first data line Di-1, in the liquid crystal cells corresponding to the first horizontal line HL1 and the first vertical line VL1, the first gate line Gj-1 The pixel electrodes Pi-1 and j-1 connected to ), the pixel electrodes Pi-1 and j connected to the second gate line Gj, and the third horizontal line HL3 and the first vertical line ( In the liquid crystal cell corresponding to VL1), the pixel electrodes Pi-1 and j+3 connected to the fifth gate line Gj+3 and the pixel electrode Pi connected to the sixth gate line Gj+4 -1,j+4) can be applied with a positive data voltage.

In addition, when a data voltage of negative polarity is applied to the second data line Di, in the liquid crystal cells corresponding to the first horizontal line HL1 and the second vertical line VL2, the first gate line Gj-1 The pixel electrodes Pi and j-1 connected to, the pixel electrodes Pi and j connected to the second gate line Gj, and corresponding to the second horizontal line HL1 and the first vertical line VL1 In the liquid crystal cell, the pixel electrodes Pi and j+1 connected to the third gate line Gj+1, the pixel electrodes Pi and j+2 connected to the fourth gate line Gj+2, and the third 3 In the liquid crystal cell corresponding to the horizontal line HL1 and the second vertical line VL2, the pixel electrodes Pi and j+3 connected to the fifth gate line Gj+3 and the sixth gate line Gj A data voltage of negative polarity may be applied to the pixel electrodes Pi,j+4 connected to +4).

In addition, in the liquid crystal cells corresponding to the first horizontal line HL1 and the third vertical line VL3, the pixel electrodes Pi+1 and j-1 connected to the first gate line Gj-1 and the second In a liquid crystal cell corresponding to the pixel electrodes Pi+1 and j connected to the gate line Gj and the second horizontal line HL1 and the second vertical line VL2, the third gate line Gj+1 The connected pixel electrodes Pi+1 and j+1, the pixel electrodes Pi+1 and j+2 connected to the fourth gate line Gj+2, and the third horizontal line HL3 and the third vertical In the liquid crystal cell corresponding to the line VL3, the pixel electrodes Pi+1 and j+3 connected to the fifth gate line Gj+3 and the pixel electrode connected to the sixth gate line Gj+4 A negative data voltage may be applied to (Pi+1,j+4).

In the case of the Z inversion driving method, the polarity of the data voltage applied to each data line (Di) is maintained for one frame and is inverted in the next frame, so that the polarity of the data voltage alternates between positive and negative polarities for each pixel. Compared to repeating dot inversion driving, power consumption can be reduced.

11 is a view showing an electrode structure of a liquid crystal cell according to an embodiment of the present invention, and a view showing a liquid crystal cell in which an auxiliary data line is formed. 12 is a diagram showing a liquid crystal cell in which an auxiliary data line is not formed.

Referring to FIG. 11, a first layer formed on a lower substrate of the liquid crystal display panel 200 and connected to the pixel electrodes Pi and j corresponding to the second data line Di and the first gate line Gj-1 The thin film transistor TFT1 may include a first drain electrode drain1 and a U-shaped first source electrode source1 surrounding a portion of the first drain electrode drain1. Also, the second data line Di may be connected to the first source electrode source1.

In addition, a second thin film transistor TFT2 formed on the lower substrate of the liquid crystal display panel 200 and connected to the pixel electrodes Pi and j-1 corresponding to the second data line Di and the second gate line Gj. May include a second drain electrode drain2 and a U-shaped second source electrode source2 surrounding a portion of the second drain electrode drain2. Also, the second data line Di may be connected to the second source electrode source2.

Referring to FIG. 12, a black matrix is formed between the pixel electrodes Pi and j corresponding to the first gate line Gj-1 and the pixel electrodes Pi and j-1 corresponding to the second gate line Gj. The region BM may exist.

A black matrix may be formed in a region of the upper substrate corresponding to the black matrix correspondence region BM in the lower substrate.

Referring to FIG. 11, auxiliary data lines Dx and y-1 may be formed on the black matrix correspondence region BM, and the auxiliary data lines Dx and y-1 are connected to the first source electrode source1. The second source electrodes source2 may be connected to each other.

As described above, the auxiliary data lines Dx,y according to the exemplary embodiment of the present invention do not affect the aperture ratio by being formed in the black matrix correspondence region BM of the lower substrate corresponding to the region where the black matrix of the upper substrate is formed. Therefore, it is possible to reduce the resistance through the design of the mask without reducing the transmittance. In addition, since the auxiliary data lines Dx,y are formed in the black matrix correspondence area BM, the auxiliary data lines Dx,y can be easily added without changing process conditions or line widths of the data lines.

13 and 14 are views showing the operation of a liquid crystal cell according to an embodiment of the present invention. 15 is a diagram illustrating an operation of a liquid crystal cell when a data open failure occurs.

Referring to FIG. 13, when the first thin film transistor TFT1 is turned on by a high-level gate voltage of the first gate line Gj-1, the data voltage on the first data line Di-1 is the first It may be applied to the pixel electrodes Pi-1 and j-1 via the source and drain electrodes of the thin film transistor TFT1.

Referring to FIG. 14, when the second thin film transistor TFT2 is turned on by a high-level gate voltage of the second gate line Gj, the data voltage on the first data line Di-1 is the second thin film transistor. It may be applied to the pixel electrodes Pi-1 and j via the source and drain electrodes of TFT2.

Referring to FIG. 15, when a data open (DO) defect occurs in the first data line Di-1, the second thin film transistor TFT2 is generated by a high-level gate voltage of the second gate line Gj. ) Is turned on, the data voltage on the first data line Di-1 passes through the first auxiliary data lines Dx-1 and y-1 and the source and drain electrodes of the second thin film transistor TFT2. It may be applied to the electrodes Pi-1 and j.

Even in the case of such a data open failure, since the data voltage is applied to the pixel electrodes Pi-1 and j via the first auxiliary data lines Dx-1 and y-1, the liquid crystal cell does not operate and the image quality is reduced. It can prevent the problem of deterioration.

In the detailed description of the present invention described above, it has been described with reference to preferred embodiments of the present invention, but those skilled in the art or those of ordinary skill in the relevant technical field of the present invention described in the claims to be described later It will be appreciated that various modifications and changes can be made to the present invention without departing from the spirit and technical scope. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

100 liquid crystal display
200 LCD panel
300 timing controller
400 data drive circuit
500 gate driving circuit

Claims (11)

First and second thin film transistors each assigned to each of the first and second gate lines and sharing one data line, first and second pixel electrodes connected to each of the first and second thin film transistors, and the data line and the A liquid crystal display panel having a liquid crystal cell including auxiliary data lines connecting connection points of the first and second thin film transistors to each other;
Including,
The auxiliary data line is connected in parallel with the data line, and when the total resistance value of the data line without the auxiliary data line is nRi ohms, the total resistance value of the data line is nRi/2 ohm,
The first and second pixel electrodes are adjacent to each other on one horizontal line and are commonly connected to the one data line,
The auxiliary data line is re-connected from the one data line through a connection point of the first thin film transistor and a connection point of the second thin film transistor connected to the adjacent first and second pixel electrodes in one horizontal line. A liquid crystal display connected to the data line. The method of claim 1,
The first thin film transistor includes a first source electrode connected to the data line and a first drain electrode connected to the first pixel electrode,
The second thin film transistor includes a second source electrode connected to the data line and a second drain electrode connected to the second pixel electrode,
The auxiliary data line connects the first and second source electrodes to each other. The method of claim 2,
The liquid crystal display panel includes: a lower substrate on which the gate line, the data line, and the first and second thin film transistors are formed; And an upper substrate on which a color filter and a black matrix are formed,
The auxiliary data line is formed in a black matrix correspondence area of the lower substrate corresponding to the black matrix. d/2 (d is an even number) data lines;
2n (n is a natural number) gate lines crossing the data lines; And
A liquid crystal cell formed in an intersection region between the data lines and the gate lines; and
The liquid crystal cell includes first and second sub liquid crystal cells that share any one of the data lines,
In vertical lines defined by two adjacent data lines among the data lines and horizontal lines defined by two adjacent gate lines among the gate lines,
A liquid crystal cell at an intersection of an m (m is a natural number)-th vertical line among the vertical lines, an n-1 (n is a natural number)-th horizontal line among the horizontal lines, and an m-1-th vertical line among the vertical lines Among the horizontal lines, the liquid crystal cells in the crossing region of the n-th horizontal line share a data line,
When an auxiliary data line is connected in parallel to one of the data lines and the total resistance value of the data line without the auxiliary data line is nRi ohms, the total resistance value of the one data line is nRi/2 ohms. ,
The first and second pixel electrodes are adjacent to each other on one horizontal line and are commonly connected to the one data line,
The auxiliary data line is re-connected from the one data line through a connection point of the first thin film transistor and a connection point of the second thin film transistor connected to the adjacent first and second pixel electrodes in one horizontal line. A liquid crystal display connected to the data line. The method of claim 4,
The auxiliary data line connects a data line shared by the first and second sub-LCD cells to a connection point between the first and second sub-LCD cells. The method of claim 4,
A liquid crystal display device in which a polarity of a data voltage applied to any one of the data lines is maintained. The method of claim 6,
A liquid crystal display device in which polarities of data voltages applied to adjacent first and second data lines among the data lines are opposite. The method of claim 5,
The first sub liquid crystal cell includes a first thin film transistor and a first pixel electrode,
The second sub liquid crystal cell includes a second thin film transistor and a second pixel electrode,
The data line shared by the first and second sub-LCD cells includes a first node connected to the first thin film transistor and a second node connected to the second thin film transistor,
The auxiliary data line is connected between the first and second nodes. First and second thin film transistors each assigned to each of the first and second gate lines and sharing one data line, first and second pixel electrodes connected to each of the first and second thin film transistors, and the data line and the Including; a liquid crystal display panel having a liquid crystal cell including an auxiliary data line for connecting the connection points of the first and second thin film transistors to each other,
The first thin film transistor includes a first source electrode connected to the data line and a first drain electrode connected to the first pixel electrode,
The second thin film transistor includes a second source electrode connected to the data line and a second drain electrode connected to the second pixel electrode,
The auxiliary data line connects the first and second source electrodes to each other,
The first and second pixel electrodes are adjacent to each other on one horizontal line and are commonly connected to the one data line,
The auxiliary data line is re-connected from the one data line through a connection point of the first thin film transistor and a connection point of the second thin film transistor connected to the adjacent first and second pixel electrodes in one horizontal line. A liquid crystal display connected to the data line. d/2 (d is an even number) data lines;
2n (n is a natural number) gate lines crossing the data lines; And
A liquid crystal cell formed in an intersection region between the data lines and the gate lines; and
The liquid crystal cell includes first and second sub liquid crystal cells that share any one of the data lines,
In vertical lines defined by two adjacent data lines among the data lines and horizontal lines defined by two adjacent gate lines among the gate lines,
A liquid crystal cell at an intersection of an m (m is a natural number)-th vertical line among the vertical lines, an n-1 (n is a natural number)-th horizontal line among the horizontal lines, and an m-1-th vertical line among the vertical lines Among the horizontal lines, the liquid crystal cells in the crossing region of the n-th horizontal line share a data line,
A data line shared by the first and second sub-LCD cells and a connection point of the first and second sub-LCD cells are connected to each other,
The first and second pixel electrodes are adjacent to each other on one horizontal line and are commonly connected to the one data line,
The auxiliary data line is re-connected from the one data line through the connection point of the first thin film transistor and the second thin film transistor connected to the adjacent first and second pixel electrodes in one horizontal line. A liquid crystal display connected to the data line. The method of claim 10,
The first sub liquid crystal cell includes a first thin film transistor and a first pixel electrode,
The second sub liquid crystal cell includes a second thin film transistor and a second pixel electrode,
The data line shared by the first and second sub-LCD cells includes a first node connected to the first thin film transistor and a second node connected to the second thin film transistor,
The auxiliary data line is connected between the first and second nodes.

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