KR101818248B1 - Liquid crystal display - Google Patents

Abstract

A liquid crystal display device according to the present invention includes: a first liquid crystal cell pair including a first common electrode and connected to two gate lines sharing a data line to display an image of a first polarity; A second liquid crystal cell pair adjacent to the first pair of liquid crystal cells in a horizontal direction and a vertical direction, the second liquid crystal cell pair including a second common electrode and connected to two gate lines sharing one data line to display an image of a second polarity; A radix common line to which a common voltage of one of a first level and a second level is applied; An excellent common line to which a common voltage of the other one of the first level and the second level is applied; A first connection pattern connecting the odd common line and the first common electrode; And a second connection pattern connecting the common stripe and the second common electrode.
The present invention has a remarkable effect of suppressing the generation of horizontal crosstalk and greatly reducing the area where the black luminance is increased.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device for swinging a common voltage.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to various display devices such as portable information devices, office equipment, computers, and televisions. Liquid crystal cells of a liquid crystal display display an image by changing the transmittance according to the potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode.

A common voltage swing technique for swinging a common voltage in units of horizontal lines in order to reduce the output swing width of a data driver in a liquid crystal display device is known. Among these, there is a line-inversion technique for changing the display polarity in the display panel to the horizontal pixel line unit while controlling the polarity of the data output from the data driver in a dot-inversion manner. Such conventional line-inversion technology is strong against vertical crosstalk, but is weak against horizontal crosstalk.

When a white window pattern is displayed on the display panel having the connection configuration as shown in FIG. 1 in the background of the halftone as shown in FIG. 1 for a line-inversion implementation, a line-like horizontal cross Torque is generated. The cause of the horizontal crosstalk is caused by the shift of the common voltage due to the asymmetry of the voltage variation between the adjacent data lines. This will be described in detail as follows.

2 is an enlarged view of "A1" Referring to FIG. 2, the liquid crystal cells arranged on the same pixel horizontal line in the display panel are connected to the TFTs arranged in zig-zag along the horizontal direction in the upper and lower gate lines. The levels of the common voltage Vcom in the odd-numbered pixel horizontal line and the even-numbered pixel horizontal line are inverted from each other in frame units. For example, a common electrode (Vcom (H)) of a high level is applied to the common electrode of the liquid crystal cells arranged in the odd-numbered pixel horizontal line in the specific frame through the odd common line (see Fig. 4) A low-level common voltage Vcom (L) may be applied to common electrodes of the arranged liquid crystal cells through an excellent common line (see FIG. 4).

When the common voltage Vcom swings between 0V and 8V and the data voltage varies between 8V and 0V, the liquid crystal molecules connected to the nth data line Dn and the (n + 1) th data line Dn + In the cells, a data voltage of 4V for the negative halftone gradation implementation, a data voltage of 8V for the positive (+) white gradation implementation, 0V for the negative (-) white gradation implementation Voltage, and a data voltage of 8V for positive (+) white gradation implementation are applied. The liquid crystal cells connected to the (n + 1) th data line Dn + 1 in the same pixel horizontal line are connected to the n-th data line Dn, because the adjacent liquid crystal cells in each pixel horizontal line are connected to different gate lines The data voltage is applied later than the liquid crystal cell by one horizontal period (1H).

The application timing of the data voltages supplied to the liquid crystal cells connected to the nth data line Dn and the (n + 1) th data line Dn + 1 is shown in FIG. In Fig. 3, the dashed line shows that the data output channels are shorted to each other in the horizontal blank period, so that the charge sharing voltage is being applied to all the data lines. 3, when the second gate line G 2 is activated, the potential of the n-th data line Dn varies by (+) 4 V from 4 V to (4) ) Changes from 4V to 4V by 0V. The ripple component is mixed in the common voltage Vcom due to the coupling noise due to the voltage variation asymmetry between the adjacent data lines, and the common voltage Vcom becomes higher than the original level. As a result, since the common voltages applied to the first and second pixel horizontal lines HL # 1 and HL2 connected to the second gate line G② become higher than the original levels 8V and 0V, respectively, As shown in the figure, the liquid crystal cells of the first pixel horizontal line HL # 1 connected to the second gate line G & cir & The liquid crystal cells of the two-pixel horizontal line HL # 2 are displayed with darker gradations than the desired halftone. On the other hand, when the third gate line G3 is activated, the potential of the (n + 1) th data line Dn + 1 changes to (-) 8V from 8V at It varies from 4V to 8V by (+) 4V. Due to the voltage variation asymmetry between the adjacent data lines, the ripple component is mixed in the common voltage Vcom due to the coupling noise, and the common voltage Vcom becomes lower than the original level. As a result, since the common voltages applied to the second and third pixel horizontal lines HL # 2 and HL3 connected to the third gate line G 3 become lower than the original levels (0V and 8V) As shown in the figure, the liquid crystal cells of the second pixel horizontal line HL # 2 connected to the third gate line G < 3 > The liquid crystal cells of the three-pixel horizontal line HL # 3 display darker gradations than the desired halftone.

The change in the luminance of the liquid crystal cells causes the bright line cross-talk and the dark line cross-talk as shown in FIG. The bright line crosstalk is observed in the first pixel horizontal line (HL # 1) including the liquid crystal cells having a lighter gradation than the middle gradation. The dark line crosstalk is observed in the third pixel horizontal line (HL # 3) including the liquid crystal cells that are darker than the halftone. In the second pixel horizontal line HL2, the liquid crystal cells having darker gradation than the intermediate gradation and the liquid crystal cells having the lower gradation than the middle gradation are included, and the desired halftone is visually canceled. On the other hand, due to the characteristics of the gamma curve, the ripple of the common voltage due to the coupling noise hardly affects the luminance of the liquid crystal cells displaying the white gradation.

The conventional line inversion technology has another problem that the above-mentioned horizontal crosstalk is generated, and the region where the black luminance is raised near the BM region where the gate line is covered with the black matrix is wide. The reason why the black luminance is increased is that as shown in Fig. 4, the odd common line and the superior common line for applying the common voltage Vcom are arranged so as to overlap with the pixel electrode in the vicinity of the gate line, An undesired electric field is applied to the liquid crystals in the pixel region.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a liquid crystal display device capable of suppressing generation of horizontal crosstalk and reducing an area where black brightness is increased.

According to an aspect of the present invention, there is provided a liquid crystal display device including a first common electrode, a first common electrode connected to two gate lines sharing a data line, Liquid crystal cell pairs; A second liquid crystal cell pair adjacent to the first pair of liquid crystal cells in a horizontal direction and a vertical direction, the second liquid crystal cell pair including a second common electrode and connected to two gate lines sharing one data line to display an image of a second polarity; A radix common line to which a common voltage of one of a first level and a second level is applied; An excellent common line to which a common voltage of the other one of the first level and the second level is applied; A first connection pattern connecting the odd common line and the first common electrode; And a second connection pattern connecting the common stripe and the second common electrode.

Wherein the first pair of liquid crystal cells and the second pair of liquid crystal cells are alternately arranged in the horizontal direction to form a pixel horizontal line; Wherein the pixel horizontal line is assigned the two gate lines; The odd common line and the even common line are alternately arranged between vertically adjacent gate lines assigned to different pixel horizontal lines.

The first connection pattern connects the first common electrode of the first pair of liquid crystal cells arranged in the nth pixel horizontal line and the nth data line and the ninth common line, Connecting the first common electrode of the first liquid crystal cell pair and the ninth common line, which are disposed in the first liquid crystal cell pair and share the (n-1) th data line; The second connection pattern connects the second common electrode of the second liquid crystal cell pair disposed in the (n-1) th pixel horizontal line and the nth data line, and the pseudo common line to each other, And connects the second common electrode of the second liquid crystal cell pair shared with the (n-1) th data line and the common common line to each other.

Wherein the ninth common line is formed on the same layer as the gate lines, the first common electrode is formed on the ninth common line with a gate insulating film and a protective film interposed therebetween; The first connection pattern connects the ninth common line and the first common electrode through a contact hole passing through the gate insulating film and the protective film.

The excellent common line is formed on the same layer as the gate lines, the second common electrode is formed on the excellent common line with a gate insulating film and a protective film interposed therebetween; And the second connection pattern connects the excellent common line and the second common electrode through a contact hole passing through the gate insulating layer and the protective layer.

The liquid crystal display device includes a third connection pattern for connecting the first common electrodes disposed on neighboring pixel horizontal lines to each other; And a fourth connection pattern connecting the second common electrodes disposed on neighboring pixel horizontal lines to each other.

The third connection pattern includes a first common electrode of a first pair of liquid crystal cells arranged in an n-th pixel horizontal line and sharing an n-th data line, a second common electrode of a first common electrode arranged in an n- Connecting the first common electrodes of the first pair of shared liquid crystal cells to each other; The fourth connection pattern includes a second common electrode of a second liquid crystal cell pair disposed on an n-th pixel horizontal line and sharing an (n-1) -th data line, And the second common electrode of the second pair of liquid crystal cells sharing the line are connected to each other.

The common electrodes of the first and second liquid crystal cell pairs are connected in a network structure by the first to fourth connection patterns.

The liquid crystal display device according to the present invention suppresses the generation of horizontal crosstalk through arrangement of liquid crystal cell pairs having different polarities, mesh connection structure of common electrodes, arrangement of common lines, and the like, There is a remarkable effect that the area to be formed can be greatly reduced.

1 is a diagram showing an example in which a horizontal crosstalk occurs when a white window pattern is displayed with a halftone background.
Fig. 2 is an enlarged view of "A1" in Fig. 1, showing a pixel connection configuration of a display panel; Fig.
3 is a view showing an application timing of a data voltage supplied to liquid crystal cells connected to the nth and (n + 1) th data lines;
4 is a view showing a position in which a common line of the prior art is disposed;
5 is a view illustrating a liquid crystal display device according to an embodiment of the present invention.
FIG. 6 illustrates an example of a common voltage and a data voltage in consecutive frames; FIG.
7 is a view showing a pixel array of a liquid crystal display panel.
8 is a cross-sectional view including the first and second connection patterns of Fig. 7; Fig.
9 is a view showing that common electrodes of a pair of first and second liquid crystal cells are connected in a network structure by first to fourth connection patterns;
10 is a cross-sectional view including third and fourth connection patterns;
11 is a diagram showing a gray scale display state of a pixel in a case where a white window pattern is displayed on a liquid crystal display panel according to an embodiment of the present invention with a halftone as a background.
12 is a view showing application timing of data voltages supplied to pairs of liquid crystal cells connected to nth and (n + 1) th data lines;
13 is a diagram showing that an intermediate gradation is displayed by gradation averaging.
14 is a diagram showing a display state when a white window pattern is displayed.
15 is a view showing a relationship between a potential difference and a transmittance;
16 is a detailed view showing a layout of a common line according to the present invention;

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 5 to 16. FIG.

5 shows a liquid crystal display according to an embodiment of the present invention.

5, a liquid crystal display according to an embodiment of the present invention includes a liquid crystal display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and a common voltage generating circuit 17 .

In the liquid crystal display panel 10, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 10 includes liquid crystal cells Clc arranged in a matrix form by an intersection structure of the data lines 15 and the gate lines 16. [

On the lower glass substrate of the liquid crystal display panel 10, a pixel array is formed. The pixel array includes liquid crystal cells Clc formed at intersections of the data lines 15 and the gate lines 16, TFTs connected to the pixel electrodes 1 of the liquid crystal cells, A common electrode 2 and a storage capacitor Cst. The pixel array can be implemented as shown in FIG. 7 to suppress the generation of the horizontal crosstalk. The liquid crystal cells Clc are connected to the TFT and driven by the electric field between the pixel electrodes 1 and the common electrode 2. [ On the upper glass substrate of the liquid crystal display panel 10, a black matrix, a color filter, and the like are formed. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system.

The liquid crystal display panel 10 applicable to the present invention may be implemented in any liquid crystal mode as well as a TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS . The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 11 receives digital video data RGB of an input image from the system board 14 through a low voltage differential signaling (LVDS) interface method and converts the digital video data RGB of the input video into mini-LVDS And supplies it to the data driving circuit 12 through an interface method. The timing controller 11 aligns the digital video data (RGB) input from the system board 14 in accordance with the configuration of the pixel array as shown in FIG. 7, and supplies the data to the data driving circuit 12.

The timing controller 11 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock CLK from the system board 14, And generates control signals for controlling the operation timing of the drive circuit 12 and the gate drive circuit 13. [ The control signals include a gate timing control signal for controlling the operation time of the gate drive circuit 13, a data timing control signal for controlling the operation timing of the data drive circuit 12 and the vertical polarity of the data voltage. The timing controller 11 controls the timing controller 11 so that the digital video data RGB input at a frame frequency of 60 Hz is displayed on the pixel array of the liquid crystal display panel 10 at a frame frequency of 60 x i The frequency of the timing control signal and the data timing control signal can be multiplied by a frame frequency of 60 x i Hz.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to the gate drive IC which generates the first gate pulse to control the gate drive IC so that the first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a vertical polarity control signal (POL), a source output enable signal (SOE) Mux control signals MC1 and MC2, and the like. The source start pulse SSP controls the data sampling start timing of the data driving circuit 12. The source sampling clock SSC is a clock signal for controlling sampling timing of data in the data driving circuit 12 on the basis of the rising or falling edge. The vertical polarity control signal POL controls the vertical polarity of the data voltages sequentially output from each of the source drive ICs. The source output enable signal SOE controls the output timing of the data driving circuit 12.

The data driving circuit 12 may include a plurality of source drive ICs (Integrated Circuit). Each of the source driver ICs of the data driving circuit 12 includes a shift register, a latch array, a digital-analog converter, an output circuit, and the like. The data driving circuit 12 latches the digital video data RGB according to the data timing control signal, converts the latched data into analog positive / negative gamma compensation voltages, and supplies data voltages whose polarities are inverted at predetermined intervals to data And outputs it to the lines 15.

The data voltages continuously output from the respective channels of the source drive ICs are inverted in a vertical two dot pattern, that is, a repetition pattern of "- - + +" or "+ + - - . The output voltages of the data voltages simultaneously output from the channels of the source drive ICs are determined such that the polarity is inverted in a horizontal one dot pattern, that is, a repetition pattern of "+" or "+ -" as shown in FIG. The polarity of the data voltage is "+" if its voltage level is higher than the common voltage, and "-"

The gate drive circuit 13 may include a plurality of gate drive ICs. The gate driving circuit 13 sequentially supplies gate pulses to the gate lines 16 in accordance with gate timing control signals using a shift register and a level shifter. The shift register of the gate drive circuit 13 may be formed directly on the lower glass substrate according to a GIP (Gate In Panel) method.

The common voltage generating circuit 17 generates a high level common voltage Vcom (H) and a low level common voltage Vcom (L). The common voltage generating circuit 17 alternately supplies the common voltage Vcom (H) of the high level and the common voltage Vcom (L) of the low level to the odd common line of the liquid crystal display panel 10 do. The common voltage generating circuit 17 alternately supplies the common voltage Vcom (H) of the high level and the common voltage Vcom (L) of the low level to the common lines of the liquid crystal display panel 10 But supplies a common voltage at a level opposite to that of the common line.

When the common voltage Vcom swings between 0V (Vcom (L)) and 8V (Vcom (H)) and the data voltage varies between 8V and 0V, the consecutive frames Fn and Fn + An example of the common voltage Vcom and the data voltage Vdata is shown in Fig. In FIG. 6, 'CSV' indicates a charge sharing voltage. The charge sharing voltage CSV is commonly supplied to the data lines through the data output channels that are shorted to each other in the horizontal blanking period. When the data voltage changes between 0V and 8V, the level of the charge sharing CSV becomes 4V.

7 shows a pixel array of the liquid crystal display panel 10. Fig. 8 shows a cross section including the first and second connection patterns of FIG. 9 shows that the common electrodes of the first and second liquid crystal cell pairs are connected in a network structure by the first to fourth connection patterns. 10 shows a cross section including third and fourth connection patterns.

7, the pixel array according to the exemplary embodiment of the present invention includes a plurality of first liquid crystal cell pairs PLC1, a plurality of second liquid crystal cell pairs PLC2, an odd common line OVCL, an excellent common line EVCL, And first to fourth connection patterns PTN1 to PTN4.

One data line and two gate lines are allocated to the first liquid crystal cell pair PLC1. The first liquid crystal cell pair PLC1 includes a first common electrode 2A and is connected to two gate lines sharing one data line to display a first polarity image. The first liquid crystal cell pair PLC1 includes a 1-1 liquid crystal cell disposed between any one of the two gate lines and the shared data line and a second liquid crystal cell arranged between the other one of the two gate lines And a 1-2 liquid crystal cell disposed between the shared data lines.

One data line and two gate lines are allocated to the second liquid crystal cell pair PLC2. The second liquid crystal cell pair PLC2 includes a second common electrode 2B and is connected to two gate lines while sharing one data line to display a second polarity (-) image. The second liquid crystal cell pair PLC2 includes a second-1 liquid crystal cell disposed between any one of the two gate lines and the shared data line, and the other of the two gate lines, And a second -2 liquid crystal cell disposed between the shared data lines.

The first liquid crystal cell pair PLC1 and the second liquid crystal cell pair PLC2 are disposed adjacent to each other in the horizontal direction and the vertical direction. The second liquid crystal cell pairs PLC2 are disposed adjacent to the first liquid crystal cell pair PLC1 and the first liquid crystal cell pairs PLC1 are disposed adjacent to the upper and lower sides of the second liquid crystal cell pair PLC2. The first liquid crystal cell pairs PLC1 are adjacent to each other in the diagonal direction, and the second liquid crystal cell pairs PLC2 are adjacent to each other in the diagonal direction.

The first liquid crystal cell pair PLC1 and the second liquid crystal cell pair PLC2 are alternately arranged in the horizontal direction to form a plurality of pixel horizontal lines HL # (n-1) to HL # (n + 2). Two gate lines are assigned to each pixel horizontal line. For example, the third gate line G 3 and the fourth gate line G 4 are allocated to the n-th pixel horizontal line HL # (n).

A common voltage Vcom (H) of a high level and a common voltage Vcom (L) of a low level are alternately supplied to the odd and even common lines OVCL and EVCL alternately in the frame period. Hereinafter, it is assumed that the low level common voltage Vcom (L) is supplied to the odd common line OVCL and the high level common voltage Vcom (H) is applied to the even common line EVCL.

The odd common line OVCL and the excellent common line EVCL are assigned to different pixel horizontal lines and are alternately arranged between vertically adjacent gate lines. For example, the odd-numbered common line OVCL is allocated to the fourth gate line G4 allocated to the n-th pixel horizontal line HL # (n) and the n + 1-th pixel horizontal line HL # (n + 1) And the extra common line EVCL is disposed between the fifth gate line G5 and the sixth gate line G6 allocated to the (n + 1) th pixel horizontal line HL # (n + 1) Is disposed between the seventh gate line G 할당 allocated to the pixel horizontal line HL # (n + 2). By disposing the common lines OVCL and EVCL between the gate lines, the gate lines are covered with the black matrix This has the effect of reducing the area where the black luminance is raised near the BM area, which will be described later with reference to FIG.

The first connection pattern PTN1 electrically connects the first common electrode 2A of the first liquid crystal cell pair PLC1 to the odd common line OVCL. In other words, the first connection pattern PTN1 is connected to the first common electrode of the first liquid crystal cell pair PLC1 disposed in the nth pixel horizontal line HL # (n) and sharing the nth data line D (n) (N-1) -th pixel horizontal line HL # (n + 1) and connecting the electrode 2A and the nose common line OVCL to each other, And the first common electrode 2A and the radial common line OVCL of the first liquid crystal cell pair PLC1 sharing the common liquid crystal cell pair PLC1. As shown in FIG. 8, the odd common line OVCL is formed on the same layer as the gate lines, and the first common electrode 2A is formed on the odd common line OVCL with the gate insulating film and the protective film sandwiched therebetween do. Accordingly, the first connection pattern PTN1 connects the ninth common line OVCL and the first common electrode 2A through the contact hole CT through the gate insulating film and the protective film.

The second connection pattern PTN2 electrically connects the second common electrode 2B of the second liquid crystal cell pair PLC2 to the common common line EVCL. In other words, the second connection pattern PTN2 is a second liquid crystal cell pair PLC2 arranged in the (n-1) -th pixel horizontal line HL # (n-1) and sharing the n-th data line D (n) (N-1) -th data line D (n-1) arranged in the n-th pixel horizontal line HL # (n) and connecting the second common electrode 2B of the n- And the second common electrode 2B of the second liquid crystal cell pair PLC2 sharing the common common line EVCL. As shown in FIG. 8, the excellent common line EVCL is formed on the same layer as the gate lines, and the second common electrode 2B is formed on the excellent common line EVCL with the gate insulating film and the protective film sandwiched therebetween do. Accordingly, the second connection pattern PTN2 connects the common common electrode line EVCL and the second common electrode 2B through the contact hole CT through the gate insulating layer and the protective layer.

The first connection pattern PTN1 connects the first common electrodes 2A of the first liquid crystal cell pairs PLC1 that are diagonally adjacent to each other and the second connection pattern PTN2 connects the first common electrodes 2A of the first liquid crystal cell pairs PLC1, And the second common electrode 2B of the cell pair PLC2. 9, a third connection pattern PTN3 for secondarily connecting the first common electrodes 2A of the pair of first liquid crystal cells PLC1, which are diagonally adjacent to each other, And a fourth connection pattern PTN4 for secondarily connecting the second common electrodes 2B of the second pair of liquid crystal cells PLC2 that are diagonally adjacent to each other.

The third connection pattern PTN3 is connected to the first common electrode 2A (n) of the first liquid crystal cell pair PLC1 disposed in the nth pixel horizontal line HL # (n) and sharing the nth data line D (n) Of the first liquid crystal cell pair PLC1 arranged in the n-1-th horizontal pixel line HL # (n-1) and sharing the n + 1-th data line D (n + 1) And the electrodes 2A are connected to each other. The third connection pattern PTN3 connects the first common electrodes 2A of the first liquid crystal cell pairs PLC1, which are diagonally adjacent to each other on the gate insulating film and the protective film, as shown in FIG.

The fourth connection pattern PTN4 is connected to the second liquid crystal cell pair PLC2 arranged in the n-th pixel horizontal line HL # (n) and sharing the n-1th data line D (n-1) A second liquid crystal cell pair PLC2 arranged in the (n + 1) th pixel horizontal line HL # (n + 1) and sharing the n-2th data line D (n-2) And the second common electrode 2B of the pixel electrode 2B are connected to each other. The fourth connection pattern PTN4 connects the second common electrodes 2B of the second liquid crystal cell pair PLC2, which are diagonally adjacent to each other on the gate insulating film and the protective film, as shown in FIG.

The common voltage can be varied by the parasitic capacitance generated in the overlap region of the common lines (OVCL, EVCL) and the data line. When the common electrodes of the liquid crystal cell pairs are connected by the network structure using the first to fourth connection patterns PTN1 to PTN4 as shown in FIG. 9, there is an effect that the noise component of the common voltage due to the parasitic capacitance is dispersed. The first to fourth connection patterns PTN1 to PTN4 may include a transparent metal material (ITO) or an opaque metal material (MoTi).

11 shows the gradation display state of a pixel in a case where a white window pattern is displayed on a liquid crystal display panel 10 according to an embodiment of the present invention with a halftone as a background. Fig. 12 shows the application timing of the data voltages supplied to the liquid crystal cell pairs connected to the nth and (n + 1) th data lines. 13 shows the principle in which the horizontal crosstalk is suppressed by the averaging of the display gradation.

The principle of suppressing the generation of the horizontal crosstalk will be described with reference to FIGS. 11 to 13 as follows.

The common voltage Vcom (L) of 0V is applied to the odd common line OVCL and the common voltage Vcom (H) of 8V is applied to the even common line EVCL and the data voltage is 8V to 0V . ≪ / RTI > 11, a common voltage Vcom (L) of 0 V is applied to the liquid crystal cell pairs having the positive polarity (+) and a common voltage Vcom (H) is applied to the liquid crystal cell pairs having the negative polarity (- Respectively. As can be seen from the characteristic curve of the potential difference (V) -transmittance (T) and the gray scale of the liquid crystal cell, the larger the potential difference (V) between the data voltage and the common voltage becomes, (V) becomes smaller, it becomes closer to black gradation.

The data voltages Vdata and Vdata for the negative gray scale implementation are applied to the left liquid crystal cell of each pair of the liquid crystal cells sequentially arranged along the vertical direction sharing the nth data line D (n) + 4V data voltage (Vdata) for implementing the intermediate gray level, a 4V data voltage (Vdata) for the negative gray level implementation, and a 4V data voltage (Vdata) for the positive gray level implementation. . In the right liquid crystal cell of each pair of liquid crystal cells sequentially sharing the nth data line D (n) and arranged in the vertical direction, a data voltage (Vdata) of 4V for implementing a negative (- A data voltage of 8V for the polarity (+) white gradation implementation, a data voltage of 0V (Vdata) for the negative white gradation implementation, a data voltage of 8V for the positive polarity white gradation implementation (Vdata) Vdata) is applied.

A data voltage Vdata of 4V is applied to left and right liquid crystal cells of the pair of liquid crystal cells sequentially sharing the (n + 1) th data line D (n + 1) A data voltage of 0 V for implementing a negative (-) white gradation, a data voltage of 8 V for implementing a positive (+) white gradation, a data of 0 V for implementing a negative (-) white gradation The voltage Vdata is applied in common.

The application timing of the data voltages supplied to the liquid crystal cell pairs connected to the nth data line D (n) and the (n + 1) th data line D (n + 1) is shown in FIG. In Fig. 12, the dotted line indicates the voltage variation due to the charge sharing voltage. 12, when the third gate line G 3 is activated, the potential of the n + 1 th data line Dn + 1 changes from 0V to 4V at 4V, (-) 4V from 4V to 0V. The common voltage Vcom becomes lower than the original level due to the influence of the coupling noise due to the asymmetry of the voltage variation amount. As a result, since the common voltage applied to the n-th pixel horizontal line HL # (n) connected to the third gate line G (3) is lower than the original level (8V, 0V) The positive polarity (+) liquid crystal cells of the n-th pixel horizontal line HL # (n) connected to the third gate line G (n) The negative polarity (-) liquid crystal cells of the connected n-th pixel horizontal line HL # (n) are displayed with gradations darker than the desired halftone as shown in FIG.

The potential of the (n + 1) th data line Dn + 1 changes from 0V to (-) 4V while the potential of the nth data line Dn changes from 8V to 8V by (+) 8V. The common voltage Vcom becomes higher than the original level due to the influence of the coupling noise due to the asymmetry of the voltage variation amount. As a result, since the common voltage applied to the (n + 1) th pixel horizontal line HL # (n + 1) connected to the fifth gate line G5 is higher than the original level (8V, 0V) The negative polarity (-) liquid crystal cells of the (n + 1) -th pixel horizontal line HL # (n + 1) connected to the line G5 ' The positive polarity (+) liquid crystal cells of the (n + 1) -th pixel horizontal line HL # (n + 1) connected to the fifth gate line G5 .

The potential of the (n + 1) th data line Dn + 1 is changed from 8V to (+) 4V while the potential of the nth data line Dn is changed from 0V to It changes by (-) 8V to 0V. The common voltage Vcom becomes lower than the original level due to the influence of the coupling noise due to the asymmetry of the voltage variation amount. As a result, since the common voltage applied to the (n + 2) th pixel horizontal line HL # (n + 2) connected to the seventh gate line G⑦ becomes lower than the original level (8V, 0V) The positive polarity (+) liquid crystal cells of the (n + 2) -th pixel horizontal line HL # (n + 2) connected to the line G (7) The negative polarity (-) liquid crystal cells of the (n + 2) -th pixel horizontal line HL # (n + 2) connected to the seventh gate line G (7) .

Thus, in the n-th to (n + 2) -th pixel horizontal lines HL # (n) to HL # (n + 2) in the halftoneregion region, the liquid crystal cells partially display grayscale brighter than the halftone The gradation darker than the intermediate gradation is displayed. Hence, the gradation levels brighter than the halftone gradation and darker gradations than the halftone gradation are offset from each other by the averaging effect shown in Fig. 13, so that the nth to (n + 2) th horizontal lines HL # (n + 2)) is visually recognized at a normal halftone. As a result, even if a white window pattern is displayed on the liquid crystal display panel 10 with a halftone background as shown in Fig. 14, the horizontal crosstalk is not generated. On the other hand, due to the characteristics of the gamma curve, the ripple of the common voltage due to the coupling noise hardly affects the luminance of the liquid crystal cells displaying the white gradation.

16 shows the arrangement of common lines in detail according to the present invention.

Referring to FIG. 16, the odd common line and the common common line for applying the common voltage are disposed between neighboring gate lines in the BM region covered with the black matrix, respectively. By disposing the common line between the gate lines in this manner, it is possible to greatly reduce an undesired electric field from being applied to the liquid crystal in the pixel region close to the BM region. As a result, according to the present invention, the region where the black luminance is raised near the BM region where the gate line is covered with the black matrix is drastically reduced.

As described above, the liquid crystal display according to the present invention suppresses the occurrence of horizontal crosstalk through arrangement of liquid crystal cell pairs having different polarities, mesh connection structure of common electrodes, arrangement position of common lines, and the like In addition, there is a remarkable effect that the region where the black luminance is increased can be greatly reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: liquid crystal display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
17: Common voltage generating circuit

Claims (10)

A first liquid crystal cell pair including a first common electrode and sharing one data line and connected to two gate lines to display an image of a first polarity;
A second liquid crystal cell pair adjacent to the first pair of liquid crystal cells in a horizontal direction and a vertical direction, the second liquid crystal cell pair including a second common electrode and connected to two gate lines sharing one data line to display an image of a second polarity;
A radix common line to which a common voltage of one of a first level and a second level is applied;
An excellent common line to which a common voltage of the other one of the first level and the second level is applied;
A first connection pattern connecting the odd common line and the first common electrode; And
And a second connection pattern connecting the excellent common line and the second common electrode,
Wherein the first pair of liquid crystal cells and the second pair of liquid crystal cells are alternately arranged in the horizontal direction to form a pixel horizontal line;
Wherein the pixel horizontal line is assigned the two gate lines;
Wherein the odd-numbered common lines and the odd-numbered common lines are allocated to different pixel horizontal lines and are alternately arranged between vertically adjacent gate lines. delete The method according to claim 1,
The first connection pattern connects the first common electrode of the first pair of liquid crystal cells arranged in the nth pixel horizontal line and the nth data line and the ninth common line, Connecting the first common electrode of the first liquid crystal cell pair and the ninth common line, which are disposed in the first liquid crystal cell pair and share the (n-1) th data line;
The second connection pattern connects the second common electrode of the second liquid crystal cell pair disposed in the (n-1) th pixel horizontal line and the nth data line, and the pseudo common line to each other, And the second common electrode of the second pair of liquid crystal cells, which are disposed in the second common electrode and share the (n-1) -th data line, and the common common line. The method according to claim 1,
Wherein the ninth common line is formed on the same layer as the gate lines, the first common electrode is formed on the ninth common line with a gate insulating film and a protective film interposed therebetween;
Wherein the first connection pattern connects the nonsense common line and the first common electrode through a contact hole passing through the gate insulating layer and the protection layer. The method according to claim 1,
The excellent common line is formed on the same layer as the gate lines, the second common electrode is formed on the excellent common line with a gate insulating film and a protective film interposed therebetween;
And the second connection pattern connects the common common line and the second common electrode through a contact hole passing through the gate insulating layer and the protection layer. The method according to claim 1,
A third connection pattern connecting the first common electrodes disposed on neighboring pixel horizontal lines to each other; And
And a fourth connection pattern connecting the second common electrodes disposed on adjacent pixel horizontal lines to each other. The method according to claim 6,
The third connection pattern includes a first common electrode of a first pair of liquid crystal cells arranged in an n-th pixel horizontal line and sharing an n-th data line, a second common electrode of a first common electrode arranged in an n- Connecting the first common electrodes of the first pair of shared liquid crystal cells to each other;
The fourth connection pattern includes a second common electrode of a second liquid crystal cell pair disposed on an n-th pixel horizontal line and sharing an (n-1) -th data line, And the second common electrode of the second pair of liquid crystal cells sharing the line are connected to each other. The method according to claim 6,
And common electrodes of the first and second liquid crystal cell pairs are connected in a network structure by the first to fourth connection patterns. 5. The method of claim 4,
Wherein the gate insulating film covers the gate lines and the odd common line and the first common electrode is disposed on the protective film to be laminated on the gate insulating film, And is arranged to cover one end of the common line. 6. The method of claim 5,
Wherein the gate insulating film covers the gate lines and the excellent common line and the second common electrode is disposed on the protective film stacked on the gate insulating film, And is arranged to cover one end of the common line.

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