KR102009441B1 - Liquid crystal display - Google Patents

Abstract

A liquid crystal display device according to the present invention includes a liquid crystal display panel in which a plurality of gate lines and a plurality of data lines intersect and liquid crystal cells are formed at an intersection thereof; And a data driving circuit including output channels connected to the data lines one-to-one, and controlling the polarity of the data output to the output channels in a column inversion manner. Data in which one of '-+-++-+-' and '+-+-+-+' is a polarity inversion period is arranged in horizontally adjacent liquid crystal cells in which the gate lines extend in the liquid crystal display panel. Is repeatedly applied, and data having opposite polarities are applied to liquid crystal cells adjacent in the vertical direction in which the data lines extend.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device.

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. The liquid crystal display device can be miniaturized compared to a cathode ray tube (CRT) and is applied to various display devices such as portable information equipment, office equipment, computers, and televisions. The liquid crystal cells of the liquid crystal display display an image by changing the transmittance according to the potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode.

In order to alleviate deterioration of liquid crystals over time, liquid crystal displays adopt an inversion scheme that periodically inverts the polarity of data applied to the liquid crystal cell. Such an inversion method includes a line inversion method of inverting the polarity of data in a vertical dot unit and a horizontal liquid crystal cell line unit as shown in FIG. Inverted horizontal two-dot inversion schemes are known.

When implementing the line inversion method of FIG. 1 or the horizontal two-dot inversion method of FIG. 3, a method for reducing the number of output transitions of the data driver has been devised to reduce power consumption of the data driver. For example, the polarity of the data output from the data driver to the data line is controlled by the column inversion method, and the connection between the liquid crystal cell and the data line is controlled to provide the line inversion method or the horizontal 2-dot inversion of FIG. 3. Power consumption reduction techniques for implementing the scheme are known.

However, if the resolution is improved while periodically inverting the polarity of the data, a short time required for inverting the polarities of pixels is shortened, and a smear phenomenon occurs.

The smear phenomenon refers to a background pattern positioned to the left and right of the window smear pattern when a window smear pattern in which white / black is repeated in units of 2 pixel lines along a vertical direction is displayed within the background pattern of the middle gray scale as shown in FIG. 2. The luminance deviation is represented by a pattern similar to the window square pattern. Therefore, the smear defect is represented by a line dim phenomenon in the vertical direction. The cause of the smear phenomenon is that in the window smear pattern, the dominant polarity is inverted in units of horizontal liquid crystal cell lines, and thus the common voltage of the corresponding line is changed according to the dominant polarity.

Referring to FIG. 3, the principle of generating smear defect will be described in detail. In FIG. 3, the dominant polarity of each of the horizontal liquid crystal cell lines of the window smear pattern is the polarity of the more liquid crystal cells of the positive (+) liquid crystal cell having white gray and the negative (-) liquid crystal cell having white gray. It is decided. In other words, the dominant polarity is defined as the negative polarity (-) in each of the odd horizontal liquid crystal cell lines L # 1, L # 3, L # 5, L # 7, L # n, and each excellent horizontal liquid crystal In the cell lines L # 2, L # 4 and L # 6, positive polarity (+) is determined.

The common voltage Vcom should be maintained at a constant input level between the positive data voltage and the negative data voltage. However, since the common electrode to which the common voltage Vcom is applied and the pixel electrode to which the data voltage is applied are coupled to the liquid crystal capacitor and the storage capacitor, the positive electrode (+) and the negative electrode ( -) Is shifted in either direction.

Background of the common horizontal liquid crystal cell lines (L # 1, L # 3, L # 5, L # 7, L # n) in which the common voltage Vcom is shifted in the negative polarity (-) direction to belong to the corresponding horizontal liquid crystal cell lines This results in a luminance deviation in the pattern. In this background pattern, the positive (+) liquid crystal cells are displayed brighter than the negative (-) liquid crystal cells. The positive (+) liquid crystal cells are displayed with a Y gray level higher than the X gray level to be originally displayed due to the negative shift of the common voltage Vcom.

In the even horizontal liquid crystal cell lines L # 2, L # 4, and L # 6, the common voltage Vcom is shifted in the negative polarity (+) direction to cause a luminance deviation in the background pattern belonging to the horizontal liquid crystal cell line. In this background pattern, the negative (-) liquid crystal cells are displayed brighter than the positive (+) liquid crystal cells. Negative (-) liquid crystal cells are displayed with a Y gray level higher than the X gray level to be originally displayed due to a positive shift of the common voltage Vcom.

This smear phenomenon degrades the display quality.

Accordingly, an object of the present invention is to provide a liquid crystal display device which can suppress a smear phenomenon by preventing a common voltage shift according to a data pattern.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention includes a liquid crystal display panel in which a plurality of gate lines and a plurality of data lines intersect and liquid crystal cells are formed at the intersection thereof; And a data driving circuit including output channels connected to the data lines one-to-one, and controlling the polarity of the data output to the output channels in a column inversion manner. Data in which one of '-+-++-+-' and '+-+-+-+' is a polarity inversion period is arranged in horizontally adjacent liquid crystal cells in which the gate lines extend in the liquid crystal display panel. Is repeatedly applied, and data having opposite polarities are applied to liquid crystal cells adjacent in the vertical direction in which the data lines extend.

The present invention controls the polarity of the data applied to the data lines in a column inversion scheme, and adjusts the horizontal polarity inversion period of the data applied to the liquid crystal cells through the pixel array connection structure to '-+-++-+-'. And '+-+-+-+'. As a result, the present invention can effectively suppress the smear phenomenon without using a separate pattern recognition algorithm by preventing the common voltage shift according to the data pattern.

1 is a view showing a polar pattern of the line inversion method.
2 is a diagram showing a specific data pattern in which a smear phenomenon occurs.
3 is a view for explaining the principle that the smear phenomenon occurs in the horizontal two-dot inversion method.
4 is a view showing a liquid crystal display according to an embodiment of the present invention.
5 illustrates a pixel array of a liquid crystal display panel for suppressing smear phenomenon.
FIG. 6 illustrates a portion of the pixel array of FIG. 5; FIG.
FIG. 7 is a diagram illustrating a principle in which a smear phenomenon is suppressed in the pixel array structure of FIGS. 5 and 6.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 7.

4 shows a liquid crystal display according to an embodiment of the present invention.

Referring to FIG. 4, the liquid crystal display according to the exemplary embodiment includes a liquid crystal display panel 10, a timing controller 11, a data driving circuit 12, and a gate driving circuit 13.

In the liquid crystal display panel 10, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 10 includes liquid crystal cells Clc arranged in a matrix by a cross structure of the data lines 15 and the gate lines 16.

A pixel array is formed on the lower glass substrate of the liquid crystal display panel 10. The pixel array is opposed to the liquid crystal cells Clc formed at the intersection of the data lines 15 and the gate lines 16, TFTs connected to the pixel electrodes 1 of the liquid crystal cells, and the pixel electrode 1. The common electrode 2 and the storage capacitor Cst are included. The pixel array may be implemented as shown in FIG. 5 so that smear phenomenon is suppressed. Each of the liquid crystal cells Clc is connected to a TFT and driven by an electric field between the pixel electrode 1 and the common electrode 2. A black matrix, a color filter, and the like are formed on the upper glass substrate of the liquid crystal display panel 10. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed.

The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate.

The liquid crystal display panel 10 applicable to the present invention may be implemented in any liquid crystal mode as well as a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in plane switching (IPS) mode, a fringe field switching (FFS) mode, and the like. Can be. The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 11 receives digital video data (RGB) of an input image from the system board 14 through a low voltage differential signaling (LVDS) interface, and mini-LVDS the digital video data (RGB) of the input image. The data driving circuit 12 is supplied to the data driving circuit 12 through an interface method. The timing controller 11 aligns the digital video data RGB input from the system board 14 to the configuration of the pixel array as shown in FIG. 7 and supplies the digital video data RGB to the data driving circuit 12.

The timing controller 11 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable (DE), and a dot clock CLK from the system board 14. Control signals for controlling the operation timing of the driving circuit 12 and the gate driving circuit 13 are generated. The control signals include a gate timing control signal for controlling the operation timing of the gate driving circuit 13 and a data timing control signal for controlling the operation timing of the data driving circuit 12. The timing controller 11 has a gate so that the digital video data RGB input at a frame frequency of 60 Hz can be displayed on the pixel array of the liquid crystal display panel 10 at a frame frequency of 60 x i (i is a positive integer) Hz. The frequency of the timing control signal and the data timing control signal can be multiplied by a frame frequency reference of 60 x i Hz.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like. The gate start pulse GSP is applied to the gate drive IC generating the first gate pulse to control the gate drive IC to generate the first gate pulse. The gate shift clock GSC is a clock signal commonly input to gate drive ICs and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), a source output enable signal (SOE), and the like. Include. The source start pulse SSP controls the data sampling start timing of the data driving circuit 12. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the data driving circuit 12 based on the rising or falling edge. The polarity control signal POL controls the polarities of the data voltages sequentially output from each of the source drive ICs. The source output enable signal SOE controls the output timing of the data driver circuit 12.

The data driver circuit 12 includes a shift register, a latch array, a digital-to-analog converter, an output circuit, and the like. The data driving circuit 12 latches the digital video data RGB according to the data timing control signal, and then converts the latched data into an analog positive / negative gamma compensation voltage to convert a plurality of data voltages whose polarities are inverted at predetermined periods. Are supplied to the data lines 15 through the output channels.

Each of the output channels is connected one-to-one to the data lines 15. The data driving circuit 12 controls the polarity of the data voltages output to the output channels in a column inversion manner to reduce power consumption. Based on the column inversion scheme, polarities of data voltages output from the same output channel are inverted in units of frames, and polarities of data voltages output from neighboring output channels are reversed.

The gate driving circuit 13 sequentially supplies gate pulses to the gate lines 16 according to gate timing control signals using a shift register and a level shifter. The shift register of the gate driving circuit 13 may be directly formed on the lower glass substrate according to a gate-driver in panel (GIP) method.

5 illustrates a pixel array of the liquid crystal display panel 10 for suppressing smear phenomenon. 6 illustrates a portion of the pixel array of FIG. 5.

Referring to FIG. 5, the data lines D1 to D17 and the gate lines G1 to G5 intersect each other in the pixel array, and liquid crystal cells are disposed at each crossing area. The polarity of the data applied to the data lines D1 to D17 is controlled by the column inversion method. Polarities of data applied to neighboring data lines are inverted from each other. Each liquid crystal cell is connected to a data line arranged on its left or right side via a TFT. Each liquid crystal cell is turned on according to a gate pulse from the gate line to receive data from the data line. In the eight liquid crystal cells adjacent to each other in the horizontal direction (gate line extension direction), data having one of '-+-++-+-' and '+-+-+-+' as the polarity inversion period is repeatedly The data of opposite polarities are applied to the liquid crystal cells adjacent to each other in the vertical direction (data line extension direction). For example, as shown in FIG. 5, each of the eight liquid crystal cells adjacent in the horizontal direction in each odd horizontal liquid crystal cell line is negative (-), positive (+), negative (-), positive (+), Data with positive (+), negative (-), positive (+), and negative (-) 'inversion cycles are applied, and eight liquid crystal cells adjacent in the horizontal direction in each of the even horizontal liquid crystal cell lines For each of these, the positive (+), negative (-), positive (+), negative (-), negative (-), positive (+), negative (-), positive (+) Data with 'inversion period' is applied.

To this end, the liquid crystal cells adjacent to each other in the vertical direction and even-numbered in the horizontal direction share the odd gate line therebetween, and the liquid crystal cells adjacent in the vertical direction and the odd-numbered arranged in the horizontal direction are the even-numbered between them. Share the gate line.

In addition, the liquid crystal cells disposed adjacent to each other in the vertical direction between the first data line and the second data line to which data of different polarities are applied are alternately connected to the first data line and the second data line. The TFTs connected to the same data line are arranged in a zigzag along the vertical direction to electrically connect the liquid crystal cell and the data lines arranged on the left side (or right side) of the liquid crystal cell.

Referring to FIG. 6, the connection structure of the liquid crystal cells will be described in detail. In order to drive 16 liquid crystal cells P11 to P18 and P21 to P28 arranged on two horizontal liquid crystal cell lines, the present invention is directed to the horizontal direction. Accordingly, nine data lines D1 to D9 sequentially arranged and three gate lines G1, G2 and G3 sequentially arranged along the vertical direction are allocated to two horizontal liquid crystal cell lines. Liquid crystal cells P11 to P18 are sequentially arranged in the horizontal horizontal liquid crystal cell line, and liquid crystal cells P21 to P28 are sequentially disposed in the horizontal direction in the even horizontal liquid crystal cell line.

The liquid crystal cell P11 is connected to the data line D2 disposed on the right side thereof through the TFT T11 and connected to the gate line G2 disposed below it to charge negative data. The liquid crystal cell P12 adjacent to the liquid crystal cell P11 in the horizontal direction is connected to the data line D3 disposed on the right side thereof through the TFT T12 and connected to the gate line G1 disposed thereon to charge positive data. . The liquid crystal cell P13 adjacent to the liquid crystal cell P12 in the horizontal direction is connected to the data line D4 disposed on the right side thereof through the TFT T13 and connected to the gate line G2 disposed below it to charge negative data (-). do. The liquid crystal cell P14 adjacent to the liquid crystal cell P13 in the horizontal direction is connected to the data line D5 disposed on the right side thereof through the TFT T14 and connected to the gate line G1 disposed thereon to charge positive data. .

The liquid crystal cell P15 horizontally adjacent to the liquid crystal cell P14 is connected to the data line D5 disposed on the left side of the liquid crystal cell P14 through the TFT T15 and is connected to the gate line G2 disposed below it to charge positive data. . The liquid crystal cell P16 adjacent to the liquid crystal cell P15 in the horizontal direction is connected to the data line D6 disposed on the left side of the liquid crystal cell P15 and connected to the gate line G1 disposed thereon to charge negative data. . The liquid crystal cell P17 adjacent to the liquid crystal cell P16 in the horizontal direction is connected to the data line D7 disposed on the left side of the liquid crystal cell P16 through the TFT T17 and connected to the gate line G2 disposed below it to charge positive polarity data. do. The liquid crystal cell P18 adjacent to the liquid crystal cell P17 in the horizontal direction is connected to the data line D8 disposed on the left side of the liquid crystal cell P17 and connected to the gate line G1 disposed thereon to charge negative data. .

The liquid crystal cell P21 adjacent to the liquid crystal cell P11 perpendicular to the liquid crystal cell P11 is connected to the data line D1 disposed on the left side of the liquid crystal cell P11 and connected to the gate line G2 disposed on the upper side thereof to charge positive data. The liquid crystal cell P22 adjacent to the liquid crystal cell P21 in the horizontal direction and vertically adjacent to the liquid crystal cell P12 is connected to the data line D2 disposed on the left side thereof through the TFT T22 and connected to the gate line G3 disposed below the negative electrode. Charge data of polarity (-). The liquid crystal cell P23 adjacent to the liquid crystal cell P22 in the horizontal direction and vertically adjacent to the liquid crystal cell P13 is connected to the data line D3 disposed on the left side of the liquid crystal cell through the TFT T23 and connected to the gate line G2 disposed thereon to be positive. Charge the data of (+). The liquid crystal cell P24 adjacent to the liquid crystal cell P23 in the horizontal direction and vertically adjacent to the liquid crystal cell P14 is connected to the data line D4 disposed on the left side thereof through the TFT T24 and connected to the gate line G3 disposed below it. Charge data of polarity (-).

The liquid crystal cell P25 horizontally adjacent to the liquid crystal cell P24 and vertically adjacent to the liquid crystal cell P15 is connected to the data line D6 disposed on the right side thereof through the TFT T25 and is connected to the gate line G2 disposed thereon and is connected to the positive polarity ( Charge the data of +). The liquid crystal cell P26 adjacent to the liquid crystal cell P25 in the horizontal direction and vertically adjacent to the liquid crystal cell P16 is connected to the data line D7 disposed on the right side thereof through the TFT T26 and connected to the gate line G3 disposed below it. Charge data of polarity (+). The liquid crystal cell P27 adjacent to the liquid crystal cell P26 in the horizontal direction and vertically adjacent to the liquid crystal cell P17 is connected to the data line D8 disposed on the right side thereof through the TFT T27 and connected to the gate line G2 disposed thereon to form a negative polarity. Charge negative data. The liquid crystal cell P28 adjacent to the liquid crystal cell P27 in the horizontal direction and vertically adjacent to the liquid crystal cell P18 is connected to the data line D9 disposed on the right side thereof through the TFT T28 and connected to the gate line G3 disposed below it. Charge data of polarity (+).

FIG. 7 illustrates a principle in which a smear phenomenon is suppressed in the pixel array structure of FIGS. 5 and 6.

The present invention controls the polarity of the data applied to the data lines in a column inversion scheme, while adjusting the horizontal polarity inversion period of the data applied to the liquid crystal cells through the pixel array connection structure as described above. It is possible to control with either-+-'or' +-+-+-+ '. As shown in FIG. 7, when data is supplied to the pixel array such that the low gray and the white gray are alternately arranged in units of three liquid crystal cells (ie, one pixel) adjacent to each other in the horizontal direction, the pixels are aligned through all pixels of each horizontal line of the pixel array. The polarity (+) and the negative (-) cancel each other on average so that no dominant polarity appears in each horizontal line.

In the Nth horizontal line between the gate lines G1 and G2 and the N + 1th horizontal line between the gate lines G2 and G3, pixels having low gray levels and pixels having white gray levels are mixed with each other to form a check board. The gradation pattern of the N + 2th horizontal line positioned between the gate lines G3 and G4 is a shift of the gradation pattern of the Nth horizontal line by one liquid crystal cell to the right, and the N + 3 horizontal line positioned between the gate lines G4 and G5. The gradation pattern of is a shift of the gradation pattern of the N + 1th horizontal line by one liquid crystal cell to the right. In the N + 2th horizontal line and the N + 3th horizontal line, pixels having low gray levels and pixels having white gray levels are mixed with each other to form a check board. The grayscale pattern of the N + 4th horizontal line positioned between the gate lines G5 and G6 is a shift of the grayscale pattern of the Nth horizontal line by 2 liquid crystal cells to the right, and the N + 5th horizontal line located between the gate lines G6 and G7. The gradation pattern of is a shift of the gradation pattern of the N + 1th horizontal line by 2 liquid crystal cells to the right. In the N + 4th horizontal line and the N + 5th horizontal line, pixels having a low gray level and pixels having a white gray level are mixed with each other to form a check board.

FIG. 7 shows a polarization bias distribution of pixels for each horizontal line sharing each gate line. The pixels arranged in the pixel lines X1 to X8 while sharing the respective gate lines G2 to G7 have eight polarity distributions. Since the eight pixel data polarities cancel each other, the dominant polarity does not appear between two horizontal lines adjacent to each other with the gate line interposed therebetween. Therefore, the common voltage Vcom is not shifted by the dominant polarity, and the common voltage Vcom is maintained at the original input level.

As described above, the present invention controls the polarity of the data applied to the data lines in a column inversion scheme, and adjusts the horizontal polarity inversion period of the data applied to the liquid crystal cells through the pixel array connection structure. Control with either-+-'or' +-+-+-+ '. As a result, the present invention can effectively suppress the smear phenomenon without using a separate pattern recognition algorithm by preventing the common voltage shift according to the data pattern.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the present invention should not be limited to the details described in the detailed description but should be defined by the claims.

10 liquid crystal display panel 11 timing controller
12: data driving circuit 13: gate driving circuit

Claims (6)

A liquid crystal display panel in which a plurality of gate lines and a plurality of data lines intersect and liquid crystal cells are formed at an intersection thereof; And
A data driving circuit including output channels connected to the data lines one-to-one and controlling a polarity of data output to the output channels in a column inversion manner;
Data in which one of '-+-++-+-' and '+-+-+-+' is a polarity inversion period is arranged in horizontally adjacent liquid crystal cells in which the gate lines extend in the liquid crystal display panel. Is repeatedly applied, and data having opposite polarities are applied to the liquid crystal cells adjacent in the vertical direction in which the data lines extend.
And liquid crystal cells adjacent to each other in the vertical direction and even or odd-numbered in the horizontal direction are electrically connected to one of the gate lines. The method of claim 1,
In the liquid crystal display panel, liquid crystal cells adjacent to each other in the vertical direction and even-numbered in the horizontal direction share an odd gate line therebetween, and liquid crystal cells adjacent in the vertical direction and arranged in the horizontal direction in the horizontal direction. And the cells share the even-numbered gate line therebetween. The method of claim 1,
Liquid crystal cells disposed adjacent to each other in the vertical direction between the first data line and the second data line to which data of different polarities are applied are alternately connected to the first data line and the second data line;
TFTs connected to the same data line are arranged in a zigzag direction along the vertical direction to electrically connect the liquid crystal cell and the data lines arranged on the left or right side of the liquid crystal cell. The method of claim 1,
The liquid crystal display panel has two horizontal liquid crystal cell lines formed by nine data lines D1 through D9 sequentially arranged along the horizontal direction, and three gate lines G1 through G3 sequentially arranged along the vertical direction. Sixteen liquid crystal cells arranged at are driven;
Among the 16 liquid crystal cells, liquid crystal cell P11, liquid crystal cell P12, liquid crystal cell P13, liquid crystal cell P14, liquid crystal cell P15, liquid crystal cell P16, liquid crystal cell P17 and liquid crystal cell P18 are the first of the two horizontal liquid crystal cell lines. Arranged in a horizontal liquid crystal cell line;
Among the 16 liquid crystal cells, liquid crystal cell P21, liquid crystal cell P22, liquid crystal cell P23, liquid crystal cell P24, liquid crystal cell P25, liquid crystal cell P26, liquid crystal cell P27 and liquid crystal cell P28 are adjacent to the first horizontal liquid crystal cell line. Liquid crystal display, characterized in that disposed on. The method of claim 4, wherein
The liquid crystal cell P11 is connected to the data line D2 disposed on the right side of the liquid crystal cell P11 through a TFT T11 and connected to the gate line G2 disposed below the liquid crystal cell P11 to charge negative data. and; The liquid crystal cell P12 adjacent to the liquid crystal cell P11 in the horizontal direction is connected to a data line D3 disposed on the right side of the liquid crystal cell P12 through a TFT T12 and connected to a gate line G1 disposed on the liquid crystal cell P12. Charge positive data; The liquid crystal cell P13 adjacent to the liquid crystal cell P12 in the horizontal direction is connected to the data line D4 disposed on the right side of the liquid crystal cell P13 through a TFT T13 and connected to the gate line G2 disposed below the liquid crystal cell P13. Connected to charge negative data; The liquid crystal cell P14 adjacent to the liquid crystal cell P13 in the horizontal direction is connected to the data line D5 disposed on the right side of the liquid crystal cell P14 through a TFT T14 and to the gate line G1 disposed on the liquid crystal cell P14. To charge positive data;
The liquid crystal cell P15 horizontally adjacent to the liquid crystal cell P14 is connected to the data line D5 disposed on the left side of the liquid crystal cell P15 through a TFT T15 and connected to the gate line G2 disposed below the liquid crystal cell P15. Connected to charge positive data; The liquid crystal cell P16 adjacent to the liquid crystal cell P15 in the horizontal direction is connected to the data line D6 disposed on the left side of the liquid crystal cell P16 through a TFT T16 and to the gate line G1 disposed on the liquid crystal cell P16. To charge negative data; The liquid crystal cell P17 adjacent to the liquid crystal cell P16 in the horizontal direction is connected to the data line D7 disposed on the left side of the liquid crystal cell P17 through a TFT T17 and connected to the gate line G2 disposed below the liquid crystal cell P17. Connected to charge positive data; The liquid crystal cell P18 adjacent to the liquid crystal cell P17 in the horizontal direction is connected to the data line D8 disposed on the left side of the liquid crystal cell P18 through a TFT T18 and to the gate line G1 disposed on the liquid crystal cell P18. And charge data of negative polarity (-). The method of claim 5,
The liquid crystal cell P21 adjacent to the liquid crystal cell P11 is connected to the data line D1 disposed on the left side of the liquid crystal cell P21 through a TFT T21 and to the gate line G2 disposed on the liquid crystal cell P21. To charge positive data; The liquid crystal cell P22 neighboring the liquid crystal cell P21 in a horizontal direction and vertically adjacent to the liquid crystal cell P12 is connected to the data line D2 disposed on the left side of the liquid crystal cell P22 through a TFT T22 and the liquid crystal cell P22. Is connected to gate line G3 disposed below to charge negative data; The liquid crystal cell P23 neighboring the liquid crystal cell P22 in the horizontal direction and vertically adjacent to the liquid crystal cell P13 is connected to the data line D3 disposed on the left side of the liquid crystal cell P23 through a TFT T23 and the liquid crystal cell P23. Connected to the gate line G2 disposed above to charge positive data; The liquid crystal cell P24 adjacent to the liquid crystal cell P23 in the horizontal direction and vertically adjacent to the liquid crystal cell P14 is connected to the data line D4 disposed on the left side of the liquid crystal cell P24 through a TFT T24 and the liquid crystal cell P24. Is connected to the gate line G3 disposed below to charge negative data;
The liquid crystal cell P25 horizontally adjacent to the liquid crystal cell P24 and vertically adjacent to the liquid crystal cell P15 is connected to the data line D6 disposed on the right side of the liquid crystal cell P25 through a TFT T25 and is connected to the liquid crystal cell P25. Is connected to the gate line G2 disposed above to charge positive data; The liquid crystal cell P26 neighboring the liquid crystal cell P25 in a horizontal direction and vertically adjacent to the liquid crystal cell P16 is connected to the data line D7 disposed on the right side of the liquid crystal cell P26 through a TFT T26 and the liquid crystal cell P26. Is connected to the gate line G3 disposed below to charge positive data; The liquid crystal cell P27 adjacent to the liquid crystal cell P26 in a horizontal direction and vertically adjacent to the liquid crystal cell P17 is connected to the data line D8 disposed on the right side of the liquid crystal cell P27 through a TFT T27 and the liquid crystal cell P27. Connected to the gate line G2 disposed above to charge negative data; The liquid crystal cell P28 adjacent to the liquid crystal cell P27 in the horizontal direction and vertically adjacent to the liquid crystal cell P18 is connected to the data line D9 disposed on the right side of the liquid crystal cell P28 through the TFT T28 and is connected to the liquid crystal cell P28. And a positive polarity (+) data connected to the gate line G3 disposed below.

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