KR101470624B1 - Liquid Crystal Display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device capable of increasing display quality and reducing power consumption of a data driving circuit.

This liquid crystal display device comprises: a plurality of liquid crystal cells driven by a data voltage and a common voltage of opposite polarities; A first common electrode connection pattern connecting common electrodes of first liquid crystal cells supplied with a common voltage having a first polarity among the liquid crystal cells; And a second common electrode connection pattern for connecting the common electrodes of the second liquid crystal cells supplied with the common voltage of the second polarity opposite to the first polarity among the liquid crystal cells to each other; Common electrodes of the first liquid crystal cells are connected to the first common electrode connection pattern through first contact holes and common electrodes of the second liquid crystal cells are connected to the second common electrode connection pattern through second contact holes do.

Description

[0001] Liquid crystal display [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of increasing display quality and reducing power consumption of a data driving circuit.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. Such a liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix form and a drive circuit for driving the liquid crystal display panel.

The liquid crystal display panel is provided with a thin film transistor for driving the liquid crystal cell Clc at the intersection of the gate line GL and the data line DL and the intersection of the gate line GL and the data line DL, A TFT (Thin Film Transistor) is formed. The thin film transistor TFT supplies the data voltage Vd supplied through the data line to the pixel electrode Ep of the liquid crystal cell Clc in response to the scan pulse supplied through the gate line GL. To this end, the gate electrode of the thin film transistor TFT is connected to the gate line GL, the source electrode thereof is connected to the data line DL, and the drain electrode thereof is connected to the pixel electrode of the liquid crystal cell Clc. The liquid crystal cell Clc is charged with the potential difference between the data voltage Vd supplied to the pixel electrode Ep and the common voltage Vcom supplied to the common electrode Ec, As the array changes, the amount of light transmitted is controlled or the light is blocked. The common electrode Ec is formed on the upper substrate or the lower substrate of the liquid crystal display panel according to a method of applying an electric field to the liquid crystal cell Clc and is connected to the storage line to which the common voltage Vcom is supplied, A storage capacitor Cst is formed between the electrodes Ep for maintaining the charged voltage of the liquid crystal cell Clc.

Such a liquid crystal display panel is driven by an inversion method in which the polarity of the liquid crystal cell Clc is inverted by a predetermined unit in order to prevent the deterioration of the liquid crystal cell Clc and improve the display quality. The inversion method includes a line inversion method of inverting the polarity of data between adjacent liquid crystal cells in the vertical line direction, a version method of inverting the polarity of data between adjacent liquid crystal cells in the horizontal line direction, a vertical line direction and a horizontal line direction There is a dot inversion method in which the polarity of data between adjacent liquid crystal cells is reversed.

The method of driving a liquid crystal display panel using the dot inversion method is different from that of the first embodiment in that the polarity of the data voltages supplied to the liquid crystal cells adjacent to each other in the vertical direction is opposite to the polarity of the data voltages supplied to the adjacent liquid crystal cells in the vertical direction, Lt; / RTI > Then, the polarity of the data voltage is inverted every frame (Fn-1, Fn). The method of driving a liquid crystal display panel using the dot inversion method is most widely applied in liquid crystal display devices since flicker is minimized in both vertical and horizontal directions. The dot inversion method includes a one dot inversion method and a two dot inversion method.

3, the common voltage Vcom is maintained at a half of the high-level power supply voltage VDD and the positive polarity (+) liquid crystal cells are driven in the region where the potential is higher than the common voltage Vcom And the data voltage of the corresponding gray level is applied to the negative polarity (-) liquid crystal cells in a region where the potential is lower than the common voltage Vcom. In order to represent a large number of gradations by varying only the potential level of the data voltage while maintaining the potential level of the common voltage Vcom constant, the range of the required data voltage must be wide. As the range of the data voltage output from the data driving circuit increases, the power consumed in the data driving circuit increases.

The method of driving the liquid crystal display panel using the proposed line inversion method for reducing the power consumption of the data driving circuit is a method for driving the polarity of the data voltage supplied to the liquid crystal cells to each horizontal line and each frame Fn- Fn. The liquid crystal display panel driving method using the line inversion method adopts a method of swinging the common voltage Vcom to two voltage levels. In other words, this driving method uses first and second common voltages (Vcom1, Vcom2) having different voltage levels to generate a first common voltage (Vcom1, Vcom2) having a relatively low potential in the positive polarity (+ (Vcom1) and a data voltage having a higher potential than that of the first common voltage (Vcom1) are applied together to express the gray level, while the second common voltage (Vcom2) having a relatively higher potential is applied to the negative And a data voltage having a potential lower than that of the second common voltage Vcom2 are applied together to express gradation. The polarities of the liquid crystal cells are controlled by inverting the voltage levels of the first and second common voltages Vcom1 and Vcom2 in the frame period. When the potential of the first common voltage Vcom1 is lowered and the potential of the second common voltage Vcom2 is made higher than the common voltage used in the dot-inversion method, the range of the data voltage output from the data driving circuit becomes larger .

However, in the method of driving a liquid crystal display panel using the line inversion method, since the common voltage is different for each odd and even horizontal line, the inversion method in which the polarity changes in units of liquid crystal cell (s), for example, Can not be applied as it is. In addition, when driving a liquid crystal display panel using such a line inversion method, a flicker such as a stripe pattern is generated due to cross talk between horizontal lines, resulting in a problem that the display quality is lower than the dot inversion method.

Accordingly, it is an object of the present invention to provide a liquid crystal display device capable of increasing display quality and reducing power consumption of a data driving circuit.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a plurality of liquid crystal cells driven by a data voltage and a common voltage having opposite polarities; A first common electrode connection pattern connecting common electrodes of first liquid crystal cells supplied with a common voltage having a first polarity among the liquid crystal cells; And a second common electrode connection pattern for connecting the common electrodes of the second liquid crystal cells supplied with the common voltage of the second polarity opposite to the first polarity among the liquid crystal cells to each other; Common electrodes of the first liquid crystal cells are connected to the first common electrode connection pattern through first contact holes and common electrodes of the second liquid crystal cells are connected to the second common electrode connection pattern through second contact holes do.
Wherein the first common electrode connection pattern is partially overlapped with the common electrodes of the first liquid crystal cells with at least one insulating film interposed therebetween, The first and second common electrode connection patterns are simultaneously patterned with the pixel electrodes of the first and second liquid crystal cells to which the data voltage is supplied.
The polarity of the data voltage is inverted in units of one liquid crystal cell adjacent in the horizontal and vertical directions.
The polarity of the data voltage is inverted in units of two adjacent liquid crystal cells in the horizontal direction and inverted in units of adjacent liquid crystal cells in the vertical direction.
The first common electrode connection pattern and the second common electrode connection pattern are electrically insulated from each other to electrically connect liquid crystal cells supplied with data voltages having the same polarity.
Common electrodes of the first and second liquid crystal cells are formed on the same substrate together with the pixel electrodes of the first and second liquid crystal cells.
A first common voltage supply line formed to supply a common voltage of the first polarity to the first common electrode connection pattern and to surround a part of the liquid crystal cells; And
And a second common voltage supply line formed to supply a common voltage of the second polarity to the second common electrode connection pattern and formed in a ""'' shape so as to surround the rest except for a part of the liquid crystal cells.
The common electrodes of the first common voltage supply line, the second common voltage supply line, and the first and second liquid crystal cells are formed through the same metal patterning process, and the first common electrode connection pattern, The connection pattern, and the pixel electrodes of the first and second liquid crystal cells are formed through the same transparent conductive film patterning process.

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INDUSTRIAL APPLICABILITY The present invention can greatly improve the display quality and significantly reduce the power consumption of the data driving circuit.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 6 to 15. FIG.

6 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

6, a liquid crystal display according to an embodiment of the present invention includes a plurality of gate lines GL1 to GLn (n is a positive integer) and a plurality of data lines DL1 to DLm (m is a positive integer) Are formed at intersections of the liquid crystal cells Clc and the gate lines GL1 to GLn and the data lines DL1 to DLm formed in the pixel regions defined by the intersections to drive the respective liquid crystal cells A data driving circuit 120 for supplying a video signal to the data lines DL1 to DLm and a data driver 120 for applying a scan pulse to the gate lines GL1 to GLn, A timing controller 110 for controlling the data driving circuit 120 and the gate driving circuit 130 and two common voltages Vcom and -Vcom having different polarities, And a common voltage control unit 150 that alternately generates the common voltage.

The liquid crystal display panel 140 has a structure in which an upper substrate and a lower substrate are bonded together. On the lower substrate of the liquid crystal display panel 140, the gate lines GL1 to GLn and the data lines DL1 to DLm cross each other. The thin film transistors TFT formed at the intersections of the gate lines GL1 to GLn and the data lines DL1 to DLm are connected to the data lines DL1 to DLn in response to the scan pulses from the gate lines GL1 to GLn, DLm to the pixel electrode Ep of the liquid crystal cell Clc. The liquid crystal cell Clc is charged with the potential difference between the data voltage supplied to the pixel electrode Ep and the common voltage Vcom supplied to the common electrode Ec, and the arrangement of the liquid crystal molecules is changed by the electric field formed by this potential difference The light amount of the transmitted light is adjusted. The common electrode Ec may be formed on the upper substrate or the lower substrate according to a method of applying an electric field to the liquid crystal cell Clc. However, in the embodiment of the present invention, the common electrode Ec is preferably formed on the lower substrate together with the pixel electrode Ep . The common electrodes Ec of the liquid crystal cells Clc are electrically connected to each other by the common electrode connection patterns according to the polarity of the data voltage supplied to the pixel electrodes Ep. In other words, the common electrodes (Ec) opposed to the pixel electrodes (Ep) to which the positive polarity data voltage is supplied are connected to each other by the first common electrode connection pattern, and the pixel electrodes And the common electrodes Ec opposing each other are connected to each other by the second common electrode connection pattern. The first and second common electrode connection patterns are connected to the first and second common voltage supply lines, respectively. This will be described later in detail with reference to FIG. 10 to FIG. A storage capacitor Cst for holding the charging voltage of the liquid crystal cell Clc is formed between the pixel electrode Ep of the liquid crystal cell Clc and the front gate line. A color filter for realizing colors and a black matrix for reducing light interference between adjacent pixels are formed on the upper substrate of the liquid crystal display panel 140. Further, polarizers each having an optical axis orthogonal to each other are attached to the upper substrate and the lower substrate, and an alignment film for setting the pretilt angle of the liquid crystal is formed on the inner surfaces of the substrates.

The timing controller 110 receives digital video data RGB, vertical / horizontal synchronizing signals Hsync and Vsync and a dot clock signal CLK from a system interface circuit (not shown) and controls the data driving circuit 120 And a gate control signal GDC for controlling the gate driving circuit 130. The digital video data RGB are rearranged in accordance with the dot clock signal CLK, 120. Here, the data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output signal SOE, a polarity control signal POL, A pulse GSP, a gate shift clock GSC, a gate output signal GOE, and the like.

The data driving circuit 120 converts the digital video data RGB supplied from the timing controller 110 into an analog gamma compensation voltage, that is, a data voltage in accordance with the data control signal DDC. To this end, the data driving circuit 120 includes a plurality of integrated circuits (ICs), each of which includes a shift register 122, which is connected between the input line and the data line, as shown in FIG. 7, A second latch array 124, a gamma compensation voltage generator 125, a digital-to-analog converter (DAC) 126, a charge share circuit 127, And an output circuit 128.

The shift register 122 shifts the source start pulse SSP from the timing controller 110 according to the source shift clock SSC to generate a sampling signal. The shift register 122 shifts the source start pulse SSP and transfers the carry signal CAR to the shift register 122 at the next stage.

The first latch array 123 samples the digital video data DHLo and DHLe from the timing controller 110 in response to a sampling signal sequentially input from the shift register 122 and outputs the data DHLo and DHLe ) For one horizontal line, and then outputs data for one horizontal line at the same time.

The second latch array 124 latches one horizontal line of data input from the first latch array 123 and then forwards the second latch array 124 of the other data ICs 124 during the low logic period of the source output signal SOE And simultaneously outputs the latched digital video data DHLo and DHLe.

The gamma compensation voltage generator 125 further divides the plurality of gamma reference voltages supplied from the gamma reference voltage generator (not shown) by the number of gradations that can be represented by the number of bits of the digital video data DHLo and DHLe, And generates the positive gamma compensation voltages VGH and negative gamma compensation voltages VGL corresponding to the gradation.

The DAC 126 includes a P-decoder (PDEC) 1261 to which a positive gamma compensation voltage VGH is supplied, an N-decoder (NDEC) 1262 to which a negative gamma compensation voltage VGL is supplied, And a multiplexer 1263 for selecting the output of the P-decoder 1261 and the output of the N-decoder 1262 in response to the polarity control signals POL. The P-decoder 1261 decodes the digital video data DHLo and DHLe input from the second latch array 124 and outputs a positive gamma compensation voltage VGH corresponding to the gray level of the data, -Decoder 1262 decodes the digital video data DHLo and DHLe input from the second latch array 124 and outputs a negative gamma compensation voltage VGL corresponding to the gray level value of the data. The multiplexer 1263 selects the positive gamma compensation voltage VGH and the negative gamma compensation voltage VGL in response to the polarity control signal POL. Here, the polarity of the polarity control signal POL is reversed with a period of one horizontal period, and the polarity is reversed with a period of one frame period. The multiplexers 1263 are alternately connected to the inverter INV to receive the polarity control signal POL of the opposite phase. Therefore, the polarity of the output gamma compensation voltage is inverted in units of adjacent liquid crystal cells in the horizontal and vertical directions.

When the multiplexers 1263 are alternately connected to the inverter INV as shown in FIG. 9, the polarity of the output gamma compensation voltage is inverted in units of two adjacent liquid crystal cells in the horizontal direction, Direction is reversed in units of one adjacent liquid crystal cell.

The charge sharing circuit 127 short-circuits the neighboring data output channels during the high logic period of the source output signal SOE to output the average value of the neighboring data voltages to the charge share voltage, The common voltage Vcom is supplied to the data output channels during the high logic period to reduce a sharp change in the positive polarity data voltage and the negative polarity data voltage.

The output circuit 128 includes a buffer to minimize signal attenuation of the data voltage supplied to the data lines DL1 to DLk.

The gate driving circuit 130 sequentially supplies a scan pulse for selecting a horizontal line of the liquid crystal display panel 140 to which a data voltage is to be supplied to the gate lines GL1 to GLn. The gate driving circuit 130 includes a shift register for sequentially shifting a gate start pulse GSP from the timing controller 110 to generate a shift output signal and a shift register for outputting a shift output signal from the shift register to a voltage Level scan pulses and supplies the scan pulses to the gate lines GL1 to GLn and an output buffer disposed between the level shifters and the gate lines GL1 to GLn to stabilize the scan pulse, .

The common voltage control unit 150 generates two common voltages having different polarities, that is, a positive common voltage + Vcom and a negative common voltage -Vcom, and then supplies them to the liquid crystal display panel 140 And alternately supplies the first and second common voltage supply lines electrically separated.

10 to 12 show a connection structure of a liquid crystal display panel for applying a common voltage swing to the dot inversion driving method according to the first embodiment of the present invention.

Referring to FIG. 10, the polarity of the liquid crystal cells is determined according to the polarity of the data voltage supplied to the pixel electrode of the liquid crystal cell. The liquid crystal cells to which the positive polarity data voltage is supplied have positive polarity and the liquid crystal cells to which the negative polarity data voltage is supplied have negative polarity. The polarities of the data voltages supplied from the data driving circuit are inverted in units of adjacent liquid crystal cells in the horizontal and vertical directions, so that the liquid crystal cells are driven by the dot inversion driving method.

The common electrodes of the liquid crystal cells are electrically connected to each other through the common electrode connection patterns according to the polarities of the liquid crystal cells. In other words, the common electrodes of the liquid crystal cells having the first polarity are mutually connected by the first common electrode connection pattern 230a, the common electrodes of the liquid crystal cells having the second polarity are connected to each other by the second common electrode And are interconnected by a connection pattern 230b. Here, the first polarity means a positive polarity in the nth frame Fn and the negative polarity in the n + 1th frame Fn = 1. The second polarity means the positive polarity in the nth frame Fn and the negative polarity in the n + 1th frame Fn = 1.

The first common electrode connection pattern 230a is electrically connected to the first common voltage supply line 240a. The first common voltage supply line 240a may be formed on the outside of the liquid crystal cells in a "" -shaped shape so as to surround a part of the liquid crystal cells. The first common voltage supply line 240a supplies the negative common voltage -Vcom from the common voltage control unit to the first common electrode connection pattern 230a in the nth frame Fn, (+ Vcom) from the common voltage control unit to the first common electrode connection pattern 230a at the first common electrode connection pattern (Fn = 1).

 And the second common electrode connection pattern 230b is electrically connected to the second common voltage supply line 240b. The second common voltage supply line 240b may be formed on the outside of the liquid crystal cells in a "" ' ' shape to be electrically insulated from the first common voltage supply line 240a to surround a part of the liquid crystal cells. The second common voltage supply line 240b supplies the positive common voltage + Vcom from the common voltage control unit to the second common electrode connection pattern 230b in the nth frame Fn, (-Vcom) from the common voltage control unit to the second common electrode connection pattern 230b at the first common electrode connection pattern (Fn = 1).

The first and second common electrode connection patterns 230a and 230b use a patterned transparent conductive film to electrically connect the common electrodes of the liquid crystal cells having the same polarity.

Referring to FIG. 11, an array structure of the thin film transistor substrate including the first and second common electrode connection patterns 230a and 230b will be described.

The thin film transistor TFT causes the data voltage from the data line 204 to be charged and held in the pixel electrode 214 in response to the scan pulse of the gate line 202. The thin film transistor TFT includes a gate electrode 208 formed to overlap with the gate line 202, a source electrode 210 connected to the data line 204, a drain electrode connected to the pixel electrode 214 An active layer (not shown), a source electrode 210, and a source electrode 210 which form a channel between the source electrode 210 and the drain electrode 212 while overlapping the gate electrode 208 with a gate insulating film (not shown) And an ohmic contact layer (not shown) for ohmic contact between the drain electrode 212 and the active layer.

The pixel electrode 214 is connected to the drain electrode 212 of the thin film transistor TFT through the first contact hole 213 passing through the protective film and is formed in the pixel region. The pixel electrode 214 includes a horizontal portion 214A connected to the drain electrode 212 and aligned with the adjacent gate line 202 and a finger electrode 214B patterned to extend from the horizontal portion 214A .

The common electrode 218 is electrically connected to the common electrode connection pattern 230 and is formed in the pixel region. The common electrode 218 is formed to overlap with the horizontal portion 214A of the pixel electrode 214 in the pixel region and is formed in parallel with the finger electrode 214B of the pixel electrode 214, As shown in FIG.

The common electrode connection pattern 230 is formed so as to overlap with a portion of the common electrode 218 which is not overlapped with the horizontal portion 214A of the pixel electrode 214 and to define the pixel region. The common electrode connection pattern 230 is connected to the common electrode 218 through the second contact hole 221 passing through the protective film and the gate insulating film. This common electrode connection pattern 230 electrically connects the common electrodes 230 of the liquid crystal cells P (1,1) and P (2,2) having the same polarity as the illustrated "B1" .

A gate line 202, a gate electrode 208, a common voltage supply line (not shown), a common electrode 218, and a gate electrode 212 are sequentially formed on a lower substrate. A gate metal pattern is formed. As the gate metal layer, a metal such as Al, Mo, or Cr is used as a single layer or a double layer structure.

A gate insulating film is coated on the lower substrate on which the gate metal pattern is formed. A semiconductor pattern including an active layer and an ohmic contact layer on a gate insulating film; A source / drain metal pattern including a data line 204, a source electrode 210, and a drain electrode 212 is formed. An inorganic insulating material such as SiOx or SiNx is used as a material of the gate insulating film. As the source / drain metal layer, a metal such as Al, Mo, Cr, or the like is used as a single layer or a double layer structure.

A protective film (not shown) including first and second contact holes 213 and 221 is formed on a gate insulating film having a source / drain metal pattern formed thereon. As the material of the protective film, an inorganic insulating material such as a gate insulating film, an acryl based organic compound having a small dielectric constant, or an organic insulating material such as BCB or PFCB is used.

A transparent conductive film pattern including the pixel electrode 214 and the common electrode connection pattern 230 is formed on the protective film. The pixel electrode 214 is connected to the drain electrode 212 exposed through the first contact hole 213 and the common electrode connection pattern 230 is connected to the drain electrode 212 exposed through the second contact hole 221 And is connected to the electrode 218. Here, ITO (Indium Tin Oxide) or the like is used as a material of the transparent conductive film.

13 and 14 show a connection structure of a liquid crystal display panel for applying a common voltage swing to a version driving method of horizontal 2 dots according to a second embodiment of the present invention.

Referring to FIG. 13, the polarity of the liquid crystal cells is determined according to the polarity of the data voltage supplied to the pixel electrode of the liquid crystal cell. The liquid crystal cells to which the positive polarity data voltage is supplied have positive polarity and the liquid crystal cells to which the negative polarity data voltage is supplied have negative polarity. The polarities of the data voltages supplied from the data driving circuit are inverted in units of two adjacent liquid crystal cells in the horizontal direction and inverted in units of adjacent liquid crystal cells in the vertical direction, It is driven by the dot inversion driving method.

The common electrodes of the liquid crystal cells are electrically connected to each other through the common electrode connection patterns according to the polarities of the liquid crystal cells. In other words, the common electrodes of the liquid crystal cells having the first polarity are mutually connected by the first common electrode connection pattern 330a, and the common electrodes of the liquid crystal cells having the second polarity are connected to each other by the second common electrode And are interconnected by a connection pattern 330b. Here, the first polarity means a positive polarity in the nth frame Fn and the negative polarity in the n + 1th frame Fn = 1. The second polarity means the positive polarity in the nth frame Fn and the negative polarity in the n + 1th frame Fn = 1.

The first common electrode connection pattern 330a is electrically connected to the first common voltage supply line 340a. The first common voltage supply line 340a may be formed outside the liquid crystal cells in a "" -shaped shape so as to surround a part of the liquid crystal cells. The first common voltage supply line 340a supplies the negative common voltage -Vcom from the common voltage control unit to the first common electrode connection pattern 330a in the nth frame Fn, (+ Vcom) from the common voltage control unit to the first common electrode connection pattern 330a at a constant voltage (Fn = 1).

 And the second common electrode connection pattern 330b is electrically connected to the second common voltage supply line 340b. The second common voltage supply line 340b may be formed outside the liquid crystal cells in a "" " " shape so as to be electrically insulated from the first common voltage supply line 340a to surround a part of the liquid crystal cells. The second common voltage supply line 340b supplies the positive common voltage + Vcom from the common voltage control unit to the second common electrode connection pattern 330b in the nth frame Fn, (-Vcom) from the common voltage control unit to the second common electrode connection pattern 330b at a time (Fn = 1).

The first and second common electrode connection patterns 330a and 330b use a patterned transparent conductive film to electrically connect the common electrodes of the liquid crystal cells having the same polarity.

Referring to FIG. 14, an array structure of the thin film transistor substrate including the first and second common electrode connection patterns 330a and 330b will be described.

The thin film transistor TFT causes the data voltage from the data line 304 to be charged and held in the pixel electrode 314 in response to the scan pulse of the gate line 302. The thin film transistor TFT includes a gate electrode 308 formed to overlap with the gate line 302, a source electrode 310 connected to the data line 304, a drain electrode connected to the pixel electrode 314 An active layer (not shown), a source electrode 310, and a source electrode 310 which form a channel between the source electrode 310 and the drain electrode 312 while overlapping the gate electrode 308 with a gate insulating film (not shown) And an ohmic contact layer (not shown) for ohmic contact between the drain electrode 312 and the active layer.

The pixel electrode 314 is formed in the pixel region by being connected to the drain electrode 312 of the thin film transistor (TFT) through the first contact hole 313 passing through the protective film. The pixel electrode 314 includes a horizontal portion 314A connected to the drain electrode 312 and aligned with the adjacent gate line 302 and a finger electrode 314B patterned to extend from the horizontal portion 314A .

The common electrode 318 is electrically connected to the common electrode connection pattern 330 and is formed in the pixel region. The common electrode 318 is formed to overlap with the horizontal portion 314A of the pixel electrode 314 in the pixel region and is formed in parallel with the finger electrode 314B of the pixel electrode 314, As shown in FIG.

The common electrode connection pattern 330 is formed so as to overlap with a part of the common electrode 318 which is not overlapped with the horizontal portion 314A of the pixel electrode 314 and to partition the pixel region. The common electrode connection pattern 330 is connected to the common electrode 318 through the second contact hole 321 passing through the protective film and the gate insulating film. The common electrode connection pattern 330 includes liquid crystal cells P (1,1), P (1,2), P (2,3), P (1,1) (2, 4) to the common electrodes 230.

The manufacturing process of the thin film transistor substrate including the common electrode connection pattern 230 is substantially the same as that described in the first embodiment, and thus a description thereof will be omitted.

FIG. 15 is a diagram comparing a data voltage range used in a driving method according to the first and second embodiments of the present invention and a data voltage range used in a conventional dot inversion driving method.

As shown in Fig. 15, in order to realize arbitrary gradation, a relatively large data voltage has to be applied to the liquid crystal cell by fixing the common voltage Vcom in the conventional dot inversion driving method. However, in the dot / horizontal two-dot version driving method according to the present invention, since the common voltage can be swung between the potential level of the first common voltage Vcom1 and the potential level of the second common voltage Vcom2, The magnitude of the data voltage necessary for implementing the same gray scale as the system is greatly reduced. In other words, the liquid crystal display according to the present invention can make the charged amount of the liquid crystal cell equal to that of the conventional liquid crystal display even with a data voltage much smaller than the conventional one.

As described above, the liquid crystal display device and the driving method thereof according to the present invention minimize the flicker in both the vertical and horizontal directions by reversing the polarity of the data voltage supplied in units of a certain liquid crystal cell (s) in the horizontal and / The display quality can be increased.

Further, in the liquid crystal display device and the driving method thereof according to the present invention, liquid crystal cells having the same polarity among the liquid crystal cells whose polarities change in units of a certain liquid crystal cell in the horizontal and vertical directions are electrically connected , And a common voltage having the polarity opposite to that of the polarity is applied to the liquid crystal cells. According to the dot / horizontal 2-dot inversion method according to the present invention, since the common voltage swings in a phase opposite to the polarity of the data voltage, the size of the data voltage for realizing the same gradation compared to the conventional one is considerably reduced. Accordingly, the liquid crystal display device and the driving method thereof according to the present invention can reduce the range of the data voltage output from the data driving circuit, thereby greatly reducing power consumption in the data driving circuit.

 It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. For example, in the embodiment of the present invention, only the dot inversion method and the horizontal two dot version method are described as an example, but the technical idea of the present invention is not limited to this, and the horizontal / vertical k (k is a positive integer of 1 or more) It is needless to say that the present invention can be applied to a version system. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is an equivalent circuit diagram for one pixel in a general liquid crystal display device.

Fig. 2 is a diagram showing a polarity change of a liquid crystal cell in a dot inversion driving method; Fig.

3 is a view showing a selection range of data voltages in a dot inversion driving method;

4 is a diagram showing a change in polarity of a liquid crystal cell in a line-inversion driving method;

5 shows a selection range of a data voltage in a line inversion driving method;

6 is a block diagram of a liquid crystal display device according to the present invention.

7 is a detailed block diagram of the data driving circuit of Fig.

8 is a block diagram showing a DAC according to a first embodiment of the present invention in detail;

9 is a block diagram showing details of a DAC according to a second embodiment of the present invention;

10 to 12 are views showing a connection structure of a liquid crystal display panel according to a first embodiment of the present invention.

13 and 14 are views showing a connection structure of a liquid crystal display panel according to a second embodiment of the present invention.

15 is a view for comparing a data voltage range used in a driving method according to the first and second embodiments of the present invention and a data voltage range used in a conventional dot inversion driving method.

Description of the Related Art

110: timing controller 120: data driving circuit

122: shift register 123: first latch array

124: second latch array 125: gamma compensation voltage generator

126: digital-to-analog converter 127: charge share circuit

128: output circuit 130: gate drive circuit

140: liquid crystal display panel 202, 302: gate line

204, 304: Data line 208, 308: Gate electrode

210, 310: source electrode 212, 312: drain electrode

213, 221, 313, 321: contact holes 214, 314:

230a, 330a: first common electrode connection pattern 230b, 330b: second common electrode connection pattern

240a, 340a: First common voltage supply line 240b, 340b: Second common voltage supply line

218,318: Common electrode

Claims (12)

A plurality of liquid crystal cells driven by a data voltage and a common voltage of opposite polarities; A first common electrode connection pattern connecting common electrodes of first liquid crystal cells supplied with a common voltage having a first polarity among the liquid crystal cells; A second common electrode connection pattern for connecting the common electrodes of the second liquid crystal cells supplied with the common voltage of the second polarity opposite to the first polarity among the liquid crystal cells to each other; A first common voltage supply line formed to supply a common voltage of the first polarity to the first common electrode connection pattern and to surround a part of the liquid crystal cells; And And a second common voltage supply line formed in a "" ' ' shape to supply a common voltage of the second polarity to the second common electrode connection pattern and surround the rest except for a part of the liquid crystal cells; Common electrodes of the first liquid crystal cells are connected to the first common electrode connection pattern through first contact holes, And common electrodes of the second liquid crystal cells are connected to the second common electrode connection pattern through second contact holes. The method according to claim 1, Wherein the first common electrode connection pattern is partially overlapped with the common electrodes of the first liquid crystal cells with at least one insulating film interposed therebetween, Wherein the second common electrode connection pattern is partially overlapped with the common electrodes of the second liquid crystal cells with at least one insulating film interposed therebetween, Wherein the first and second common electrode connection patterns are simultaneously patterned with the pixel electrodes of the first and second liquid crystal cells to which the data voltage is supplied. The method according to claim 1, And the polarity of the data voltage is inverted in units of one liquid crystal cell adjacent in the horizontal and vertical directions. The method according to claim 1, The polarity of the data voltage, Wherein the liquid crystal display panel is inverted in units of two adjacent liquid crystal cells in a horizontal direction and inverted in a unit of a neighboring liquid crystal cell in a vertical direction. The method according to claim 3 or 4, Wherein the first common electrode connection pattern and the second common electrode connection pattern are electrically insulated from each other to electrically connect liquid crystal cells supplied with data voltages having the same polarity. 3. The method of claim 2, Wherein the common electrodes of the first and second liquid crystal cells are formed on the same substrate together with the pixel electrodes of the first and second liquid crystal cells. delete The method according to claim 1, Common electrodes of the first common voltage supply line, the second common voltage supply line, and the first and second liquid crystal cells are formed through the same metal patterning process, Wherein the first common electrode connection pattern, the second common electrode connection pattern, and the pixel electrodes of the first and second liquid crystal cells are formed through the same transparent conductive film patterning process. delete delete delete delete

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