KR20080035086A - Liquid crystal display - Google Patents

Abstract

An LCD(Liquid Crystal Display) is provided to test an output by disposing a test pad in an output terminal of the last dummy stage, and determine a generated fault as a line fault caused by a gate line within a display area if the line fault is generated even when the output is normal, thereby easily determining whether the fault is caused by the signal line within the display area or by a shift register. An LCD comprises plural pixels, a gate line and plural stages(410). The gate line is connected to the pixel. The plural stages are connected to the gate line to generate gate signals, and apply the gate signal to the gate line. The pixel is disposed in a display area. A gate driving unit(400) is disposed in a peripheral area. In the gate line connected to the last stage of the plural stages, a test pad is disposed.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

With reference to the accompanying drawings will be described in detail the embodiments of the present invention to make the present invention clear.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a gate driver according to an exemplary embodiment of the present invention.

4 is a block diagram of a gate driver according to another exemplary embodiment of the present invention.

<Description of Drawing>

3: liquid crystal layer 100: lower display panel

191: pixel electrode 200: upper display panel

230: color filter 270: common electrode

300: liquid crystal panel assembly 400: gate driver

410: stage 500: data driver

600: signal controller 800: gray voltage generator

TP1, TP2: test pad

R, G, B: Input image data DE: Data enable signal

MCLK: Main Clock Hsync: Horizontal Sync Signal

Vsync: Vertical Sync Signal CONT1: Gate Control Signal

CONT2: data control signal DAT: digital video signal

Clc: Liquid Crystal Capacitor Cst: Keeping Capacitor

Q: switching device

The present invention relates to a liquid crystal display device.

Recently, organic light emitting display (OLED), plasma display panel (PDP), and liquid crystal display (LCD) are substituted for heavy and large cathode ray tube (CRT). Flat panel display devices such as are being actively developed.

PDP is a device that displays characters or images using plasma generated by gas discharge, and OLED displays characters or images by using electroluminescence of specific organic materials or polymers. The liquid crystal display device applies an electric field to a liquid crystal layer interposed between two display panels, and adjusts the intensity of the electric field to adjust a transmittance of light passing through the liquid crystal layer to obtain a desired image.

Among such flat panel display devices, for example, a liquid crystal display includes a display panel including a pixel including a switching element and a display signal line, and a gate driver to turn on / off the switching element of the pixel by sending a gate signal to a gate line among the display signal lines; That is, it includes a shift register.

The shift register includes a plurality of stages connected to each other, and each stage includes a plurality of transistors.

On the other hand, the liquid crystal display detects a defect such as disconnection or short circuit through various inspections and repairs or discards it.

By the way, it is difficult to detect a defect when the shift register is integrated in the liquid crystal display. This is because the shift register is made by the same process as the switching element of the pixel. For example, it is difficult to determine whether the signal is not transmitted to the gate line because of the disconnection of the gate line in the display area or the defect of the shift register itself.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of easily determining a defect.

According to an exemplary embodiment of the present invention, a liquid crystal display including a peripheral area and a display area includes a plurality of pixels, a gate line connected to the pixel, and a gate signal connected to the gate line. A gate driver including a plurality of stages to generate and apply to the gate line, the pixel is disposed in the display area, the gate driver is disposed in the peripheral area, and a last one of the plurality of stages An inspection pad may be disposed on the gate line connected to the stage.

The gate line may be disposed over the peripheral area and the display area, and the test pad may be disposed at the peripheral area.

The gate driver may be integrated in the liquid crystal display.

In addition, the pixel may include a switching element that operates according to the gate signal, and the switching element may be made of amorphous silicon.

On the other hand, the liquid crystal display according to another embodiment of the present invention, a plurality of pixels, a gate line connected to the pixel, and a plurality of stages connected to the gate line and generating and applying a gate signal to the gate line The gate driver includes a gate driver including a gate off voltage, a plurality of clock signals, and an initialization signal, and a test pad configured to detect the initialization signal in the vicinity of a first stage of the plurality of stages.

In this case, the initialization signal may be an output of a last stage of the plurality of stages.

The gate driver may be integrated in the liquid crystal display.

In addition, the pixel may include a switching element that operates according to the gate signal, and the switching element may be made of amorphous silicon.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily practice the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. Include. In contrast, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a plurality of data lines for transmitting a data signal ( D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX, for example, the pixel PX connected to the i-th (i = 1, 2,, n) gate line G _i and the j-th (j = 1, 2,, m) data line Dj. ) Includes a switching element Q connected to the signal line G _i D _j , a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

The gate driver 400 is formed in the same process as the switching element Q of the pixel PX and is integrated in the peripheral area of the liquid crystal panel assembly 300, and the gate lines G ₁ -G of the liquid crystal panel assembly 300 are provided. _n is applied to the gate line G ₁ -G _n connected to the gate line voltage Von and the gate-off voltage Voff.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or mounted on a flexible printed circuit film (not shown). And attached to the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m and the thin film transistor switching element Q. It may be. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is a load for applying a data signal to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the start of image data transmission for the pixels PX in one row [bundling]. Signal LOAD and data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal for the common voltage &quot;) RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixels PX in one row (bundling), and each digital image signal DAT. By converting the digital image signal DAT into an analog data signal by selecting a gray scale voltage corresponding to), it is applied to the corresponding data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. Then, the data signal applied to the data lines D ₁ -D _m is applied to the pixel PX through the switching element Q turned on.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all the gate lines G ₁ -G _n. ), The gate-on voltage Von is sequentially applied to the data signal to all the pixels PX, thereby displaying an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarity of the data signal flowing through one data line is changed (eg, row inversion and point inversion) or the polarity of the data signal applied to one pixel row is different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

Next, the gate driver of the liquid crystal display according to the exemplary embodiment of the present invention will be described in more detail with reference to FIGS. 3 and 4.

3 is a block diagram of a gate driver according to an exemplary embodiment of the present invention, and FIG. 4 is a block diagram of a gate driver according to another exemplary embodiment of the present invention.

The gate driver 400 shown in FIG. 3 is a shift register including a plurality of stages 410 arranged in a line and connected to the gate lines G ₁ -G _n , respectively, and include a scan start signal STV, The initialization signal INT, the plurality of clock signals CLK1 and CLK2 and the gate off voltage Voff are input. An NMOS transistor TR is connected to the end of each gate line G ₁ -G _n , and a gate off voltage Voff is input.

Although not shown, each shift register 410 also includes a plurality of NMOS transistors.

Each stage 410 includes a set terminal S, a gate voltage terminal GV, a pair of clock terminals CK1 and CK2, a reset terminal R, a frame reset terminal FR, and a gate output terminal ( OUT). However, the last dummy stage does not have the reset terminal R and the frame reset terminal FR.

The set terminal S of each stage, for example, the j-th stage ST _j , has a gate output of the front stage ST _j-1 , that is, a front gate output Gout (j-1), and a reset terminal ( The gate output of the rear stage ST _{j + 1} , that is, the rear gate output Gout (j + 1) is input to R, and the clock signals CLK1 and CLK2 are input to the clock terminals CK1 and CK2. The gate off voltage Voff is input to the gate voltage terminal GV. The gate output terminal OUT outputs the gate output Gout (j).

However, the scan start signal STV is input to the first stage of the shift register 400 instead of the front carry output. Further, when the clock signal CLK1 is input to the clock terminal CK1 of the j-th stage ST _j and the clock signal CLK2 is input to the clock terminal CK2, the (j-1) th and (j) adjacent thereto are The clock signal CLK2 is input to the clock terminal CK1 of the ₊ 1th stage ST _j-1 and ST _{j + 1} , and the clock signal CLK1 is input to the clock terminal CK2.

Each clock signal CLK1 and CLK2 is equal to the gate-on voltage Von when the voltage level is high, and equal to the gate-off voltage Voff when the voltage level is high so as to drive the switching element Q of the pixel. desirable. Each clock signal CLK1 and CLK2 may have a duty ratio of 50% and a phase difference between the two clock signals CLK1 and CLK2 may be 180 °.

In this way, each stage 410, for example the j th stage ST, is based on the front gate output Gout (j-1) and the rear gate output Gout (j + 1) and the clock signal CLK1. , The gate signal Gout (j) is generated in synchronization with CLK2).

At this time, the output Gout (n + 1) of the last dummy stage ST _{n + 1} is applied to the control terminal of the transistor TR, while resetting the frames of all the remaining stages 410 as the initialization signal INT. It is input to the terminal FR.

At this time, as illustrated in FIG. 3, the test pad TP1 is disposed at the output terminal OUT of the last dummy stage ST _{n + 1} to test the output Gout (n + 1).

In this way, it is possible to easily determine whether the failure is caused by the disconnection of the gate lines G1 -Gn in the display area or the failure of the shift register 410. That is, when disconnection failure occurs even when the output Gout (n + 1) is normal, it may be determined as the disconnection failure by the gate lines G1 -Gn in the display area.

In addition, as illustrated in FIG. 4, the test pad TP2 is disposed near the path where the output Gout (n + 1) is input as the initialization signal INT, for example, the first stage ST1 to output the output Gout. (n + 1)]. In the embodiment illustrated in FIG. 4, the test pad TP2 is disposed at the inlet of the shift register 400, and thus, the test pad TP2 may be easier to inspect than the embodiment illustrated in FIG. 3.

In this manner, it is possible to easily determine whether the signal line in the display area is defective or the shift register itself is defective.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (8)

A liquid crystal display device comprising a peripheral area and a display area, A plurality of pixels, A gate line connected to the pixel, and A gate driver connected to the gate line and including a plurality of stages for generating a gate signal and applying the gate signal to the gate line; Including, The pixel is disposed in the display area, the gate driver is disposed in the peripheral area, An inspection pad is disposed on the gate line connected to the last stage of the plurality of stages. Liquid crystal display. In claim 1, The gate line is disposed over the peripheral area and the display area; The test pad is disposed in the peripheral area Liquid crystal display. In claim 2, And the gate driver is integrated in the liquid crystal display. In claim 1, The pixel includes a switching element that operates according to the gate signal, The switching element is made of amorphous silicon Liquid crystal display. A plurality of pixels, A gate line connected to the pixel, and A gate driver connected to the gate line and including a plurality of stages for generating a gate signal and applying the gate signal to the gate line; Including, A gate-off voltage, a plurality of clock signals, and an initialization signal are input to the stage, An inspection pad for detecting the initialization signal is disposed near a first stage of the plurality of stages. Liquid crystal display. In claim 5, And the initialization signal is an output of a last stage of the plurality of stages. In claim 6, And the gate driver is integrated in the liquid crystal display. In claim 5, The pixel includes a switching element that operates according to the gate signal, The switching element is made of amorphous silicon Liquid crystal display.

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