CN106297616B - Array detection circuit, driving method, display driver, display substrate and device - Google Patents
Array detection circuit, driving method, display driver, display substrate and device Download PDFInfo
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- CN106297616B CN106297616B CN201610821948.2A CN201610821948A CN106297616B CN 106297616 B CN106297616 B CN 106297616B CN 201610821948 A CN201610821948 A CN 201610821948A CN 106297616 B CN106297616 B CN 106297616B
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
Abstract
The invention provides an array detection circuit, a driving method, a display driver, a display substrate and a device. The array detection circuit includes: the first detection unit controls the output ends of the GOA units in the odd-numbered rows to be connected with the first detection control line and controls the output ends of the GOA units in the even-numbered rows to be connected with the first level line under the control of a first detection control signal output by the first detection control line; and the second detection unit controls the output ends of the GOA units in the even rows to be connected with the second detection control line and controls the output ends of the GOA units in the odd rows to be connected with the first level line under the control of a second detection control signal output by the second detection control line. The invention can realize the purpose of respectively opening the odd-numbered grid lines and the even-numbered grid lines and is beneficial to improving the bad detection rate of array detection.
Description
Technical Field
The invention relates to the technical field of array detection, in particular to an array detection circuit, a driving method, a display driver, a display substrate and a device.
Background
At present, the design of products with low cost and narrow frames is the development trend of the liquid crystal panel industry. The goa (Gate driver on array) is a Gate line driving circuit on the TFT substrate, and can replace the function of a Gate IC (Gate driver), thereby reducing the cost and facilitating the realization of a narrow frame design. The current GOA products are generally classified into Normal Pattern and GOA Pattern when AT (Array Test) is performed. (GOA Pattern is a GOA signal time sequence which is input in actual design during AT, so that the function of a GOA region is verified, the aspect of the invention is not related, and the description is not repeated) when an AA (effective display region) region is detected, a Normal Pattern is adopted, all signals of the GOA are set to be high level, the function of pulling up OUTPUT signals OUTPUT of all lines of the GOA can be realized, but the odd line grid lines and the even line grid lines in the AA region can not be respectively opened, and AT missing detection is easy to occur.
Disclosure of Invention
The invention mainly aims to provide an array detection circuit, a driving method, a display driver, a display substrate and a device, and solves the problems that in the prior art, the odd-numbered row grid lines and the even-numbered row grid lines in an AA area can not be respectively opened during array detection, and AT (auto-test) missing detection is easy to occur.
In order to achieve the above object, the present invention provides an array detection circuit applied to a GOA circuit, wherein the GOA circuit includes a plurality of cascaded rows of GOA cells, and the array detection circuit includes:
the first detection unit is respectively connected with a first detection control line, a first level line and the output ends of the multiple GOA units, and is used for controlling the output ends of the odd-numbered GOA units to be connected with the first detection control line and controlling the output ends of the even-numbered GOA units to be connected with the first level line under the control of a first detection control signal output by the first detection control line; and the number of the first and second groups,
and the second detection unit is respectively connected with a second detection control line, the first level line and the output ends of the multiple rows of GOA units, and is used for controlling the output ends of the GOA units in the even rows to be connected with the second detection control line and controlling the output ends of the GOA units in the odd rows to be connected with the first level line under the control of a second detection control signal output by the second detection control line.
In practice, the first detection unit includes a plurality of first switching transistors;
the grid electrode of each first switch transistor is connected with the first detection control line;
the first pole of the 2 nth first switching transistor is connected with the output end of the GOA unit in the 2 nth row; the first pole of the 2n-1 st first switching transistor is connected with the output end of the GOA unit in the 2n-1 th row; n is a positive integer;
the second pole of the 2 n-th first switching transistor is connected to the first level line, and the second pole of the 2n-1 th first switching transistor is connected to the first detection control line.
In practice, the plurality of first switching transistors are all n-type transistors or the plurality of first switching transistors are all p-type transistors.
In practice, the second detection unit includes a plurality of second switching transistors;
the grid electrode of each second switch transistor is connected with the second detection control line;
the first pole of the 2 nth second switching transistor is connected with the output end of the GOA unit in the 2 nth row; the first pole of the 2n-1 second switching transistor is connected with the output end of the GOA unit in the 2n-1 row; n is a positive integer;
a second pole of the 2n-1 th second switching transistor is connected to the first level line, and a second pole of the 2 n-th second switching transistor is connected to the second detection control line.
In practice, the plurality of second switching transistors are all n-type transistors or the plurality of second switching transistors are all p-type transistors.
The invention also provides a driving method of the array detection circuit, which is applied to the array detection circuit and comprises the following steps:
a first detection control step: under the control of a first detection control signal output by a first detection control line, the first detection unit controls the output ends of the GOA units in the odd-numbered rows to be connected with the first detection control line and controls the output ends of the GOA units in the even-numbered rows to be connected with a first level line;
a second detection control step: under the control of a second detection control signal output by the second detection control line, the second detection unit controls the output ends of the GOA units in the even rows to be connected with the second detection control line and controls the output ends of the GOA units in the odd rows to be connected with the first level line.
In practice, when the types of transistors included in the first detection unit are all n-type, the first detection control step includes: in the odd-numbered row detection stage, a first level line outputs a low level, a first detection control line outputs a high level, and a first detection unit controls the output end of the odd-numbered row GOA unit to be connected with the first detection control line so as to control the electric potential of the output end of the odd-numbered row GOA unit to be the high level and control the output end of the even-numbered row GOA unit to be connected with the first level line so as to control the electric potential of the output end of the even-numbered row GOA unit to be the low level;
when the types of transistors included in the first detection unit are all p-type, the first detection control step includes: in the even-numbered row detection stage, the first level line outputs a high level, the first detection control line outputs a low level, and the first detection unit controls the output end of the odd-numbered row of GOA units to be connected with the first detection control line, so that the potential of the odd-numbered row of GOA units is controlled to be a low level, the output end of the even-numbered row of GOA units is controlled to be connected with the first level line, and the potential of the output end of the even-numbered row of GOA units is controlled to be a high level.
In practice, when the transistors included in the second detection unit are all of n-type, the second detection control step includes: in the even-numbered row detection stage, the first level line outputs a low level, the second detection control line outputs a high level, the second detection unit controls the output end of the even-numbered row GOA unit to be connected with the second detection control line so as to control the electric potential of the output end of the even-numbered row GOA unit to be the high level, and controls the output end of the odd-numbered row GOA unit to be connected with the first level line so as to control the electric potential of the output end of the odd-numbered row GOA unit to be the low level;
when the types of transistors included in the second detection unit are all p-type, the second detection control step includes: in the odd-numbered line detection stage, the first level line outputs a high level, the second detection control line outputs a low level, the second detection unit controls the output end of the even-numbered line GOA unit to be connected with the second detection control line so as to control the potential of the output end of the even-numbered line GOA unit to be a low level, and controls the output end of the odd-numbered line GOA unit to be connected with the first level line so as to control the potential of the output end of the odd-numbered line GOA unit to be a high level.
In practice, when the transistors included in the first detection unit are all of n-type, and the transistors included in the second detection unit are all of n-type, the driving method of the array detection circuit further includes:
in the standard mode detection stage, the first level line outputs a high level, the first detection control line outputs a high level, and the second detection control line outputs a high level; the first detection unit controls the output ends of the GOA units in the odd rows to be connected with the first detection control line so that the electric potential of the output ends of the GOA units in the odd rows is at a high level, and controls the output ends of the GOA units in the even rows to be connected with the first level line so that the electric potential of the output ends of the GOA units in the even rows is at a high level; the second detection unit controls the output ends of the GOA units in the even rows to be connected with the second detection control line so that the electric potential of the output ends of the GOA units in the even rows is at a high level, and controls the output ends of the GOA units in the odd rows to be connected with the first level line so that the electric potential of the output ends of the GOA units in the odd rows is at a high level.
The invention also provides a display driver, which comprises the GOA circuit, wherein the GOA circuit comprises a plurality of rows of cascaded GOA units, and the display driver also comprises the array detection circuit.
The invention also provides a display substrate comprising the display driver.
The invention also provides a display device which comprises the display substrate.
Compared with the prior art, the array detection circuit, the driving method, the display driver, the display substrate and the device provided by the invention have the advantages that the purpose of respectively opening the odd-numbered grid lines and the even-numbered grid lines can be realized under the control of the first detection control signal and the second detection control signal by adopting the first detection unit and the second detection unit through setting the potential value of the first detection control signal output by the first detection control line and setting the potential value of the second detection control signal output by the second detection control line, and the bad detection rate of an AA (effective display) area is favorably improved.
Drawings
FIG. 1 is a block diagram of an array detection circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of a first embodiment of an array detection circuit according to the present invention;
FIG. 3A is a timing diagram of the first embodiment of the array detection circuit of the present invention during the odd row detection phase;
FIG. 3B is a timing diagram of the first embodiment of the array detection circuit of the present invention during the even row detection phase;
FIG. 3C is a timing diagram of the first embodiment of the array detection circuit of the present invention during the normal mode detection phase;
FIG. 4 is a block diagram of a second embodiment of an array detection circuit according to the present invention;
FIG. 5A is a timing diagram of the second embodiment of the array detection circuit of the present invention during the odd row detection phase;
FIG. 5B is a timing diagram of the detection stage of the even rows in the second embodiment of the array detection circuit according to the present invention;
fig. 6 is a flow chart of a driving method of the array detection circuit according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the array detection circuit according to the embodiment of the present invention is applied to a GOA circuit, where the GOA circuit includes multiple cascaded rows of GOA cells (not shown in fig. 1); the array detection circuit includes:
first detecting units 11, respectively connected to a first detecting control line CL1, a first level line (not shown in fig. 1) and the output terminals of the plurality of rows of GOA units, for controlling the output terminals of the odd-numbered rows of GOA units to be connected to the first detecting control line CL1 and controlling the output terminals of the even-numbered rows of GOA units to be connected to the first level line (not shown in fig. 1) under the control of a first detecting control signal GO output by the first detecting control line CL 1; and the number of the first and second groups,
the second detecting units 12 are respectively connected to the second detecting control line CL2, the first level line (not shown in fig. 1) and the output terminals of the plurality of rows of GOA units, and are configured to control the output terminals of the even-numbered rows of GOA units to be connected to the second detecting control line CL2 and control the output terminals of the odd-numbered rows of GOA units to be connected to the first level line (not shown in fig. 1) under the control of the second detecting control signal GE output by the second detecting control line CL 2.
In fig. 1, OUTPUT terminal labeled OUTPUT1 is the OUTPUT terminal of the GOA cells in the first row, OUTPUT terminal labeled OUTPUT2 is the OUTPUT terminal of the GOA cells in the second row, OUTPUT terminal labeled OUTPUT N is the OUTPUT terminal of the GOA cells in the nth row, and N is the number of rows of GOA cells included in the GOA circuit.
The array detection circuit provided by the embodiment of the invention has the advantages that through setting the potential value of the first detection control signal output by the first detection control line and setting the potential value of the second detection control signal output by the second detection control line, the purpose of respectively opening the odd-numbered row grid lines and the even-numbered row grid lines can be realized under the control of the first detection control signal and the second detection control signal by adopting the first detection unit and the second detection unit, and the bad detection rate of an AA (effective display) area is favorably improved.
Specifically, the first detection unit may include a plurality of first switching transistors;
the grid electrode of each first switch transistor is connected with the first detection control line;
the first pole of the 2 nth first switching transistor is connected with the output end of the GOA unit in the 2 nth row; the first pole of the 2n-1 st first switching transistor is connected with the output end of the GOA unit in the 2n-1 th row; n is a positive integer;
the second pole of the 2 n-th first switching transistor is connected to the first level line, and the second pole of the 2n-1 th first switching transistor is connected to the first detection control line.
In actual operation, the plurality of first switching transistors are all n-type transistors or the plurality of first switching transistors are all p-type transistors.
Specifically, the second detection unit may include a plurality of second switching transistors;
the grid electrode of each second switch transistor is connected with the second detection control line;
the first pole of the 2 nth second switching transistor is connected with the output end of the GOA unit in the 2 nth row; the first pole of the 2n-1 second switching transistor is connected with the output end of the GOA unit in the 2n-1 row; n is a positive integer;
a second pole of the 2n-1 th second switching transistor is connected to the first level line, and a second pole of the 2 n-th second switching transistor is connected to the second detection control line.
In actual operation, the plurality of second switching transistors are all n-type transistors or the plurality of second switching transistors are all p-type transistors.
The array detection circuit of the present invention is illustrated in two specific embodiments below.
As shown in fig. 2, the first embodiment of the array detection circuit of the present invention includes a first detection unit and a second detection unit;
the first detection unit includes a plurality of first switching transistors;
the second detection unit includes a plurality of second switching transistors;
in fig. 2, reference numeral M11 is a first row of first switch transistors connected to OUTPUT terminals OUTPUT1 of a first row of GOA cells;
reference M21 is a second row first switch transistor connected to OUTPUT terminal OUTPUT2 of a second row of GOA cells;
reference numeral M31 is a third row first switch transistor connected to the OUTPUT terminal OUTPUT3 of the third row GOA unit;
reference M41 is a fourth row first switch transistor connected to OUTPUT terminal OUTPUT4 of the fourth row GOA unit;
a first switch transistor labeled MN1 for row N connected to output terminal output of GOA cell in row N;
reference M12 is the second switch transistor of the first row connected to OUTPUT terminal OUTPUT1 of the GOA cell of the first row;
second row second switch transistors, labeled M22, connected to OUTPUT terminals OUTPUT2 of second row GOA cells;
reference numeral M32 is a third row second switch transistor connected to the OUTPUT terminal OUTPUT3 of the third row GOA unit;
reference M42 is a fourth row second switch transistor connected to OUTPUT terminal OUTPUT4 of the fourth row GOA unit;
second switch transistors labeled MN2, for row N to which output terminals output of GOA cells in row N are connected;
assuming N is an even number;
in fig. 2, all transistors are n-type transistors;
the gate of M11, the gate of M21, the gate of M31, the gate of M41, and the gate of MN1 are all connected to a first detection control line CL 1;
the source of M11 is connected with OUTPUT1, the source of M21 is connected with OUTPUT2, the source of M31 is connected with OUTPUT3, the source of M41 is connected with OUTPUT4, and the source of MN1 is connected with OUTPUT;
the drain of M11, the drain of M31, and the drain of MN1 are all connected to a first detection control line CL 1;
the drain of M21 and the drain of M41 are both connected to a first level line VL 1;
the gate of M12, the gate of M22, the gate of M32, the gate of M42, and the gate of MN2 are all connected to a second detection control line CL 2;
the source of M21 is connected with OUTPUT1, the source of M22 is connected with OUTPUT2, the source of M32 is connected with OUTPUT3, the source of M42 is connected with OUTPUT4, and the source of MN2 is connected with OUTPUT;
the drain of M22 and the drain of M42 are both connected to a second detection control line CL 2;
the drain of M12, the drain of M32, and the drain of MN2 are all connected to a first level line VL 1.
In operation of the array detection circuit of the present invention as shown in figure 2,
as shown in fig. 3A, when GO OUTPUT by CL1 is high, GE OUTPUT by CL2 is low, and VL1 OUTPUTs low, M11, M21, M31, M41, and MN1 are all turned on, and M12, M22, M32, M42, and MN2 are all turned off, so that OUTPUT1 and OUTPUT3 OUTPUT high, and OUTPUT2, OUTPUT4, and OUTPUT 35output low;
as shown in fig. 3B, when GO OUTPUT by CL1 is low, GE OUTPUT by CL2 is high, and VL1 OUTPUTs low, M11, M21, M31, M41, and MN1 are all turned off, and M12, M22, M32, M42, and MN2 are all turned on, so that OUTPUT1 and OUTPUT3 OUTPUT low, and OUTPUT2, OUTPUT4, and OUTPUT 35output high;
as shown in fig. 3C, when GO OUTPUT by CL1 is high, GE OUTPUT by CL2 is high, and VL1 OUTPUTs high, M11, M21, M31, M41, and MN1 are all turned on, and M12, M22, M32, M42, and MN2 are all turned on, so that OUTPUT1 and OUTPUT3 OUTPUT high, and OUTPUT2, OUTPUT4, and OUTPUT 35also OUTPUT high;
in another case, when GO output by CL1 is at low level, GE output by CL2 is at low level, and VL1 outputs low level, all transistors in fig. 2 are turned off, and the potentials of the output terminals of the GOA cells in all rows are not affected by the array detection circuit shown in fig. 2, i.e., the array detection circuit has no effect on the gate line output.
As shown in fig. 4, the first embodiment of the array detection circuit according to the present invention includes a first detection unit 11 and a second detection unit 12;
the first detection unit 11 includes a plurality of first switching transistors;
the second detection unit 12 includes a plurality of second switching transistors;
in fig. 4, reference numeral M11 is a first row of first switch transistors connected to OUTPUT terminals OUTPUT1 of a first row of GOA cells;
reference M21 is a second row first switch transistor connected to OUTPUT terminal OUTPUT2 of a second row of GOA cells;
reference numeral M31 is a third row first switch transistor connected to the OUTPUT terminal OUTPUT3 of the third row GOA unit;
reference M41 is a fourth row first switch transistor connected to OUTPUT terminal OUTPUT4 of the fourth row GOA unit;
a first switch transistor labeled MN1 for row N connected to output terminal output of GOA cell in row N;
reference M12 is the second switch transistor of the first row connected to OUTPUT terminal OUTPUT1 of the GOA cell of the first row;
second row second switch transistors, labeled M22, connected to OUTPUT terminals OUTPUT2 of second row GOA cells;
reference numeral M32 is a third row second switch transistor connected to the OUTPUT terminal OUTPUT3 of the third row GOA unit;
reference M42 is a fourth row second switch transistor connected to OUTPUT terminal OUTPUT4 of the fourth row GOA unit;
second switch transistors labeled MN2, for row N to which output terminals output of GOA cells in row N are connected;
assuming that N is an odd number;
in fig. 4, all transistors are p-type transistors;
the gate of M11, the gate of M21, the gate of M31, the gate of M41, and the gate of MN1 are all connected to a first detection control line CL 1;
the drain of M11 is connected with OUTPUT1, the drain of M21 is connected with OUTPUT2, the drain of M31 is connected with OUTPUT3, the drain of M41 is connected with OUTPUT4, and the drain of MN1 is connected with OUTPUT;
the source of M11, the source of M31, and the source of MN1 are all connected to the first detection control line CL 1;
the source of M21 and the source of M41 are both connected to a first level line VL 1;
the gate of M12, the gate of M22, the gate of M32, the gate of M42, and the gate of MN2 are all connected to a second detection control line CL 2;
the drain of M21 is connected with OUTPUT1, the drain of M22 is connected with OUTPUT2, the drain of M32 is connected with OUTPUT3, the drain of M42 is connected with OUTPUT4, and the drain of MN2 is connected with OUTPUT;
the source of M22 and the source of M42 are both connected to a second detection control line CL 2;
the source of M12, the source of M32, and the source of MN2 are all connected to a first level line VL 1.
In operation of the array detection circuit of the present invention as shown in figure 4,
as shown in fig. 5A, when GO OUTPUT by CL1 is low, GE OUTPUT by CL2 is high, and VL1 OUTPUTs high, M11, M21, M31, M41, and MN1 are all turned on, and M12, M22, M32, M42, and MN2 are all turned off, so that OUTPUT1 and OUTPUT3 OUTPUT low, and OUTPUT2, OUTPUT4, and OUTPUT 35output high;
as shown in fig. 5B, when GO OUTPUT by CL1 is high, GE OUTPUT by CL2 is low, and VL1 OUTPUTs high, M11, M21, M31, M41, and MN1 are all turned off, and M12, M22, M32, M42, and MN2 are all turned on, so that OUTPUT1 and OUTPUT3 OUTPUT high, and OUTPUT2, OUTPUT4, and OUTPUT 35output low.
When the array detection circuit shown in fig. 4 of the present invention is in operation, when GO output by CL1 is at high level and GE output by CL2 is at high level, M11, M21, M31, M41, and MN1 are all turned off, M12, M22, M32, M42, and MN2 are all turned off, and the potentials of the output terminals of the GOA cells in all rows are not affected by the array detection circuit shown in fig. 4, that is, the array detection circuit does not affect the gate line output.
The invention designs a circuit structure for GOA product AT (Array Test), when the GOA product is used for detecting pixels in an AA (effective display) area, the purpose of respectively opening odd-numbered grid lines and even-numbered grid lines can be realized by operating the added AT circuit, and the invention is beneficial to improving the bad detection rate of the AA area.
As shown in fig. 6, the driving method of the array detection circuit according to the embodiment of the present invention is applied to the array detection circuit, and the driving method includes:
first detection control step S1: under the control of a first detection control signal output by a first detection control line, the first detection unit controls the output ends of the GOA units in the odd-numbered rows to be connected with the first detection control line and controls the output ends of the GOA units in the even-numbered rows to be connected with a first level line;
second detection control step S2: under the control of a second detection control signal output by the second detection control line, the second detection unit controls the output ends of the GOA units in the even rows to be connected with the second detection control line and controls the output ends of the GOA units in the odd rows to be connected with the first level line.
According to the driving method of the array detection circuit, the potential value of the first detection control signal output by the first detection control line is set, the potential value of the second detection control signal output by the second detection control line is set, and the purpose that the odd-numbered row grid lines and the even-numbered row grid lines are respectively opened under the control of the first detection control signal and the second detection control signal can be achieved by adopting the first detection unit and the second detection unit, so that the bad detection rate of an AA (effective display) area is favorably improved.
Specifically, when the types of transistors included in the first detection unit are all n-type, the first detection control step includes: in the odd-numbered row detection stage, a first level line outputs a low level, a first detection control line outputs a high level, and a first detection unit controls the output end of the odd-numbered row GOA unit to be connected with the first detection control line so as to control the electric potential of the output end of the odd-numbered row GOA unit to be the high level and control the output end of the even-numbered row GOA unit to be connected with the first level line so as to control the electric potential of the output end of the even-numbered row GOA unit to be the low level;
when the types of transistors included in the first detection unit are all p-type, the first detection control step includes: in the even-numbered row detection stage, the first level line outputs a high level, the first detection control line outputs a low level, and the first detection unit controls the output end of the odd-numbered row of GOA units to be connected with the first detection control line, so that the potential of the odd-numbered row of GOA units is controlled to be a low level, the output end of the even-numbered row of GOA units is controlled to be connected with the first level line, and the potential of the output end of the even-numbered row of GOA units is controlled to be a high level.
Specifically, when the types of transistors included in the second detection unit are all n-type, the second detection control step includes: in the even-numbered row detection stage, the first level line outputs a low level, the second detection control line outputs a high level, the second detection unit controls the output end of the even-numbered row GOA unit to be connected with the second detection control line so as to control the electric potential of the output end of the even-numbered row GOA unit to be the high level, and controls the output end of the odd-numbered row GOA unit to be connected with the first level line so as to control the electric potential of the output end of the odd-numbered row GOA unit to be the low level;
when the types of transistors included in the second detection unit are all p-type, the second detection control step includes: in the odd-numbered line detection stage, the first level line outputs a high level, the second detection control line outputs a low level, the second detection unit controls the output end of the even-numbered line GOA unit to be connected with the second detection control line so as to control the potential of the output end of the even-numbered line GOA unit to be a low level, and controls the output end of the odd-numbered line GOA unit to be connected with the first level line so as to control the potential of the output end of the odd-numbered line GOA unit to be a high level.
Specifically, when the types of the transistors included in the first detection unit are all n-type, and the types of the transistors included in the second detection unit are all n-type, the driving method of the array detection circuit further includes:
in the standard mode detection stage, the first level line outputs a high level, the first detection control line outputs a high level, and the second detection control line outputs a high level; the first detection unit controls the output ends of the GOA units in the odd rows to be connected with the first detection control line so that the electric potential of the output ends of the GOA units in the odd rows is at a high level, and controls the output ends of the GOA units in the even rows to be connected with the first level line so that the electric potential of the output ends of the GOA units in the even rows is at a high level; the second detection unit controls the output ends of the GOA units in the even rows to be connected with the second detection control line so that the electric potential of the output ends of the GOA units in the even rows is at a high level, and controls the output ends of the GOA units in the odd rows to be connected with the first level line so that the electric potential of the output ends of the GOA units in the odd rows is at a high level.
The display driver comprises a GOA circuit, wherein the GOA circuit comprises a plurality of cascaded GOA units, and the display driver also comprises the array detection circuit.
The display substrate of the embodiment of the invention comprises the display driver.
The display device provided by the embodiment of the invention comprises the display substrate.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (12)
1. An array detection circuit applied to a GOA circuit, wherein the GOA circuit comprises a plurality of cascaded rows of GOA units, the array detection circuit comprising:
the first detection unit is respectively connected with a first detection control line, a first level line and the output ends of the multiple GOA units, and is used for controlling the output ends of the odd-numbered GOA units to be connected with the first detection control line and controlling the output ends of the even-numbered GOA units to be connected with the first level line under the control of a first detection control signal output by the first detection control line; and the number of the first and second groups,
and the second detection unit is respectively connected with a second detection control line, the first level line and the output ends of the multiple rows of GOA units, and is used for controlling the output ends of the GOA units in the even rows to be connected with the second detection control line and controlling the output ends of the GOA units in the odd rows to be connected with the first level line under the control of a second detection control signal output by the second detection control line.
2. The array detection circuit of claim 1, wherein the first detection cell comprises a plurality of first switching transistors;
the grid electrode of each first switch transistor is connected with the first detection control line;
the first pole of the 2 nth first switching transistor is connected with the output end of the GOA unit in the 2 nth row; the first pole of the 2n-1 st first switching transistor is connected with the output end of the GOA unit in the 2n-1 th row; n is a positive integer;
the second pole of the 2 n-th first switching transistor is connected to the first level line, and the second pole of the 2n-1 th first switching transistor is connected to the first detection control line.
3. The array detection circuit of claim 2, wherein the first plurality of switching transistors are all n-type transistors or the first plurality of switching transistors are all p-type transistors.
4. The array detection circuit of any of claims 1 to 3, wherein the second detection cell comprises a plurality of second switching transistors;
the grid electrode of each second switch transistor is connected with the second detection control line;
the first pole of the 2 nth second switching transistor is connected with the output end of the GOA unit in the 2 nth row; the first pole of the 2n-1 second switching transistor is connected with the output end of the GOA unit in the 2n-1 row; n is a positive integer;
a second pole of the 2n-1 th second switching transistor is connected to the first level line, and a second pole of the 2 n-th second switching transistor is connected to the second detection control line.
5. The array detection circuit of claim 4, wherein the second plurality of switching transistors are all n-type transistors or the second plurality of switching transistors are all p-type transistors.
6. A driving method of an array detection circuit applied to the array detection circuit according to any one of claims 1 to 5, the driving method comprising:
a first detection control step: under the control of a first detection control signal output by a first detection control line, the first detection unit controls the output ends of the GOA units in the odd-numbered rows to be connected with the first detection control line and controls the output ends of the GOA units in the even-numbered rows to be connected with a first level line;
a second detection control step: under the control of a second detection control signal output by the second detection control line, the second detection unit controls the output ends of the GOA units in the even rows to be connected with the second detection control line and controls the output ends of the GOA units in the odd rows to be connected with the first level line.
7. The driving method of an array detection circuit according to claim 6, wherein when the types of transistors included in the first detection cell are all n-type, the first detection control step includes: in the odd-numbered row detection stage, a first level line outputs a low level, a first detection control line outputs a high level, and a first detection unit controls the output end of the odd-numbered row GOA unit to be connected with the first detection control line so as to control the electric potential of the output end of the odd-numbered row GOA unit to be the high level and control the output end of the even-numbered row GOA unit to be connected with the first level line so as to control the electric potential of the output end of the even-numbered row GOA unit to be the low level;
when the types of transistors included in the first detection unit are all p-type, the first detection control step includes: in the even-numbered row detection stage, the first level line outputs a high level, the first detection control line outputs a low level, and the first detection unit controls the output end of the odd-numbered row of GOA units to be connected with the first detection control line, so that the potential of the odd-numbered row of GOA units is controlled to be a low level, the output end of the even-numbered row of GOA units is controlled to be connected with the first level line, and the potential of the output end of the even-numbered row of GOA units is controlled to be a high level.
8. The driving method of an array detection circuit according to claim 7, wherein when the types of transistors included in the second detection cells are all n-type, the second detection control step includes: in the even-numbered row detection stage, the first level line outputs a low level, the second detection control line outputs a high level, the second detection unit controls the output end of the even-numbered row GOA unit to be connected with the second detection control line so as to control the electric potential of the output end of the even-numbered row GOA unit to be the high level, and controls the output end of the odd-numbered row GOA unit to be connected with the first level line so as to control the electric potential of the output end of the odd-numbered row GOA unit to be the low level;
when the types of transistors included in the second detection unit are all p-type, the second detection control step includes: in the odd-numbered line detection stage, the first level line outputs a high level, the second detection control line outputs a low level, the second detection unit controls the output end of the even-numbered line GOA unit to be connected with the second detection control line so as to control the potential of the output end of the even-numbered line GOA unit to be a low level, and controls the output end of the odd-numbered line GOA unit to be connected with the first level line so as to control the potential of the output end of the odd-numbered line GOA unit to be a high level.
9. The driving method of the array detection circuit according to claim 7 or 8, wherein when the transistors included in the first detection cells are all of n-type, and the transistors included in the second detection cells are all of n-type, the driving method of the array detection circuit further includes:
in the standard mode detection stage, the first level line outputs a high level, the first detection control line outputs a high level, and the second detection control line outputs a high level; the first detection unit controls the output ends of the GOA units in the odd rows to be connected with the first detection control line so that the electric potential of the output ends of the GOA units in the odd rows is at a high level, and controls the output ends of the GOA units in the even rows to be connected with the first level line so that the electric potential of the output ends of the GOA units in the even rows is at a high level; the second detection unit controls the output ends of the GOA units in the even rows to be connected with the second detection control line so that the electric potential of the output ends of the GOA units in the even rows is at a high level, and controls the output ends of the GOA units in the odd rows to be connected with the first level line so that the electric potential of the output ends of the GOA units in the odd rows is at a high level.
10. A display driver comprising a GOA circuit comprising a plurality of cascaded rows of GOA cells, characterized in that the display driver further comprises an array detection circuit according to any of claims 1 to 5.
11. A display substrate comprising the display driver of claim 10.
12. A display device comprising the display substrate according to claim 11.
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| CN109119043A (en) * | 2018-09-30 | 2019-01-01 | 惠科股份有限公司 | Display panel and its driving method, display device |
| CN109616036B (en) * | 2019-01-07 | 2022-01-18 | 重庆京东方显示技术有限公司 | Display screen monomer, display screen monomer bad position positioning system and positioning method thereof |
| CN113093446B (en) * | 2019-12-20 | 2024-03-26 | 京东方科技集团股份有限公司 | Detection circuit, array substrate, detection method of array substrate, electronic paper and detection tool |
| CN111599297B (en) * | 2020-06-19 | 2023-12-15 | 京东方科技集团股份有限公司 | Test circuit, test method and display device |
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