KR101240655B1 - Driving apparatus for display device - Google Patents

Abstract

The present invention relates to a driving device of a display device.

A driving apparatus of a display device including a plurality of stages connected to each other, wherein each stage includes a plurality of transistors and a capacitor, and each stage includes a scan start signal, a plurality of clock signals, and first and second gate offs. Voltages Voff1 and Voff2 are input, some of the transistors are connected to the first gate-off voltage, and some are connected to the second gate-off voltage. As described above, the leakage current of the contact may be reduced by connecting some transistors to the second gate off voltage Voff2 lower than the first gate off voltage Voff1 to make the voltage between the gate drains of the other transistors negative. For this reason, it is possible to prevent the display of the screen abnormally by allowing the transistor to operate correctly.

LCD, Gate-Off Voltage, Transistor, Leakage Current

Description

Drive device for display device {DRIVING APPARATUS FOR DISPLAY DEVICE}

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG.

1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.

2 is an equivalent circuit diagram of a pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a gate driver according to an embodiment of the present invention.

4 is an example of a circuit diagram of the j-th stage of the gate driver shift register shown in Fig.

5 is a signal waveform diagram of the gate driver shown in FIG.

FIG. 6 is a graph comparing leakage current characteristics of transistors forming the gate driver illustrated in FIG. 3.

<Description of Drawing>

3: liquid crystal layer 100: lower display panel

191: pixel electrode 200: upper display panel

230: color filter 270: common electrode

300: liquid crystal panel assembly 400: gate driver

410: stage 500:

600: a signal controller 800: a gradation voltage generator

R, G, B: input image data DE: data enable signal

MCLK: Main Clock Hsync: Horizontal Sync Signal

Vsync: Vertical Sync Signal CONT1: Gate Control Signal

CONT2: Data control signal DAT: Output video signal

PX: pixel Clc: liquid crystal capacitor

Cst: Holding capacitor Q: Switching element

STV1, STV2: scan start signals CLK1, CLK2: clock signal

S: Set terminal R: Reset terminal

GV1, GV2: Gate voltage terminal OUT: Output terminal

CK1, CK2: Clock terminal

The present invention relates to a driving device of a display device.

2. Description of the Related Art Recently, a cathode ray tube (CRT) has been replaced by an organic light emitting diode (OLED) display, a plasma display panel (PDP), a liquid crystal display LCD) are being actively developed.

A PDP is a device for displaying characters or images by using a plasma generated by a gas discharge, and an organic light emitting display displays characters or images by electroluminescence of specific organic materials or polymers. A liquid crystal display device obtains a desired image by applying an electric field to a liquid crystal layer interposed between two display panels and adjusting the intensity of the electric field to adjust the transmittance of light passing through the liquid crystal layer.

Of these display devices, for example, a liquid crystal display device includes a display panel provided with a pixel including a switching element and a display signal line, and a gate-on voltage and a gate-off voltage to the gate line of the display signal line to turn on / And a data driver for applying a data voltage to a data line of a display signal line and applying the data voltage to the pixel through a turned-on switching element.

The gate driver may be formed in the same process as the switching elements of the pixels and integrated in the display panel part in order to reduce the cost in the large-sized display device as well as the small-sized display device.

The gate driver includes a plurality of stages that are substantially connected to each other and arranged in a row as a shift register, and the first stage receives a scan start signal to output a gate output while simultaneously carrying a carry output to the next stage. Send to sequentially generate the gate outputs. This carry output may use a gate output.

In this case, each shift register includes a plurality of transistors. In a specific transistor, a leakage current flows due to the same voltage between the gate and the drain. As a result, an abnormal operation of the output terminal due to failure to maintain a constant voltage may cause an abnormality of the screen as a whole.

Accordingly, an aspect of the present invention is to provide a driving device for a reliable display device by reducing leakage current.

According to an exemplary embodiment of the present invention, a driving device of a display device including a plurality of stages connected to each other includes a plurality of transistors and a capacitor, and each stage starts scanning. Signal, a plurality of clock signals, and first and second gate off voltages Voff1 and Voff2, and some of the transistors are connected to the first gate off voltage, and some are connected to the second gate off voltage. It is.

In this case, the second gate off voltage may be smaller than the first gate off voltage.

In addition, each stage has a set terminal, a reset terminal, first and second gate voltage terminals, an output terminal, and first and second clock terminals.

The plurality of transistors and capacitors may include a first transistor connected between the first clock terminal and the output terminal and having a control terminal connected to a first contact point, and a control terminal and an input terminal are commonly connected to the set terminal. A second transistor having an output terminal connected to the first contact point, a third transistor connected between the first contact point and the second gate voltage terminal, and a control terminal connected to the reset terminal; A fourth transistor connected between a first contact point and the second gate voltage terminal and a control terminal connected to the second contact point; a fourth transistor connected between the output terminal and the first gate voltage terminal; and a control terminal connected to the second contact point. A fifth transistor connected between the output transistor and the first gate voltage terminal; A sixth transistor having a terminal connected to the second clock terminal, a seventh transistor connected between the second contact and the first gate voltage terminal and a control terminal connected to the first contact, and the first clock And a first capacitor connected between the terminal and the second contact, and a second capacitor connected between the first contact and the output terminal.

In this case, the first gate off voltage may be input to the first gate voltage terminal, and the second gate off voltage may be input to the second gate voltage terminal.

The second gate off voltage may be smaller than the first gate off voltage. For example, the first gate off voltage may be -10V, and the second gate off voltage may be -15V.

The stage may be integrated in the display device.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated with like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

First, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2, and a liquid crystal display device will be described as an example.

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a pixel of a liquid crystal display device according to an embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention may include a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a gate driver 400 connected thereto. A gate voltage generator 700 connected to 400, a gray voltage generator 800 connected to the data driver 500, and a signal controller 600 for controlling them are included.

The liquid crystal panel assembly 300 includes a plurality of signal lines G ₁ -G _n and D ₁ -D _m and a plurality of pixels PX connected to the signal lines G ₁ -G _n and D ₁ -D _m arranged in the form of a matrix . 2, the liquid crystal display panel assembly 300 includes lower and upper display panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n and D ₁ -D _m include a plurality of gate lines G ₁ -G _n for transferring gate signals (also referred to as "scan signals") and a plurality of data lines D ₁ -D _m ). The gate lines G _{1 to} G _n extend in a substantially row direction and are substantially parallel to each other, and the data lines D _{1 to} D _m extend in a substantially column direction and are substantially parallel to each other.

The pixel PX connected to each pixel PX, for example, the i-th (i = 1, 2, n) gate line G _i and the j- Includes a switching element Q connected to a signal line G _i D _j and a liquid crystal capacitor Clc and a storage capacitor Cst connected thereto. The storage capacitor Cst can be omitted if necessary.

The switching element Q is a three terminal element such as a thin film transistor provided in the lower panel 100. The control terminal is connected to the gate line G _i and the input terminal is connected to the data line D _j And the output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200 as two terminals and the liquid crystal layer 3 between the two electrodes 191 and 270, . The pixel electrode 191 is connected to the switching element Q and the common electrode 270 is formed on the entire surface of the upper panel 200 to receive the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst serving as an auxiliary capacitor of the liquid crystal capacitor Clc is formed by superimposing a separate signal line (not shown) and a pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween, A predetermined voltage such as the common voltage Vcom is applied to the separate signal lines. However, the storage capacitor Cst may be formed by overlapping the pixel electrode 191 with the previous gate line immediately above via an insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of primary colors (space division), or each pixel PX alternately displays a basic color (time division) So that the desired color is recognized by the spatial and temporal sum of these basic colors. Examples of basic colors include red, green, and blue. 2 shows that each pixel PX has a color filter 230 indicating one of the basic colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of space division. 2, the color filter 230 may be formed on or below the pixel electrode 191 of the lower panel 100. [

At least one polarizer (not shown) for polarizing light is attached to the outer surface of the liquid crystal panel assembly 300.

Referring again to FIG. 1, the gradation voltage generator 800 generates two sets of gradation voltages (or a set of reference gradation voltages) related to the transmittance of the pixel PX. One of the two has a positive value for the common voltage (Vcom) and the other has a negative value.

The gate voltage generator 700 generates a gate on voltage Von and a plurality of gate off voltages Voff1 and Voff2.

The gate driver 400 is integrated in the liquid crystal panel assembly 300, and is connected to the gate lines G ₁ -G _n to be connected to the gate on voltage Von and the gate off voltage Voff1 from the gate voltage generator 700. , A gate signal composed of a combination of Voff2 is applied to the gate lines G ₁ -G _n .

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects the gradation voltage from the gradation voltage generator 800 and supplies it as a data signal to the data line D ₁ -D _m . However, when the gradation voltage generator 800 provides only a predetermined number of reference gradation voltages instead of providing all the voltages for all gradations, the data driver 500 divides the reference gradation voltage and supplies the gradation voltage And selects a data signal among them.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 500, 600, 700, and 800 except the gate driver 400 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film. (Not shown) may be attached to the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP), or may be mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 500, 600, 700, 800 may be integrated with the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m and the thin film transistor switching elements Q It is possible. In addition, the drivers 500, 600, 700, 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside of a single chip.

The operation of the liquid crystal display device will now be described in detail.

The signal controller 600 receives an input control signal for controlling the display of the input image signals R, G, and B from an external graphic controller (not shown). Examples of the input control signal include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes scan start signals STV1 and STV2 indicating the start of scanning and at least one clock signal CLK1 and CLK2 controlling the output period of the gate on voltage Von. The gate control signal CONT1 may further include an output enable signal OE that defines the duration of the gate on voltage Von.

The data control signal CONT2 includes a horizontal synchronization start signal STH for notifying the start of transmission of video data to the pixel PX of one row and a load for applying a data signal to the data lines D _{1 to} D _m Signal LOAD and a data clock signal HCLK. The data control signal CONT2 is also an inverted signal which inverts the voltage polarity of the data signal with respect to the common voltage Vcom (hereinafter referred to as "the polarity of the data signal by reducing the voltage polarity of the data signal with respect to the common voltage" RVS).

The data driver 500 receives the digital video signal DAT for the pixel PX of one row and outputs the digital video signal DAT for the pixel PX in accordance with the data control signal CONT2 from the signal controller 600. [ ) To convert the digital video signal DAT into an analog data signal, and then applies the analog data signal to the corresponding data lines D ₁ -D _m .

Gate driver 400 is a signal control gate lines (G ₁ -G _n) is applied to the gate line of the gate-on voltage (Von), (G ₁ -G _n) in accordance with the gate control signal (CONT1) of from 600 The switching element Q is turned on. Then, the data signal applied to the data lines D ₁ -D _m is applied to the corresponding pixel PX through the turned-on switching element Q.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom appears as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The liquid crystal molecules have different arrangements according to the magnitude of the pixel voltage, and thus the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H &quot;, which is the same as one cycle of the horizontal synchronization signal Hsync and the data enable signal DE), so that all the gate lines G ₁ -G _n On voltage Von is sequentially applied to all the pixels PX to display an image of one frame by applying a data signal to all the pixels PX.

At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled such that the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame ( "Frame inversion"). At this time, the polarity of the data signal flowing through one data line changes (for example, row inversion and dot inversion) depending on the characteristics of the inversion signal RVS in one frame, or the polarity of the data signal applied to one pixel row is different (For example, thermal inversion, dot inversion).

Next, a driving device of the display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 to 6.

3 is a block diagram of a gate driver according to an exemplary embodiment of the present invention. FIG. 4 is an example of a circuit diagram of the j-th stage of the shift register for the gate driver shown in FIG. 3, and FIG. 5 is illustrated in FIG. 3. 6 is a graph illustrating signal waveforms of a gate driver, and FIG. 6 is a graph comparing leakage current characteristics of a transistor forming the gate driver illustrated in FIG. 3.

For convenience of description, the voltage corresponding to the high level of the clock signals CLK1 and CLK2 is equal to the gate on voltage Von and is referred to as a high voltage, and the magnitude of the voltage corresponding to the low level is the first gate off voltage. The same as Voff1 is called the first low voltage and the same as the second gate off voltage Voff2 is called the second low voltage. At this time, the first gate off voltage Voff1 is greater than the second gate off voltage Voff2. That is, the second low voltage is smaller than the first low voltage.

The gate driver 400 illustrated in FIG. 3 is a shift register including a plurality of stages 410 connected to the gate lines G ₁ -G _n , respectively, and includes scan start signals STV1 and STV2 and clock signals. CLK1 and CLK2 and first and second gate off voltages Voff1 and Voff2 are input.

Each stage 410 includes a set terminal S, a reset terminal R, first and second gate voltage terminals GV1 and GV2, an output terminal OUT, and a clock terminal CK1 and CK2. .

The gate output of the front stage [ST (j-1)], that is, the gate output Gout (j-1) of the front stage is connected to the set terminal S of each stage 410, (J + 1)] is input to the reset terminal R, and the gate output of the rear stage [ST (j + 1) (CLK1 and CLK2), respectively. An output terminal (OUT) emits a gate line (G _j) and front and rear stages [ST (j-1), ST (j + 1)] as a gate output [Gout (j)]. Alternatively, a separate output terminal for outputting a carry signal output to the front stage and rear stage ST (j-1) and ST (j + 1) may be further provided, and a buffer connected to the output terminal OUT You can have more.

In summary, each stage 410 generates a gate output in synchronization with clock signals CLK1 and CLK2 based on the front gate output Gout (j-1) and the rear gate output Gout (j + 1). .

The scan start signal STV1 is input to the first stage ST1 of the shift register 400 instead of the previous gate output and the scan start signal STV2 is input to the last stage ST do. The scan start signals STV1 and STV2 are signals of one frame period, each of which is input at the beginning and end of one frame, with a width of 1H.

The clock signals CLK1 and CLK2 have a duty ratio of about 50% and a period of 2H, and in turn have a phase difference of 180 degrees.

At this time, for example, when the clock signal CLK1 is input to the clock terminal CK1 of the j-th stage ST (j) and the clock signal CLK2 is input to the clock terminal CK2, The clock signal CLK2 is input to the clock terminal CK1 and the clock signal CK2 is input to the clock terminal CK1 of the (j + 1) -th stage ST (j-1) Is input.

4, each stage of the gate driver 400 according to an embodiment of the present invention, for example, the j-th stage, includes at least one NMOS transistor T1-T7 and capacitors C1 and C2 . However, PMOS transistors may be used instead of NMOS transistors. In addition, the capacitors C1 and C2 may actually be parasitic capacitances between the gate and the drain / source formed during the process.

The transistor T2 has a control terminal and an input terminal connected to the set terminal S and transmits the front end gate output Gout (j-1) to the contact J1.

The transistor T3 has a control terminal connected to the reset terminal R, and outputs a second gate-off voltage Voff2 to the contact J1.

The control terminals of the transistors T4 and T5 are commonly connected to the contact point J2, and the transistor T4 has the second gate-off voltage Voff2 as the contact point J1, and the transistor T5 is connected to the zero point. One gate-off voltage Voff1 is transferred to the output terminal OUT.

The transistor T6 is connected to the clock terminal CK2 and the transistor T7 is connected to the contact J1 to transfer the first gate off voltage Voff1 to the contact J2 and the output terminal OUT, respectively.

The transistor T1 has its control terminal connected to the contact J1 and transmits the clock signal CLK1 to the output terminal OUT.

The capacitor C1 is connected between the clock terminal CK1 and the contact J2 and the capacitor C2 is connected between the contact J1 and the output terminal OUT.

The j-th stage will now be described with reference to the operation of the shift register shown in Fig.

the previous stage ST (j-1) and the previous stage ST (j + 1) are connected to the clock signal CLK2 when the jth stage ST (j) generates the gate output in synchronization with the clock signal CLK1. To generate a gate output.

First, when the clock signal CLK2 and the front gate output Gout (j-1) become high, the transistors T2 and T6 are turned on. Transistor T2 then transfers a high voltage to contact J1 to turn on both transistors T1 and T7. Accordingly, the transistor T7 transfers the first low voltage to the contact point J2, and the transistor T6 transfers the first low voltage to the output terminal OUT. In addition, the transistor T1 is turned on and the clock signal CLK1 is output to the output terminal OUT. At this time, since the clock signal CLK1 is the first low voltage, the gate output Gout (j) receives the first low voltage. Keep it. At the same time, the capacitor C2 charges a voltage having a magnitude corresponding to the difference between the high voltage and the first low voltage.

At this time, since the rear stage gate output [Gout (j + 1)] is low, the input of the reset terminal R is also low. Therefore, the transistors T3, T4, and T5 to which the control terminal is connected to the reset terminal R and the contact J2 are turned off.

Subsequently, when the clock signal CLK1 goes high and the clock signal CLK2 goes low, both transistors T5 and T6 are turned off. Accordingly, the output terminal OUT is cut off from the first gate off voltage Voff and connected to the clock signal CLK1 to output a high voltage as the gate output Gout (j). At this time, the capacitor C1 is charged with a voltage corresponding to the difference between the high voltage and the first low voltage. On the other hand, one end of the capacitor C2, that is, the potential of the contact J1 rises further by a high voltage.

Subsequently, when the clock signal CLK1 goes low, since the contact J1 is in a floating state, the transistor T1 remains turned on while maintaining the previous voltage, and the output terminal OUT outputs the clock signal CLK1 that is low. do. In addition, since the transistor T7 also maintains a turn-on state, the contact J2 maintains a first low voltage.

Next, when the rear gate output Gout (j + 1) becomes high, the transistor T3 is turned on to transfer the second low voltage to the contact J1. As a result, the transistor T1 is turned off and the connection between the clock signal CLK1 and the output terminal OUT is cut off.

At the same time, since the clock signal CLK2 becomes high and the transistor T6 is turned on, the output terminal OUT and the first gate-off voltage Voff1 are connected, so that the output terminal OUT continuously emits the first low voltage. In addition, as the transistor T7 is turned off, the contact J2 is in a floating state, so the contact J2 maintains the first low voltage which is the previous voltage. At this time, the control terminal of the transistor T7 is connected to the contact J1 and the input terminal is connected to the first gate-off voltage Voff1, and the voltage between the control terminal and the input terminal, that is, the voltage Vgd between the gate and the drain. ) Has a negative value because it corresponds to a difference between the second gate off voltage and the first gate off voltage.

For this reason, as shown in the graph of FIG. 6 showing the I-V characteristics of the transistor, it can be seen that the leakage current can be significantly reduced.

That is, as in the embodiment of the present invention, when the second gate off voltage Voff2 smaller than the first gate off voltage Voff1 is connected to the input terminals of the two transistors T3 and T4, the transistors T3 and T4 are conventionally used. This can be seen by comparing the case of connecting to the first gate-off voltage.

For example, when the first gate off voltage Voff1 is -10V and the second gate off voltage Voff2 is -15V, the leakage current Il1 according to the embodiment of the present invention is applied to the conventional leakage current Il2. It is almost 100 times smaller than that. At this time, the leakage current is a current flowing from the output terminal of the transistor T7, that is, the contact J2 to the input terminal, that is, the first gate-off voltage terminal GV2, and reducing the potential certainly reduces the potential of the contact J2. Can be. Therefore, the potential of the contact J2 is increased to prevent the transistors T4 and T5 from turning on, thereby preventing the image from being displayed abnormally.

Next, when the rear gate output Gout (j + 1) and the clock signal CLK2 are low, the contacts J1 and J2 maintain the previous voltage in the floating state. At this time, since one end of the capacitor C1 is connected to the clock signal CLK1, the potential of the floating contact J2 changes in accordance with the level of the clock signal CLK1.

Thereafter, the output terminal OUT is connected to the first gate-off voltage Voff1 through the transistor T5 when the high voltage of the contact point J2 becomes high, that is, when the clock signal CLK1 is high, and the clock signal CLK2 is When it is high, it is connected to the first gate off voltage Voff1 through the transistor T6.

In this manner, after the gate output is generated from the first stage ST1 to the last stage ST (n), the scan start signal STV2 is supplied to the reset terminal R of the last stage ST (n) The operation for one frame is completed.

As described above, the two transistors T3 and T4 are connected to the second gate off voltage Voff2 lower than the first gate off voltage Voff1 to make the gate-drain voltage of the transistor T7 negative. The leakage current of J2) can be reduced. Thus, the two transistors T4 and T5 can be operated correctly to prevent the screen from being displayed abnormally.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of the right.

Claims (14)

1. A driving apparatus for a display apparatus including a plurality of stages connected to each other, Each stage includes a plurality of transistors and a capacitor, Each stage receives a scan start signal, a plurality of clock signals, and first and second gate off voltages Voff1 and Voff2. Some of the transistors are connected to the first gate off voltage, some of the transistors are connected to the second gate off voltage, Each stage may include a first gate voltage terminal receiving the first gate off voltage, a second gate voltage terminal receiving the second gate off voltage, an output terminal outputting a gate signal, and a plurality of clock signals. Has a first clock terminal for receiving one clock signal, The plurality of transistors and capacitors A first transistor connected between the first clock terminal and the output terminal and having a control terminal connected to a first contact point; A fourth transistor connected between the first contact point and the second gate voltage terminal, and a control terminal connected to the second contact point; and A seventh transistor connected between the second contact point and the first gate voltage terminal and a control terminal is connected to the first contact point Including, A voltage varying according to the level of the first clock signal is applied to an output terminal of the seventh transistor connected to the second contact point. Drive device for display device. In claim 1, And the second gate off voltage is less than the first gate off voltage. In claim 1, Each stage further includes a set terminal, a reset terminal, and a second clock terminal configured to receive a second clock signal different from the first clock signal; The plurality of transistors and capacitors A second transistor in which a control terminal and an input terminal are commonly connected to the set terminal, and an output terminal is connected to the first contact point; A third transistor connected between the first contact point and the second gate voltage terminal and having a control terminal connected to the reset terminal; A fifth transistor connected between the output terminal and the first gate voltage terminal and having a control terminal connected to the second contact point; A sixth transistor connected between the output terminal and the first gate voltage terminal, and a control terminal connected to the second clock terminal; A first capacitor connected between the first clock terminal and the second contact, and A second capacitor connected between the first contact and the output terminal Further comprising Drive device for display device. 4. The method of claim 3, The first gate off voltage is input to the first gate voltage terminal, and the second gate off voltage is input to the second gate voltage terminal. In claim 4, And the second gate off voltage is less than the first gate off voltage. The method of claim 5, The first gate off voltage is -10V, and the second gate off voltage is -15V. In claim 1, Wherein the stage is integrated in the display device. 1. A driving apparatus for a display apparatus including a plurality of stages connected to each other, Each stage A plurality of transistors and capacitors, Each stage receives a scan start signal, a plurality of clock signals, and first and second gate off voltages Voff1 and Voff2. Some of the transistors are connected to the first gate off voltage, some of the transistors are connected to the second gate off voltage, Each stage may include a first gate voltage terminal receiving the first gate off voltage, a second gate voltage terminal receiving the second gate off voltage, an output terminal outputting a gate signal, and a plurality of clock signals. Has a first clock terminal for receiving one clock signal, The plurality of transistors and capacitors A first transistor connected between the first clock terminal and the output terminal and having a control terminal connected to a first contact point; A fourth transistor connected between the first contact point and the second gate voltage terminal, and a control terminal connected to the second contact point; and A seventh transistor connected between the second contact point and the first gate voltage terminal and a control terminal is connected to the first contact point Including, The gate output of the previous stage is input to the output terminal of the fourth transistor. Drive device for display device. In claim 8, And the second gate off voltage is less than the first gate off voltage. In claim 8, Each stage further includes a set terminal, a reset terminal, and a second clock terminal configured to receive a second clock signal different from the first clock signal; The plurality of transistors and capacitors A second transistor in which a control terminal and an input terminal are commonly connected to the set terminal, and an output terminal is connected to the first contact point; A third transistor connected between the first contact point and the second gate voltage terminal and having a control terminal connected to the reset terminal; A fifth transistor connected between the output terminal and the first gate voltage terminal and having a control terminal connected to the second contact point; A sixth transistor connected between the output terminal and the first gate voltage terminal, and a control terminal connected to the second clock terminal; A first capacitor connected between the first clock terminal and the second contact, and A second capacitor connected between the first contact and the output terminal The driving device of the display device further comprising. In claim 10, The first gate off voltage is input to the first gate voltage terminal, and the second gate off voltage is input to the second gate voltage terminal. 12. The method of claim 11, And the second gate off voltage is less than the first gate off voltage. The method of claim 12, The first gate off voltage is -10V, and the second gate off voltage is -15V. In claim 8, Wherein the stage is integrated in the display device.

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