KR101016739B1 - Shift register - Google Patents

Abstract

The present invention provides a shift resistor that can prevent a malfunction of an amorphous-silicon thin film transistor due to a gate bias stress.

To this end, the shift register of the present invention shifts a start pulse input by using the first and second driving voltages and the first and second clock signals, and supplies a plurality of output signals to the respective output signals and the next stage start pulses. In a shift register consisting of stages, each of the stages supplies the first clock signal to an output line under control of a first node and supplies the second driving voltage under control of a second node and a third node. An output buffer section for supplying an output line; A first node controller for controlling the first node by controlling the second clock signal; A second node controller selectively supplying a voltage of a fourth node and the second driving voltage to the second node by controlling the first and second clock signals; A third node controller configured to supply the voltage of the fourth node and the second driving voltage to the third node so as to be opposite to the second node by controlling the first and second clock signals; And a fourth node controller configured to control the fourth node by controlling the first and second clock signals.

Description

Shift register {SHIFT REGISTER}             

1 is a block diagram showing a conventional two-phase shift register.

FIG. 2 is a detailed circuit diagram of the first stage shown in FIG. 1. FIG.

3 is a drive waveform diagram of the stage shown in FIG.

4 is a detailed circuit diagram of one stage of a shift register according to an embodiment of the present invention.

FIG. 5 is a drive waveform diagram of the stage shown in FIG. 4; FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of a liquid crystal display device, and more particularly to a shift register using an amorphous-silicon thin film transistor.

A liquid crystal display device used as a display device of a television and a computer displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area provided at the intersection of the gate lines and the data lines. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines.

The driving circuit includes a gate driver for driving the gate lines and a data driver for driving the data lines. The gate driver sequentially supplies scan signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel. The data driver supplies a video signal to each of the data lines whenever a scan signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the video signal for each liquid crystal cell.

In this driving circuit, the gate driver generates a scan signal for sequentially driving the gate lines using the shift register. The data driver generates a sampling signal for sequentially sampling the video signal input from the outside by a predetermined unit using the shift register.

FIG. 1 is a block diagram showing a general two-phase shift register, in which the shift register shown in FIG. 1 has first to nth stages connected in cascade.

First and second clock signals C1 and C2 are commonly supplied to the first to nth stages together with the high potential and high potential driving voltages (not shown), and the output signal of the start pulse Vst or the previous stage is Supplied. The first stage outputs the first output signal Out1 in response to the start pulse Vst and the first and second clock signals C1 and C2. The second through n-th stages output the second through n-th output signals Out2 through Outn in response to the output signal of the previous stage and the first and second clock signals C1 and C2. These first to nth stages have the same circuit configuration and sequentially shift the specific voltage of the start pulse Vst. The first to n th output signals Out1 to Outn are supplied as scan signals for sequentially driving the gate lines of the liquid crystal panel, or as sampling signals for sequentially sampling the video signals in the data driver.

FIG. 2 shows a detailed circuit configuration of one stage shown in FIG. 1.

The stage shown in FIG. 2 outputs the fifth NMOS transistor T5 outputting the first clock signal C1 to the output line under the control of the Q node, and the low potential driving voltage VSS under the control of the QB node. The sixth NMOS transistor T6 output to the line and the first to fourth NMOS transistors T1 to T4 for controlling the Q node and the QB node are provided.

The high potential and low potential voltages VDD and VSS are supplied to the stage, and the start pulse Vst and the first and second clock signals C1 and C2 are supplied as shown in FIG. 3. Here, the high and low state voltages having a constant pulse width are alternately supplied to the second clock signal C2, and a voltage opposite to the second clock signal C2 is supplied to the first clock signal C1. . Here, the high state of the start pulse Vst is synchronized with any one of the high states supplied to the second clock signal C2. The start pulse Vst is supplied from the outside or the output signal of the previous stage is supplied. Hereinafter, an operation process of the stage will be described with reference to the driving waveform shown in FIG. 3.

In the period A, the first NMOS transistor T1 is turned on by the second clock signal C2 in the high state so that the high state voltage of the start pulse Vst is supplied to the Q node, that is, precharged. The fifth NMOS transistor T5 is turned on by the high state voltage precharged to the Q node to supply the low state voltage of the first clock signal C1 to the output line. At this time, the second NMOS transistor T2 is also turned on by the second clock signal C2 in the high state to supply the high potential driving voltage VDD to the QB node, and the high potential driving voltage supplied to the QB node ( The sixth NMOS transistor T6 is also turned on by VDD to supply the low potential driving voltage VSS. Accordingly, in the period A, the output line of the stage outputs the output signal OUT in the low state.

The fifth NMOS transistor T5 remains turned on because the first NMOS transistor T1 is turned off by the second clock signal C2 in the low period B, so that the Q node floats to a high state. . At this time, the Q node floated as the high voltage is supplied to the first clock signal C1 due to the influence of the internal capacitor Cgs and the capacitor CB formed between the gate and the drain of the fifth NMOS transistor T5. Bootstrapping. As a result, the Q-node voltage further increases to ensure that the fifth NMOS transistor T5 is turned on reliably so that the high voltage of the first clock signal C1 is quickly supplied to the output line. The fourth NMOS transistor T4 is turned on by the Q node floated to the high state, and the third NMOS transistor T3 is turned on by the first clock signal C1 in the high state to drive the low potential to the QB node. Since the voltage VSS is supplied, the sixth NMOS transistor T6 is turned off. Accordingly, in the period B, the output line of the stage outputs the output signal OUT in the high state.

In the period C, the first NMOS transistor T1 is turned on by the second clock signal C2 in the high state so that the low state voltage of the start pulse Vst is supplied to the Q node. Is turned off. At this time, since the second NMOS transistor T2 is turned on by the second clock signal C2 in the high state and the high potential driving voltage VDD is supplied to the QB node, the sixth NMOS transistor T6 is turned on. The low potential driving voltage VSS is output to the output line. At this time, the third NMOS transistor T3 is turned off by the first clock signal C1 in the low state, and the fourth NMOS transistor T4 is turned off by the Q node in the low state and is high in the QB node. The above driving voltage VDD is maintained. Accordingly, in the period C, the output line of the stage outputs the output signal OUT in the low state.

In the period D, the second NMOS transistor T2 is turned off by the second clock signal C2 in the low state, and the fourth NMOS transistor T4 is turned off by the Q node in the low state. Even when the third NMOS transistor T3 is turned on by the first clock signal C1 having a high state, the third NMOS transistor T3 is floated while maintaining the high potential driving voltage VDD supplied in the previous period C. Accordingly, the sixth NMOS transistor T6 maintains the turn-on state and outputs the low potential driving voltage VSS to the output line. As a result, in the D period, the output line of the stage outputs the output signal OUT in the low state.

In the remaining periods, since the C and D periods are alternately repeated, the output signal OUT of the stage is kept low.

Recently, many attempts have been made to apply a poly-silicon thin film transistor technology capable of directly forming a shift resistor on a glass substrate to an amorphous-silicon amorphous thin film transistor technology. However, amorphous-silicon thin film transistors have a bias temperature stress characteristic that causes malfunction due to bias stress when a direct current (DV) voltage is continuously supplied to a gate terminal during high temperature operation.

However, in the conventional shift register, as shown in FIG. 3, the high potential is applied to the QB node which is the gate node of the sixth NMOS transistor T6 for most of the period (that is, the Q node is in the high state except the 1H or 2H period). It can be seen that the driving voltage VDD is applied in the form of direct current. Accordingly, the conventional shift register has a problem in that the sixth NMOS transistor T6 malfunctions due to a gate bias stress when operating at a high temperature.

Accordingly, an object of the present invention is to provide a shift resistor capable of preventing malfunction of an amorphous-silicon thin film transistor due to a gate bias stress.

In order to achieve the above object, the shift register according to an exemplary embodiment of the present invention shifts a start pulse input by using first and second driving voltages and first and second clock signals, thereby outputting each output signal and a next stage. A shift register comprising a plurality of stages for supplying start pulses of a plurality of stages, wherein each of the stages supplies the first clock signal to an output line under control of a first node, and controls the second and third nodes. An output buffer unit to supply the second driving voltage to the output line; A first node controller for controlling the first node by controlling the second clock signal; A second node controller selectively supplying a voltage of a fourth node and the second driving voltage to the second node by controlling the first and second clock signals; A third node controller configured to supply the voltage of the fourth node and the second driving voltage to the third node so as to be opposite to the second node by controlling the first and second clock signals; And a fourth node controller configured to control the fourth node by controlling the first and second clock signals.

The first and second clock signals are phase inverted.

The first and second clock signals are alternately supplied to the plurality of stages.

The first driving voltage is higher than the second driving voltage.

The first node controller includes a first transistor connected between the input line of the start pulse and the first node and controlled by the second clock signal.

The fourth node controller includes a second transistor connected between an input line of the first driving voltage and a fourth node and controlled by the second clock signal, and connected in parallel with the second transistor to the first clock signal. A third transistor controlled by the; And a fourth transistor connected between the fourth node and the input line of the second driving voltage and controlled by the first node.

The output buffer unit includes a fifth transistor connected between an input line of the first clock signal and an output line of the stage and controlled by the first node; A sixth transistor connected between an output line of the stage and an input line of the second driving voltage and controlled by the second node; And a seventh transistor connected in parallel with the sixth transistor and controlled by the third node.

The output buffer section is further provided with a capacitor connected to the fifth transistor to bootstrap the first node using any one clock signal.

The second node controller is connected between the fourth node and the second node and is controlled between the eighth transistor controlled by the first clock signal, the input line of the second driving voltage, and the second node. And a ninth transistor controlled by the second clock signal.

The third node controller is connected between the fourth node and the third node and is controlled between the tenth transistor controlled by the second clock signal, the input line of the second driving voltage, and the third node. And an eleventh transistor controlled by the first clock signal.                     

The stage is composed of transistors of the same channel type.

delete

The stage is composed of NPMOS transistors.

The stage is composed of amorphous-silicon thin film transistors.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 4 and 5.

4 is a detailed circuit diagram of any one of a plurality of stages that are cascaded in a shift register according to an exemplary embodiment of the present invention, and FIG. 5 is a driving waveform diagram thereof.

The stage shown in FIG. 4 includes a fifth NMOS transistor T5 outputting the first clock signal C1 to the output line under the control of the Q node, and a low potential driving voltage VSS under the control of the QB1 and QB1 nodes. An output buffer having sixth and seventh NMOS transistors T6 and T7 for outputting the signal to an output line; A Q node controller having a first NMOS transistor T1 for controlling the Q node; A QB node control unit including second to fourth NMOS transistors T2, T3, and T4 for controlling the QB node; QB1 node control unit including eighth and ninth NMOS transistors T8 and T9 for controlling the QB1 node, and QB2 node control unit including tenth and eleventh NMOS transistors T10 and T11 for controlling the QB2 node. do.                     

The fifth NMOS transistor T5 of the output buffer is connected between the first clock signal C1 input line and the output line of the stage and controlled by the Q node, and the sixth and seventh NMOS transistors T6 and T7 are staged. It is connected in parallel between the output line and the low potential drive voltage (VSS) input line, and is controlled by the QB1 and QB2 nodes, respectively.

The first NMOS transistor T1 of the Q node is connected between the input line of the start pulse Vst and the Q node and controlled by the second clock signal C2.

The second NMOS transistor T2 of the QB node controller is connected between the high potential drive voltage VDD supply line and the QB node and controlled by the second clock signal, and the third NMOS transistor T3 is connected to the second NMOS transistor (T2). It is connected in parallel with T2 and controlled by the first clock signal C1, and the fourth NMOS transistor T4 is connected between the QB node and the input line of the low potential driving voltage VSS and controlled by the Q node.

The eighth NMOS transistor T8 of the QB1 node controller is connected between the QB node and the QB1 node and controlled by the first clock signal C1, and the ninth NMOS transistor T9 is a low potential driving voltage VSS input line. And is connected between the QB1 node and controlled by the second clock signal C2.

The tenth NMOS transistor T10 of the QB2 node controller is connected between the QB node and the QB2 node and controlled by the second clock signal C1, and the eleventh NMOS transistor T11 is connected to the low potential driving voltage VSS input line. Is connected between the and QB2 nodes and controlled by the second clock signal C2.

The capacitor CB connected between the Q node and the input line of the low potential driving voltage VSS, and the capacitor CQB connected between the QB node and the input line of the low potential driving voltage VSS are the Q node and the QB node. Remove noise from

The high potential and low potential voltages VDD and VSS are supplied to the stage, the start pulse Vst is supplied as shown in FIG. 5, and the first and second clock signals C1 and C2 are supplied. The high and low state voltages having a constant pulse width are alternately supplied to the first clock signal C1, and the voltage inverted in phase with the first clock signal C1 is supplied to the second clock signal C2. . Here, the high state of the start pulse Vst is synchronized with any one of the high states supplied to the second clock signal C2. The start pulse Vst is supplied from the outside or the output signal of the previous stage is supplied.

Hereinafter, an operation process of the stage will be described with reference to the driving waveform shown in FIG. 5.

In the period A, the first NMOS transistor T1 is turned on by the high start pulse Vst to supply the high potential driving voltage VDD to the Q node, and is precharged to the Q node high state. The fifth NMOS transistor T5 is turned on by the Q node precharged to the high state to supply the low state voltage of the first clock signal C1 to the output line. At this time, the high potential supply voltage VDD is supplied to the QB node through the second NMOS transistor T2 turned on by the second clock signal C2. Then, the ninth and tenth NMOS transistors T9 and T10 are turned on by the second clock signal C2, so that the low potential driving voltage VSS is supplied to the QB1 node and the QB node is supplied to the QB2 node. The above driving voltage VDD is supplied. Accordingly, the seventh NMOS transistor T7 is turned on to supply the low potential driving voltage VSS to the output line. As a result, in the period A, the output line of the stage outputs an output signal Out in a low state.

In the period B, the first NMOS transistor T1 is turned off by the second clock signal C2 in the low state, so that the Q node floats to the high state so that the fifth NMOS transistor T5 remains turned on. . At this time, the Q node floated as the high voltage is supplied to the first clock signal C1 due to the influence of the internal capacitor Cgs and the capacitor CB formed between the gate and the drain of the fifth NMOS transistor T5. Bootstrapping. As a result, the Q node voltage is further increased to ensure that the fifth NMOS transistor T5 is turned on reliably, so that the high voltage of the first clock signal C1 is quickly supplied to the output line. At this time, the third NMOS transistor T3 is turned on by the first clock signal C1, and the fourth PMOS transistor T4 is turned on by the bootstrapped Q node to be turned low in the QB node. . Then, the eighth and eleventh NMOS transistors T8 and T11 are turned on by the first clock signal C1, so that the low potential driving voltage VSS supplied to the QB node is low at the QB1 node, and low at the QB2 node. The potential driving voltage VSS is supplied. Accordingly, the sixth and seventh NMOS transistors T6 and T7 are turned off. As a result, in the period B, the output line of the stage outputs the output signal Out in the high state.

In the C period, the first NMOS transistor T1 is turned on by the second clock signal C2 in the high state, and is supplied to the Q node to the low voltage of the start pulse Vst, so that the fifth NMOS transistor T5 is supplied. Is turned off. At this time, the second NMOS transistor T2 is turned on by the second clock signal C2 and the high potential driving voltage VDD is supplied to the QB node. Then, the ninth and tenth NMOS transistors T9 and T10 are turned on by the second clock signal C2, so that the low potential driving voltage VSS is supplied to the QB1 node and the QB node to the QB2 node. The high potential drive voltage VDD is supplied. Accordingly, the seventh NMOS transistor T7 is turned on to supply the low potential driving voltage VSS to the output line. As a result, in the period C, the output line of the stage outputs the output signal Out in the low state.

In the period D, the first and second NMOS transistors T1 and T2 are turned off by the second clock signal C2 in the low state. Accordingly, the fifth NMOS transistor T5 is turned off because the Q node floats to the previous low state. At this time, the third NMOS transistor T3 is turned on by the first clock signal C1 in the high state, and the high potential driving voltage VDD is supplied to the QB node. The eighth and eleventh NMOS transistors T9 are turned on by the first clock signal C1, so that the high potential driving voltage VDD supplied to the QB node is supplied to the QB1 node, and the low potential driving is performed to the QB2 node. The voltage VSS is supplied. Accordingly, the sixth NMOS transistor T6 is turned on to supply the low potential driving voltage VSS to the output line. As a result, in the period B, the output line of the stage outputs an output signal Out in a low state.

In the remaining periods, the stage operates in the same manner as the C and D periods, so that the output signal OUT of the stage is kept low.

As described above, the shift register according to the present invention connects the seventh NMOS transistor T7 operating in parallel to the sixth NMOS transistor T6 at the stage, and connects the gate nodes QB1 and QB2 nodes to the first and second nodes. AC drive in accordance with the clock signal. Accordingly, since the DC bias is not applied to the gate nodes of the sixth and seventh NMOS transistors T6 and T7, the sixth and seventh NMOS transistors T6 and T7 malfunction due to the gate bias stress during high temperature driving. I can prevent it

As described above, the shift register according to the present invention parallels the seventh NMOS transistor T7 operating in opposition to the sixth NMOS transistor T6 which supplies the low potential driving voltage VSS to the output line for most of the period. Connect. In addition, AC driving is performed according to the gate node first and second clock signals of the sixth and seventh NMOS transistors T6 and T7. Accordingly, since the DC bias is not applied to the gate nodes of the sixth and seventh NMOS transistors T6 and T7, the sixth and seventh NMOS transistors T6 and T7 malfunction due to the gate bias stress during high temperature driving. It can be prevented.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (14)

A shift register comprising a plurality of stages for shifting a start pulse input by using a first and a second driving voltage and a first and a second clock signal to supply each output signal and a start pulse of a next stage, Each of the stages An output buffer unit supplying the first clock signal to an output line under control of a first node, and supplying the second driving voltage to the output line under control of second and third nodes; A first node controller for controlling the first node by controlling the second clock signal; A second node controller selectively supplying a voltage of a fourth node and the second driving voltage to the second node by controlling the first and second clock signals; A third node controller configured to supply the voltage of the fourth node and the second driving voltage to the third node so as to be opposite to the second node by controlling the first and second clock signals; And a fourth node controller for controlling the fourth node by controlling the first and second clock signals. The method of claim 1, And the first and second clock signals are phase inverted. The method of claim 1, And the first and second clock signals are alternately supplied to the plurality of stages. The method of claim 1, And the first driving voltage is higher than the second driving voltage. The method according to any one of claims 1 to 4, The first node controller is And a first transistor connected between the input line of the start pulse and the first node and controlled by the second clock signal. The method of claim 5, The fourth node controller is A second transistor connected between an input line of the first driving voltage and a fourth node and controlled by the second clock signal; A third transistor connected in parallel with the second transistor and controlled by the first clock signal; And a fourth transistor connected between the fourth node and an input line of the second driving voltage and controlled by the first node. The method of claim 6, The output buffer unit A fifth transistor connected between an input line of the first clock signal and an output line of the stage and controlled by the first node; A sixth transistor connected between an output line of the stage and an input line of the second driving voltage and controlled by the second node; And a seventh transistor connected in parallel with the sixth transistor and controlled by the third node. The method of claim 7, wherein The output buffer unit And a capacitor connected to the fifth transistor for bootstrapping the first node using any one clock signal. The method of claim 6, The second node controller An eighth transistor connected between the fourth node and the second node and controlled by the first clock signal; And a ninth transistor connected between the input line of the second driving voltage and the second node and controlled by the second clock signal. The method of claim 9, The third node controller A tenth transistor connected between the fourth node and the third node and controlled by the second clock signal; And an eleventh transistor connected between the input line of the second driving voltage and the third node and controlled by the first clock signal. delete The method of claim 1, And the stage comprises a transistor of the same channel type. The method of claim 1, And said stage comprises an NPMOS transistor. The method of claim 1, And said stage comprises an amorphous silicon silicon transistor.

Images