CN111508415B - Grid array substrate driving circuit - Google Patents
Grid array substrate driving circuit Download PDFInfo
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- CN111508415B CN111508415B CN202010352611.8A CN202010352611A CN111508415B CN 111508415 B CN111508415 B CN 111508415B CN 202010352611 A CN202010352611 A CN 202010352611A CN 111508415 B CN111508415 B CN 111508415B
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- 239000000758 substrate Substances 0.000 title claims abstract description 79
- 239000010409 thin film Substances 0.000 claims description 195
- 239000003990 capacitor Substances 0.000 claims description 19
- 238000012795 verification Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000001808 coupling effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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Abstract
The invention provides a grid array substrate driving circuit which comprises a plurality of grid array substrate driving units which are connected in series, wherein each grid array substrate driving unit also comprises a first grid array substrate driving subunit with a first signal source and a second grid array substrate driving subunit with a second signal source. The first gate array substrate driving subunit operates when the first signal source transmits a first signal having a high level voltage, and the second gate array substrate driving subunit operates when the first signal source transmits the first signal having a low level voltage.
Description
Technical Field
The invention relates to the technical field of display, in particular to a grid array substrate driving circuit.
Background
With the development of Gate On Array (GOA) technology, Gate driving circuits connected to scan lines can be fabricated around the display area on the substrate by the original process of fabricating the display panel, instead of completing the Gate driving of the scan lines by an external integrated circuit. The gate array substrate technology not only reduces the binding of the external integrated circuit to reduce the production cost, but also becomes a key technology for manufacturing narrow-frame or frameless display products.
In order to meet the market demand, a plurality of gate array substrate driving subunits are often required to be verified, but if the gate array substrate driving subunits are to be verified, the gate array substrate driving subunits are often required to be rearranged or an experimental mask is required to be added for verification, so that the verification cost for verifying the gate array substrate driving subunits is increased, and the verification opportunity is indirectly reduced.
Therefore, it is necessary to provide a gate array substrate driving circuit to improve the chances of verifying the plurality of gate array substrate driving sub-units and reduce the verification cost.
Disclosure of Invention
The present invention provides a gate array substrate driving circuit to improve the chances of verifying a plurality of gate array substrate driving sub-units and reduce the verification cost.
In order to achieve the above object, an aspect of the present invention provides a gate array substrate driving circuit, including a plurality of gate array substrate driving units connected in series, and an nth stage gate array substrate driving unit transmitting a signal to an nth stage scanning line corresponding to the nth stage gate array substrate driving unit, each gate array substrate driving unit including:
the first grid array substrate driving subunit comprises a first signal source, a first bridging thin film transistor, a second bridging thin film transistor and a third bridging thin film transistor, wherein the first signal source is used for transmitting a first signal to a corresponding scanning line; and
a second gate array substrate driving subunit, including a second signal source, connected to the first bridging thin film transistor, the second bridging thin film transistor, and the third bridging thin film transistor, the second signal source being configured to transmit a second signal to the corresponding scan line;
wherein the first gate array substrate driving subunit operates when the first signal source transmits the first signal having a high level voltage, and the second gate array substrate driving subunit operates when the first signal source transmits the first signal having a low level voltage.
Further, the first gate array substrate driving subunit includes:
a first thin film transistor having a source terminal and a gate terminal connected to a constant high level voltage, and a drain terminal connected to a first signal node and a gate terminal of the first bridge thin film transistor;
a second thin film transistor having a source terminal connected to a constant low level voltage, a gate terminal connected to the first signal source, the gate terminal of the second bridging thin film transistor, and the source terminal of the third bridging thin film transistor, and a drain terminal connected to the first signal node, the drain terminal of the first thin film transistor, and the gate terminal of the first bridging thin film transistor;
a source terminal and a drain terminal of the first bridging thin film transistor are connected with the second grid array substrate driving subunit, and a grid terminal of the first bridging thin film transistor is connected with the first signal node, the drain terminal of the first thin film transistor and the drain terminal of the second thin film transistor;
a source end of the second bridging thin film transistor is connected with the second grid array substrate driving subunit, a grid end of the second bridging thin film transistor is connected with the first signal source, a grid end of the second thin film transistor and a source end of the third bridging thin film transistor, and a drain end of the second bridging thin film transistor is connected with a grid end of the third bridging thin film transistor; and
and the source terminal of the third bridging thin film transistor is connected with the first signal source, the grid terminal of the second thin film transistor and the grid terminal of the second bridging thin film transistor, the grid terminal of the third bridging thin film transistor is connected with the drain terminal of the second bridging thin film transistor, and the drain terminal of the third bridging thin film transistor is connected with the second grid array substrate driving subunit and the corresponding scanning line.
Further, when the first signal source transmits the first signal with a high level voltage, the first bridging thin film transistor is in an off state, and the second bridging thin film transistor is in an on state.
Further, when the second signal source transmits the second signal having a high level voltage, the first signal received by the corresponding scan line has a stronger level signal than when the second signal source transmits the second signal having a low level voltage.
Further, when the first signal source transmits the first signal with a low level voltage, the first bridging thin film transistor is in an on state, and the second bridging thin film transistor is in an off state.
Further, when the second signal source transmits the second signal with a low level voltage, the corresponding scan line and the second signal source are in a conducting state.
Further, when the second signal source transmits the second signal having a high level voltage, the corresponding scan line receives the second signal having a high level voltage.
Further, the second gate array substrate driving subunit includes:
a third thin film transistor having a source terminal and a gate terminal connected to the Mth level start voltage, and a drain terminal connected to the second signal node and the source terminal of the second bridge thin film transistor;
a fourth thin film transistor, a source terminal of which is connected to the second signal source and the source terminal of the first bridging thin film transistor, a gate terminal of which is connected to the second signal node, a drain terminal of the third thin film transistor, and the source terminal of the second bridging thin film transistor, and a drain terminal of which is connected to the nth stage start voltage;
a bootstrap capacitor having a first terminal connected to the second signal node, the drain terminal of the third thin film transistor, the gate terminal of the fourth thin film transistor, and the source terminal of the second bridge thin film transistor, and a second terminal connected to the drain terminal of the fourth thin film transistor and the nth-stage start voltage;
a fifth thin film transistor having a source terminal connected to the constant low level voltage, a gate terminal connected to the P-th stage start voltage, and a drain terminal connected to the drain terminal of the third thin film transistor, the second signal node, the first terminal of the bootstrap capacitor, the gate terminal of the fourth thin film transistor, and the source terminal of the second bridge thin film transistor;
a sixth thin film transistor, a source terminal of which is connected to the constant low level voltage and the source terminal of the fifth thin film transistor, a gate terminal of which is connected to the gate terminal of the fifth thin film transistor and the P-th stage start voltage, and a drain terminal of which is connected to the drain terminal of the fourth thin film transistor, the second terminal of the bootstrap capacitor, and the N-th stage start voltage;
a seventh thin film transistor, a source terminal of which is connected to the constant low level voltage, the source terminal of the fifth thin film transistor, and the source terminal of the sixth thin film transistor, a gate terminal of which is connected to the gate terminal of the fifth thin film transistor, the P-th level start voltage, and the gate terminal of the sixth thin film transistor, and a drain terminal of which is connected to the drain terminal of the third bridging thin film transistor and the corresponding scan line; and
a source terminal of the eighth thin film transistor is connected to the drain terminal of the first bridging thin film transistor, a gate terminal of the eighth thin film transistor is connected to the gate terminal of the fourth thin film transistor, the first terminal of the bootstrap capacitor, the second signal node, the drain terminal of the third thin film transistor, the drain terminal of the fifth thin film transistor, and the source terminal of the second bridging thin film transistor, and the drain terminal of the eighth thin film transistor is connected to the drain terminal of the third bridging thin film transistor, the corresponding scan line, and the drain terminal of the seventh thin film transistor;
wherein M and P are natural numbers smaller and larger than N respectively.
Further, when the second signal source transmits the second signal having a low level voltage, the nth stage start voltage is a low level voltage, and the mth stage start voltage and the pth stage start voltage are high level voltages.
Further, when the second signal source transmits the second signal having a high level voltage, the nth stage start voltage is the high level voltage, and the mth stage start voltage and the pth stage start voltage are low level voltages.
The present invention controls the switching of two different gate array substrate driving subunits according to the level voltage of the first signal transmitted by the first signal source, that is, when the first signal source transmits the first signal with high level voltage, the first gate array substrate driving subunit operates (transmits the first signal to the corresponding scan line), and when the first signal source transmits the first signal with low level voltage, the second gate array substrate driving subunit operates (transmits the second signal to the corresponding scan line). Compared with the prior art, the invention has the advantages of improving the opportunity of verifying the driving subunits of the grid array substrates and reducing the verification cost.
Drawings
Fig. 1 is a schematic view of a gate array substrate driving unit according to an embodiment of the invention.
FIG. 2A is a timing diagram illustrating a first signal source with a high level voltage according to an embodiment of the invention.
FIG. 2B is a timing diagram illustrating a low level voltage of the first signal source according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The following description of the various embodiments refers to the accompanying drawings, which illustrate embodiments of the invention and which are set forth in part in the description. The directional terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention.
Referring to fig. 1, fig. 1 is a schematic view of a gate array substrate driving unit according to an embodiment of the invention. The gate array substrate driving circuit includes a plurality of gate array substrate driving units connected in series, and the nth stage gate array substrate driving unit transmits signals (including a first signal and a second signal described below) to the nth stage scanning line g (N) corresponding thereto. For convenience of description, the nth-stage gate array substrate driving unit is used in the embodiments of the present invention for description, and therefore "the corresponding scan line g (N)" refers to "the nth-stage scan line g (N)", "the first signal source S1" refers to "the nth-stage first signal source S1 (N)", and "the second signal source S2" refers to "the nth-stage second signal source S2 (N)", which are not described herein unless otherwise specified.
Further, each gate array substrate driving unit further includes a first gate array substrate driving subunit 10 and a second gate array substrate driving subunit 20, wherein the first gate array substrate driving subunit 10 includes a first signal source S1, a first bridging thin film transistor Tb1, a second bridging thin film transistor Tb2, and a third bridging thin film transistor Tb3, and the first signal source S1 is configured to transmit a first signal to a corresponding scan line g (n); the second gate array substrate driving sub-unit 20 includes a second signal source S2 (e.g. a clock signal), and the second gate array substrate driving sub-unit 20 is connected to the first bridging tft Tb1, the second bridging tft Tb2 and the third bridging tft Tb3 (described later), and the second signal source S2 is used for transmitting a second signal to the corresponding scan line g (n).
Specifically, the first gate array substrate driving subunit 10 includes a first thin film transistor T1, a second thin film transistor T2, the first bridging thin film transistor Tb1, the second bridging thin film transistor Tb2, and the third bridging thin film transistor Tb 3.
Further, a source terminal and a gate terminal of the first thin film transistor T1 are connected to a constant high level voltage VGH, and a drain terminal is connected to a first signal node k (n), a drain terminal of the second thin film transistor T2, and a gate terminal of the first bridging thin film transistor Tb 1; a source terminal of the second thin film transistor T2 is connected to a constant low level voltage VSS, a gate terminal is connected to the first signal source S1, a gate terminal of the second bridging thin film transistor Tb2, and a source terminal of the third bridging thin film transistor Tb3, and a drain terminal is connected to the first signal node k (n), a drain terminal of the first thin film transistor T1, and a gate terminal of the first bridging thin film transistor Tb 1; a source terminal and a drain terminal of the first bridging tft Tb1 are connected to the second gate array substrate driving subunit 20 (specifically, the source terminals are connected to the second signal source S2 and the source terminal of the fourth tft T4, and the drain terminal is connected to the source terminal of the eighth tft T8), and the gate terminal is connected to the first signal node k (n), the drain terminal of the first tft T1, and the drain terminal of the second tft T2; a source terminal of the second bridging tft Tb2 is connected to the second gate array substrate driving subunit 20 (specifically, connected to a drain terminal of a fifth tft T5, a drain terminal of a third tft T3, a second signal node q (n), a first terminal of a bootstrap capacitor Cb, a gate terminal of a fourth tft T4, and a gate terminal of an eighth tft T8), a gate terminal of the second bridging tft Tb2 is connected to the first signal source S1, the gate terminal of the second tft T2, and a source terminal of the third bridging tft Tb3, and a drain terminal of the third bridging tft Tb3 is connected to the gate terminal of the third bridging tft Tb 4; the source terminal of the third bridging tft Tb3 is connected to the first signal source S1, the gate terminal of the second tft T2, and the gate terminal of the second bridging tft Tb2, the gate terminal is connected to the drain terminal of the second bridging tft Tb2, and the drain terminal is connected to the first gate array substrate driving subunit 20 (specifically, to the drain terminal of the seventh tft T7 and the drain terminal of the eighth tft T8) and the corresponding scan line g (n).
Specifically, the second gate array substrate driving sub-unit 20 further includes a third thin film transistor T3, a fourth thin film transistor T4, a bootstrap capacitor Cb, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7, and an eighth thin film transistor T8.
Further, a source terminal and a gate terminal of the third thin film transistor T3 are connected to the mth stage start voltage st (M), and a drain terminal is connected to the second signal node q (n), the first terminal of the bootstrap capacitor Cb, the gate terminal of the fourth thin film transistor T4, the gate terminal of the eighth thin film transistor T8, the source terminal of the second bridge thin film transistor Tb2, and the drain terminal of the fifth thin film transistor T5; a source terminal of the fourth thin film transistor T4 is connected to the second signal source S2 and a source terminal of the first bridging thin film transistor Tb1, a gate terminal is connected to the first terminal of the bootstrap capacitor Cb, the second signal node q (N), a drain terminal of the third thin film transistor T3, a drain terminal of the fifth thin film transistor T5, a gate terminal of the eighth thin film transistor T8, and a source terminal of the second bridging thin film transistor Tb2, and drain terminals are connected to the nth-stage start voltage st (N), a drain terminal of the sixth thin film transistor T6, and a second terminal of the bootstrap capacitor Cb; a first terminal of the bootstrap capacitor Cb is connected to the second signal node q (N), the drain terminal of the third thin-film transistor T3, the drain terminal of the fifth thin-film transistor T5, the gate terminal of the fourth thin-film transistor T4, the gate terminal of the eighth thin-film transistor T8, and the source terminal of the second bridging thin-film transistor Tb2, and a second terminal thereof is connected to the drain terminal of the fourth thin-film transistor T4, the nth-stage start voltage st (N), and the drain terminal of the sixth thin-film transistor T6; a source terminal of the fifth thin film transistor T5 is connected to the constant low level voltage VSS, a source terminal of the sixth thin film transistor T6, and a source terminal of the seventh thin film transistor T7, a gate terminal is connected to a P-th stage start voltage st (P), a gate terminal of the sixth thin film transistor T6, and a gate terminal of the seventh thin film transistor T7, and a drain terminal is connected to a drain terminal of the third thin film transistor T3, the second signal node q (n), a first terminal of the bootstrap capacitor Cb, a gate terminal of the fourth thin film transistor T4, a gate terminal of the eighth thin film transistor T8, and a source terminal of the second bridge thin film transistor Tb 2; a source terminal of the sixth thin film transistor T6 is connected to the constant low level voltage VSS, a source terminal of the fifth thin film transistor T5, and a source terminal of the seventh thin film transistor T7, a gate terminal is connected to a gate terminal of the fifth thin film transistor T5, the P-th stage start voltage st (P), and a gate terminal of the seventh thin film transistor T7, and a drain terminal is connected to a drain terminal of the fourth thin film transistor T4, the N-th stage start voltage st (N), and a second terminal of the bootstrap capacitor Cb; a source terminal of the seventh thin film transistor T7 is connected to the constant low level voltage VSS, a source terminal of the fifth thin film transistor T5, and a source terminal of the sixth thin film transistor T6, a gate terminal thereof is connected to a gate terminal of the fifth thin film transistor T5, the P-th stage start voltage st (P), and a gate terminal of the sixth thin film transistor T6, and a drain terminal thereof is connected to a drain terminal of the eighth thin film transistor T8, a drain terminal of the third bridging thin film transistor Tb3, and a corresponding scan line g (n); a source terminal of the eighth thin film transistor T8 is connected to a drain terminal of the first bridging thin film transistor Tb1, a gate terminal thereof is connected to a gate terminal of the fourth thin film transistor T4, a first terminal of the bootstrap capacitor Cb, the second signal node q (n), a drain terminal of the third thin film transistor T3, a drain terminal of the fifth thin film transistor T5, and a drain terminal of the second bridging thin film transistor Tb2, and a drain terminal thereof is connected to a drain terminal of the seventh thin film transistor T7, a source terminal of the third bridging thin film transistor Tb3, and the corresponding scan line g (n).
In the present embodiment, M and P are natural numbers smaller and larger than N, respectively. Preferably, the mth stage start voltage ST (M) is an N-4 th stage start voltage ST (N-4), and the pth stage start voltage ST (P) is an N +4 th stage start voltage ST (N +4), and the timing control is implemented using start voltages of different levels. It will be understood by those skilled in the art that the mth stage start voltage st (M) and the pth stage start voltage st (P) may be designed according to specific applications, and the present invention is not limited thereto.
Referring to fig. 2A and 2B, fig. 2A is a timing diagram of the first signal source S10 being at a high voltage level according to the embodiment of the present invention, and fig. 2B is a timing diagram of the first signal source S10 being at a low voltage level according to the embodiment of the present invention. The gate array substrate driving circuit provided by the embodiment of the invention can realize the conversion of two gate array substrate driving subunits (i.e. the first gate array substrate driving subunit 10 and the second gate array substrate driving subunit 20).
Referring to fig. 2A, when the first signal source S1 transmits a first signal having a high level voltage, since the gate terminal of the first thin film transistor T1 and the gate terminal of the second thin film transistor T2 are connected to the constant high level voltage VGH and the first signal source S1 of the first signal having the high level voltage, respectively, and the source terminals thereof are connected to the constant high level voltage VGH and the constant low level voltage VSS, respectively, therefore, the first thin film transistor T1 and the second thin film transistor T2 form an inverter (inverter), that is, when a high level voltage is inputted to the gate terminals of the first thin film transistor T1 and the second thin film transistor T2, the voltage at the output end of the drain terminal connection is a low level voltage (i.e. the first signal node k (n) is a low level voltage), so that the first bridging thin film transistor Tb1 is in an off state. Furthermore, since the gate terminal of the second bridge tft Tb2 receives the first signal having the high level voltage, the second bridge tft Tb2 is turned on.
Further, since the nth stage second signal source S2 is connected to the nth stage start voltage st (N) through the fourth tft T4, the level voltage of the second signal transmitted by the second signal source S2 (nth stage) is synchronous with the nth stage start voltage st (N), and the same is true for other stages, which is not described herein. When the second signal source S2 transmits the second signal having the low level voltage, the nth stage start voltage ST (N) is the low level voltage, and the (N +4) th stage start voltage ST (N +4) and the (N-4) th stage start voltage ST (N-4) are the high level voltage (refer to (a) of fig. 2A), at this time, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, the seventh thin film transistor T7, the eighth thin film transistor T8, and the third bridging thin film transistor Tb3 are all in the on state, so that the second signal node q (N) has the high level voltage, the bootstrap capacitor Cb starts to be charged, and the corresponding scan line g (N) is allowed to receive the first signal having the high level voltage. It is understood that, since the seventh tft T7 and the eighth tft T8 are turned on, the first signal is shunted and cannot be received by the corresponding scan line g (n).
Further, when the second signal source S2 transmits the second signal having a high level voltage, the nth stage start voltage ST (N) is a high level voltage, and the (N +4) th stage start voltage ST (N +4) and the (N-4) th stage start voltage ST (N-4) are low level voltages (refer to (b) of fig. 2A), at this time, the third thin film transistor T3, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 are all in an off state, and since the bootstrap capacitor Cb can continuously provide high level voltages to the gate terminal of the fourth thin film transistor T4, the gate terminal of the eighth thin film transistor T8, and the gate terminal of the third bridging thin film transistor Tb3, they are all in an on state, so that the corresponding scan line g (N) can receive the first signal having a high level voltage, since the seventh tft T7 and the eighth tft T8 are in the off state, all the first signals are received by the corresponding scan lines g (n), and thus the corresponding scan lines g (n) have stronger level signals. In addition, when the second signal having the high level voltage is transmitted to the source terminal of the fourth tft T4, the source terminal and the gate terminal thereof generate a capacitive coupling effect, so that the voltage at the gate terminal of the fourth tft T4 is further increased, and thus the level voltage of the second signal node q (n) is increased accordingly.
Referring to fig. 2B, when the first signal source S1 transmits the first signal having a low level voltage, the gate terminal of the first tft T1 and the gate terminal of the second tft T2 are connected to the constant high level voltage VGH and the first signal source S1 of the first signal having a low level voltage, respectively, so that the first tft T1 is in an on state, and the second tft T2 is in an off state, and the gate terminal of the first bridge tft Tb1 may receive the constant high level voltage VGH (i.e., the first signal node k (n) is a high level voltage), so that the first bridge tft Tb1 is also in an on state. Further, since the gate terminal of the second bridging tft Tb2 receives the first signal having a low level voltage, the second bridging tft Tb2 is in an off state, resulting in the third bridging tft Tb3 also being in an off state (i.e., its gate terminal does not receive a high level voltage).
Further, when the second signal source S2 transmits the second signal having a low level voltage, the nth stage start voltage ST (N) is a low level voltage, the (N +4) th stage start voltage ST (N +4) and the (N-4) th stage start voltage ST (N-4) are high level voltages (refer to (a) of fig. 2B), and at this time, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, the seventh thin film transistor T7 and the eighth thin film transistor T8 are all in an on state, therefore, the second signal node q (n) has a high level voltage, the bootstrap capacitor Cb starts to charge, the corresponding scan line g (n) and the second signal source S2 are turned on (but no signal is input to the corresponding scan line g (n)).
Further, when the second signal source S2 transmits the second signal having a high level voltage, the nth stage start voltage ST (N) is a high level voltage, the (N +4) th stage start voltage ST (N +4) and the (N-4) th stage start voltage ST (N-4) are low level voltages (refer to (B) of fig. 2B), and at this time, the third thin film transistor T3, the fifth thin film transistor T5, the sixth thin film transistor T6 and the seventh thin film transistor T7 are all in an off state, and since the bootstrap capacitor Cb can continuously supply the high level voltage to the gate terminal of the fourth thin film transistor T4 and the gate terminal of the eighth thin film transistor T8, therefore, they are all turned on, so that the corresponding scan line g (n) receives the second signal with high level voltage through the first bridging tft Tb1 and the eighth tft T8. In addition, when the second signal having the high level voltage is transmitted to the source terminal of the fourth tft T4, the source terminal and the gate terminal thereof generate a capacitive coupling effect, so that the voltage at the gate terminal of the fourth tft T4 is further increased, and thus the level voltage of the second signal node q (n) is increased accordingly.
The present invention controls the switching of two different gate array substrate driving sub-units according to the level voltage of the first signal transmitted by the first signal source S10, that is, when the first signal source S10 transmits the first signal with high level voltage, the first gate array substrate driving sub-unit 10 transmitting the first signal to the corresponding scan line g (n) is operated, and when the first signal source S10 transmits the first signal with low level voltage, the second gate array substrate driving sub-unit 20 transmitting the second signal to the corresponding scan line g (n) is operated. Compared with the prior art, the invention has the advantages of improving the opportunity of verifying the driving subunits of the grid array substrates and reducing the verification cost.
Although the present invention has been described with reference to the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope of the invention as defined by the appended claims.
Claims (8)
1. A gate array substrate driving circuit comprises a plurality of gate array substrate driving units which are connected in series, wherein the nth level gate array substrate driving unit transmits signals to the nth level scanning line corresponding to the nth level gate array substrate driving unit, and each gate array substrate driving unit comprises: a first gate array substrate driving subunit, comprising:
the first signal source is used for transmitting a first signal to the corresponding scanning line;
a first thin film transistor having a source terminal and a gate terminal connected to a constant high level voltage, and a drain terminal connected to a first signal node;
a second thin film transistor having a source terminal connected to a constant low level voltage, a gate terminal connected to the first signal source, and a drain terminal connected to the first signal node;
a first bridge thin film transistor having a gate terminal connected to the first signal node;
a second bridge thin film transistor, the grid end of which is connected with the first signal source; and
a third bridging thin film transistor, wherein the source end of the third bridging thin film transistor is connected with the first signal source, the grid end of the third bridging thin film transistor is connected with the drain end of the second bridging thin film transistor, and the drain end of the third bridging thin film transistor is connected with the corresponding scanning line; and
a second gate array substrate driving subunit, comprising:
the second signal source is used for transmitting a second signal to the corresponding scanning line;
a third thin film transistor having a source terminal and a gate terminal connected to the Mth level start voltage, and a drain terminal connected to the second signal node and the source terminal of the second bridge thin film transistor;
a fourth thin film transistor, a source terminal of which is connected to the second signal source and a source terminal of the first bridging thin film transistor, a gate terminal of which is connected to the second signal node, and a drain terminal of which is connected to the nth-stage start voltage;
a bootstrap capacitor having a first terminal connected to the second signal node and a second terminal connected to the nth stage start-up voltage;
a fifth thin film transistor having a source terminal connected to the constant low level voltage, a gate terminal connected to the P-th level start voltage, and a drain terminal connected to the second signal node;
a sixth thin film transistor, a source terminal of which is connected to the constant low level voltage, a gate terminal of which is connected to the P-th stage start voltage, and a drain terminal of which is connected to the second terminal of the bootstrap capacitor;
a seventh thin film transistor, a source terminal of which is connected with the constant low level voltage, a gate terminal of which is connected with the P-th level starting voltage, and a drain terminal of which is connected with the corresponding scanning line; and
a source terminal of the eighth thin film transistor is connected with a drain terminal of the first bridging thin film transistor, a gate terminal of the eighth thin film transistor is connected with the second signal node, and a drain terminal of the eighth thin film transistor is connected with the corresponding scanning line; wherein M and P are natural numbers smaller and larger than N respectively;
wherein the first gate array substrate driving subunit operates when the first signal source transmits the first signal having a high level voltage, and the second gate array substrate driving subunit operates when the first signal source transmits the first signal having a low level voltage.
2. The gate array substrate driving circuit of claim 1, wherein: when the first signal source transmits the first signal with high level voltage, the first bridging thin film transistor is in an off state, and the second bridging thin film transistor is in an on state.
3. The gate array substrate driving circuit of claim 2, wherein: when the second signal source transmits the second signal having a high level voltage, the first signal received by the corresponding scan line has a stronger level signal than when the second signal source transmits the second signal having a low level voltage.
4. The gate array substrate driving circuit of claim 1, wherein: when the first signal source transmits the first signal with low level voltage, the first bridging thin film transistor is in an on state, and the second bridging thin film transistor is in an off state.
5. The gate array substrate driving circuit of claim 4, wherein: when the second signal source transmits the second signal with low level voltage, the corresponding scanning line and the second signal source are in a conducting state.
6. The gate array substrate driving circuit of claim 4, wherein: when the second signal source transmits the second signal with a high level voltage, the corresponding scan line receives the second signal with a high level voltage.
7. The gate array substrate driving circuit of claim 1, wherein: when the second signal source transmits the second signal having a low level voltage, the nth stage start voltage is a low level voltage, and the mth stage start voltage and the pth stage start voltage are high level voltages.
8. The gate array substrate driving circuit of claim 1, wherein: when the second signal source transmits the second signal having a high level voltage, the nth stage start voltage is a high level voltage, and the mth stage start voltage and the pth stage start voltage are low level voltages.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010352611.8A CN111508415B (en) | 2020-04-28 | 2020-04-28 | Grid array substrate driving circuit |
| PCT/CN2020/096331 WO2021217814A1 (en) | 2020-04-28 | 2020-06-16 | Gate array substrate driving circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010352611.8A CN111508415B (en) | 2020-04-28 | 2020-04-28 | Grid array substrate driving circuit |
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| CN111508415A CN111508415A (en) | 2020-08-07 |
| CN111508415B true CN111508415B (en) | 2021-09-03 |
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Also Published As
| Publication number | Publication date |
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| CN111508415A (en) | 2020-08-07 |
| WO2021217814A1 (en) | 2021-11-04 |
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