CN107516492B - Shifting register, grid driving circuit and display device - Google Patents
Shifting register, grid driving circuit and display device Download PDFInfo
- Publication number
- CN107516492B CN107516492B CN201710859739.1A CN201710859739A CN107516492B CN 107516492 B CN107516492 B CN 107516492B CN 201710859739 A CN201710859739 A CN 201710859739A CN 107516492 B CN107516492 B CN 107516492B
- Authority
- CN
- China
- Prior art keywords
- signal
- switching transistor
- node
- output
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Shift Register Type Memory (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a shift register, a grid drive circuit and a display device, comprising: the device comprises a first control module, a second control module, a first output module and a second output module; the four modules are matched with each other, so that the output of the driving signal output end can be realized through a simple structure and fewer signal lines, the preparation process is simplified, and the production cost is reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a shift register, a grid driving circuit and a display device.
Background
With the rapid development of display technology, display panels are increasingly developed toward high integration and low cost. The Array substrate line driving (GOA) technology integrates a Thin Film Transistor (TFT) Gate switch Circuit on an Array substrate of a display panel to form scanning driving of the display panel, so that a wiring space of a binding (Bonding) area and a Fan-out (Fan-out) area of a Gate Integrated Circuit (IC) can be saved, the product cost can be reduced in two aspects of material cost and preparation process, and the display panel can be designed to be symmetrical at two sides and narrow-frame; moreover, the integration process can also omit the Bonding process in the direction of a grid scanning line, thereby improving the productivity and the yield.
A common gate driving circuit is composed of a plurality of cascaded shift registers, and scan signals are sequentially input to each row of gate lines on a display panel through each stage of shift register. At present, although the output of the scan signal can be realized by inputting more control signals with different functions, the number of the switching transistors forming each shift register in the gate driving circuit is large, and the specific structure of the connection between the switching transistors is also complicated, which leads to increase of the process difficulty and increase of the production cost, and even because more signal lines are needed to input the control signals with different functions into each shift register, the frame of the display panel is increased, and the display panel has no competitiveness.
Disclosure of Invention
Embodiments of the present invention provide a shift register, a gate driving circuit, and a display device, which have a simple structure, and have fewer signal lines connected to implement different functions of outputting scanning signals, so that the process complexity can be simplified, and the production cost can be reduced.
Accordingly, an embodiment of the present invention provides a shift register, including: the device comprises a first control module, a second control module, a first output module and a second output module;
the first control module is respectively connected with an input signal end, a reset signal end, a first reference signal end, a second reference signal end and a first node, and is used for providing a signal of the first reference signal end to the first node under the common control of the signals of the input signal end, the reset signal end and the first node, and providing a signal of the second reference signal end to the first node under the common control of the signals of the input signal end and the first node;
the second control module is respectively connected with the input signal end, the reset signal end and the first node, and is used for providing the signal of the input signal end to the first node under the control of the reset signal end;
the first output module is respectively connected with a clock signal end, the first node, the second node and a drive signal output end of the shift register, and is used for controlling the potential of the signal of the second node to be opposite to the potential of the signal of the first node and supplying the signal of the clock signal end to the signal output end under the common control of the signal of the first node and the signal of the second node;
the second output module is respectively connected with an output control signal end, the second reference signal end, the second node and the driving signal output end, and is used for providing the signal of the second reference signal end to the driving signal output end under the common control of the signals of the output control signal end and the second node.
Optionally, in the shift register provided in the embodiment of the present invention, the first control module includes: a first nor gate, a first switching transistor, a second switching transistor, and a third switching transistor;
a first input end of the first nor gate is connected with the input signal end, a second input end of the first nor gate is connected with the first node, and an output end of the first nor gate is respectively connected with a control electrode of the second switching transistor and a control electrode of the third switching transistor;
a control electrode of the first switching transistor is connected with the reset signal end, a first electrode of the first switching transistor is connected with the first reference signal end, and a second electrode of the first switching transistor is connected with a first electrode of the second switching transistor;
a second pole of the second switching transistor is connected to the first node;
a first pole of the third switching transistor is connected to the second reference signal terminal, and a second pole of the third switching transistor is connected to the first node.
Optionally, in the shift register provided in the embodiment of the present invention, the first control module includes: a second nor gate, the first inverter, the fourth switching transistor, the fifth switching transistor, and the sixth switching transistor;
a first input end of the second nor gate is connected with the input signal end, a second input end of the second nor gate is connected with the first node, and an output end of the second nor gate is connected with an input end of the first phase inverter;
the output end of the first inverter is connected with the control electrode of the fifth switching transistor and the control electrode of the sixth switching transistor respectively;
a control electrode of the fourth switching transistor is connected with the reset signal end, a first electrode of the fourth switching transistor is connected with the first reference signal end, and a second electrode of the fourth switching transistor is connected with a first electrode of the fifth switching transistor;
a second pole of the fifth switching transistor is connected to the first node;
a first pole of the sixth switching transistor is connected to the second reference signal terminal, and a second pole of the sixth switching transistor is connected to the first node.
Optionally, in the shift register provided in the embodiment of the present invention, the second control module includes: a seventh switching transistor;
and the control electrode of the seventh switching transistor is connected with the reset signal end, the first electrode of the seventh switching transistor is connected with the input signal end, and the second electrode of the seventh switching transistor is connected with the first node.
Optionally, in the shift register provided in the embodiment of the present invention, the first output module includes: a transmission gate and a second inverter;
the first control end of the transmission gate is connected with the first node, the second control end of the transmission gate is connected with the second node, the input end of the transmission gate is connected with the clock signal end, and the output end of the transmission gate is connected with the driving signal output end;
the input end of the second phase inverter is connected with the first node, and the output end of the second phase inverter is connected with the second node.
Optionally, in the shift register provided in the embodiment of the present invention, the second output module includes: an eighth switching transistor and a ninth switching transistor;
a control electrode of the eighth switching transistor is connected to the second node, a first electrode of the eighth switching transistor is connected to the second reference signal terminal, and a second electrode of the eighth switching transistor is connected to a first electrode of the ninth switching transistor;
and the control electrode of the ninth switching transistor is connected with the output control signal end, and the second electrode of the ninth switching transistor is connected with the driving signal output end.
Optionally, in the shift register provided in the embodiment of the present invention, the shift register further includes: a third inverter and a fourth inverter; the first output module and the second output module are respectively connected with the driving signal output end through the third inverter and the fourth inverter;
the input end of the third phase inverter is connected with the first output module and the second output module respectively, and the output end of the third phase inverter is connected with the input end of the fourth phase inverter;
and the output end of the fourth phase inverter is connected with the driving signal output end.
Optionally, in the shift register provided in the embodiment of the present invention, the shift register further includes: a tenth switching transistor and an eleventh switching transistor;
a control electrode of the tenth switching transistor is connected with a touch control signal end, a first electrode of the tenth switching transistor is connected with the second reference signal end, and a second electrode of the tenth switching transistor is connected with the first node;
a control electrode of the eleventh switching transistor is connected with the output control signal end, a first electrode of the eleventh switching transistor is connected with the first reference signal end, and a second electrode of the eleventh switching transistor is connected with the driving signal output end.
Correspondingly, an embodiment of the present invention further provides a gate driving circuit, including: a plurality of cascaded shift registers of any one of the above embodiments of the present invention are provided;
the input signal end of the first-stage shift register is connected with the frame trigger signal end;
except the first stage of shift register, the input signal end of each stage of shift register is respectively connected with the drive signal output end of the adjacent previous stage of shift register;
except the last stage of shift register, the reset signal end of each stage of shift register is respectively connected with the drive signal output end of the next stage of shift register adjacent to the reset signal end of the last stage of shift register.
Correspondingly, the embodiment of the invention also provides a display device which comprises the gate driving circuit provided by the embodiment of the invention.
The invention has the following beneficial effects:
the shift register, the gate driving circuit and the display device provided by the embodiment of the invention comprise: the device comprises a first control module, a second control module, a first output module and a second output module; the first control module is used for providing a signal of the first reference signal terminal to the first node under the common control of the signals of the input signal terminal, the reset signal terminal and the first node, and providing a signal of the second reference signal terminal to the first node under the common control of the signals of the input signal terminal and the first node; the second control module is used for providing the signal of the input signal end to the first node under the control of the reset signal end; the first output module is used for controlling the potential of the signal of the second node to be opposite to the potential of the signal of the first node, and providing the signal of the clock signal end to the driving signal output end under the common control of the signal of the first node and the signal of the second node; the second output module is used for providing the signal of the second reference signal end to the driving signal output end under the common control of the output control signal end and the signal of the second node. Therefore, through the mutual matching of the four modules, the output of the driving signal output end can be realized through a simple structure and fewer signal lines, so that the preparation process is simplified, and the production cost is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 2a is a schematic diagram of a specific structure of a shift register according to an embodiment of the present invention;
fig. 2b is a second schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 3a is a third schematic structural diagram of a shift register according to an embodiment of the present invention;
FIG. 3b is a fourth exemplary diagram of a shift register according to an embodiment of the present invention;
FIG. 4 is a timing diagram of an input/output according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, specific embodiments of a shift register, a gate driver circuit and a display device according to an embodiment of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only for illustrating and explaining the present invention and are not to be used for limiting the present invention. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
An embodiment of the present invention provides an array substrate, as shown in fig. 1, including: the system comprises a first control module 1, a second control module 2, a first output module 3 and a second output module 4;
the first control module 1 is respectively connected to the Input signal terminal Input, the Reset signal terminal Reset, the first reference signal terminal V1, the second reference signal terminal V2 and the first node N1, and is configured to provide the signal of the first reference signal terminal V1 to the first node N1 under the common control of the Input signal terminal Input, the Reset signal terminal Reset and the signal of the first node N1, and provide the signal of the second reference signal terminal V2 to the first node N1 under the common control of the Input signal terminal Input and the signal of the first node N1;
the second control module 2 is respectively connected to the Input signal terminal Input, the Reset signal terminal Reset and the first node N1, and is configured to provide a signal of the Input signal terminal Input to the first node N1 under the control of the Reset signal terminal Reset;
the first Output module 3 is respectively connected to the clock signal terminal CK, the first node N1, the second node N2, and the driving signal Output terminal Output of the shift register, and is configured to control a potential of the signal at the second node N2 to be inverted from a potential of the signal at the first node N1, and to provide the signal at the clock signal terminal CK to the signal Output terminal Output under common control of the signal at the first node N1 and the signal at the second node N2;
the second Output module 4 is respectively connected to the Output control signal terminal EN1, the second reference signal terminal V2, the second node N2, and the driving signal Output terminal Output, and is configured to provide the signal of the second reference signal terminal V2 to the driving signal Output terminal Output under the common control of the signals of the Output control signal terminal EN1 and the second node N2.
The shift register provided in the embodiment of the present invention includes: the device comprises a first control module, a second control module, a first output module and a second output module; the first control module is used for providing a signal of a first reference signal end to a first node under the common control of signals of the input signal end, the reset signal end and the first node, and providing a signal of a second reference signal end to the first node under the common control of the signals of the input signal end and the first node; the second control module is used for providing the signal of the input signal end to the first node under the control of the reset signal end; the first output module is used for controlling the potential of the signal of the second node to be opposite to the potential of the signal of the first node and supplying the signal of the clock signal end to the driving signal output end under the common control of the signal of the first node and the signal of the second node; the second output module is used for providing the signal of the second reference signal end to the driving signal output end under the common control of the output control signal end and the signal of the second node. Therefore, through the mutual matching of the four modules, the output of the driving signal output end can be realized through a simple structure and fewer signal lines, so that the preparation process is simplified, and the production cost is reduced.
In a specific implementation, in the shift register provided in the embodiment of the present invention, the effective pulse signal at the input signal end is a high-level signal, the signal at the first reference signal end is a high-level signal, and the signal at the second reference signal end is a low-level signal.
The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.
Specifically, in the shift register provided in the embodiment of the present invention, as shown in fig. 2a and fig. 2b, the first control module 1 may include: a first nor gate NY1, a first switching transistor M1, a second switching transistor M2, and a third switching transistor M3;
a first Input end of the first nor gate NY1 is connected to the Input signal end Input, a second Input end of the first nor gate NY1 is connected to the first node N1, and an output end of the first nor gate NY1 is connected to a control electrode of the second switching transistor M2 and a control electrode of the third switching transistor M3, respectively;
a control electrode of the first switching transistor M1 is connected to a Reset signal terminal Reset, a first electrode of the first switching transistor M1 is connected to a first reference signal terminal V1, and a second electrode of the first switching transistor M1 is connected to a first electrode of the second switching transistor M2;
a second pole of the second switching transistor M2 is connected to the first node N1;
a first pole of the third switching transistor M3 is connected to the second reference signal terminal V2, and a second pole of the third switching transistor M3 is connected to the first node N1.
In a specific implementation, in the shift register provided in the embodiment of the invention, as shown in fig. 2a and fig. 2b, the first switching transistor M1 and the second switching transistor M2 may be P-type transistors, and the third switching transistor M3 may be N-type transistors.
In a specific implementation, in the shift register provided in the embodiment of the present invention, when the signals at the input end of the first nor gate are all low-level signals, the output end of the first nor gate outputs a high-level signal. As long as the signal at one input terminal of the first nor gate is a high-level signal, the output terminal thereof will output a low-level signal. The first switching transistor may supply a signal of the first reference signal terminal to the first pole of the second switching transistor when the first switching transistor is in a turned-on state under control of a signal of the reset signal terminal. The second switching transistor may supply a signal input to the first pole thereof to the first node when it is in a turned-on state under control of a signal of the control pole thereof. The third switching transistor may supply a signal of the second reference signal terminal to the first node when it is in a turned-on state under control of a signal of a control electrode thereof. The specific structure of the first nor gate may be the same as that in the prior art, which is understood by those skilled in the art and is not described herein again.
Specifically, in the shift register provided in the embodiment of the present invention, as shown in fig. 3a and 3b, the first control module 1 may also include: a second nor gate NY2, a first inverter D1, a fourth switching transistor M4, a fifth switching transistor M5, and a sixth switching transistor M6;
a first Input terminal of the second nor gate NY2 is connected to the Input signal terminal Input, a second Input terminal of the second nor gate NY2 is connected to the first node N1, and an output terminal of the second nor gate NY2 is connected to an Input terminal of the first inverter D1;
an output end of the first inverter N1 is connected to a control electrode of the fifth switching transistor M5 and a control electrode of the sixth switching transistor M6, respectively;
a control electrode of the fourth switching transistor M4 is connected to the Reset signal terminal Reset, a first electrode of the fourth switching transistor M4 is connected to the first reference signal terminal V1, and a second electrode of the fourth switching transistor M4 is connected to a first electrode of the fifth switching transistor M5;
a second pole of the fifth switching transistor M5 is connected to the first node N1;
a first pole of the sixth switching transistor M6 is connected to the second reference signal terminal V2, and a second pole of the sixth switching transistor M6 is connected to the first node N1.
In the shift register according to the embodiment of the invention, as shown in fig. 3a and 3b, the fourth switching transistor M4 and the sixth switching transistor M6 may be P-type transistors, and the fifth switching transistor M5 may be N-type transistors.
In a specific implementation, in the shift register provided in the embodiment of the present invention, when the signals at the input end of the second nor gate are all low-level signals, the output end of the second nor gate outputs a high-level signal. As long as the signal at one input terminal of the second nor gate is a high-level signal, the output terminal thereof will output a low-level signal. The fourth switching transistor may supply the signal of the first reference signal terminal to the first pole of the fifth switching transistor when being in a turn-on state under the control of the signal of the reset signal terminal. The fifth switching transistor may supply a signal input to the first pole thereof to the first node when it is in a turned-on state under control of a signal of the control pole thereof. The sixth switching transistor may supply a signal of the second reference signal terminal to the first node when it is in a turned-on state under control of a signal of a control electrode thereof. The first inverter may have a signal at its input terminal opposite in potential to a signal at its output terminal. The specific structures of the second nor gate and the first inverter may be the same as those in the prior art, which is understood by those skilled in the art and will not be described herein.
Specifically, in the shift register provided in the embodiment of the present invention, as shown in fig. 2a to 3b, the second control module 2 may include: a seventh switching transistor M7;
a control electrode of the seventh switching transistor M7 is connected to the Reset signal terminal Reset, a first electrode of the seventh switching transistor M7 is connected to the Input signal terminal Input, and a second electrode of the seventh switching transistor M7 is connected to the first node N1.
In practical implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 2a to fig. 3b, the seventh switching transistor M7 may be an N-type transistor.
In a specific implementation, in the shift register provided in the embodiment of the present invention, when the seventh switching transistor is in a conducting state under the control of the signal at the reset signal terminal, the signal at the input signal terminal may be provided to the first node.
Specifically, in the shift register provided in the embodiment of the present invention, as shown in fig. 2a to 3b, the first output module 3 may include: a transmission gate TG and a second inverter D2;
a first control end of the transmission gate TG is connected with a first node N1, a second control end of the transmission gate TG is connected with a second node N2, an input end of the transmission gate TG is connected with a clock signal end CK, and an Output end of the transmission gate TG is connected with a driving signal Output end Output;
an input terminal of the second inverter D2 is connected to the first node N1, and an output terminal of the second inverter D2 is connected to the second node N2.
In a specific implementation, in the shift register provided in the embodiment of the present invention, the transmission gate is turned on when the signal of the first control terminal is a high-level signal and the signal of the second control terminal is a low-level signal, so as to provide the signal of the clock signal terminal to the driving signal output terminal. The second inverter may make the signal of its output terminal opposite in potential to the signal of its input terminal. The specific structures of the transmission gate and the second inverter may be respectively the same as those in the prior art, which can be understood by those skilled in the art and are not described herein again.
Specifically, in practical implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 2a to 3b, the second output module 4 may include: an eighth switching transistor M8 and a ninth switching transistor M9;
a control electrode of the eighth switching transistor M8 is connected to the second node N2, a first electrode of the eighth switching transistor M8 is connected to the second reference signal terminal V2, and a second electrode of the eighth switching transistor M8 is connected to a first electrode of the ninth switching transistor M9;
a control electrode of the ninth switching transistor M9 is connected to the Output control signal terminal EN1, and a second electrode of the ninth switching transistor M9 is connected to the driving signal Output terminal Output.
In a specific implementation, in the shift register provided in the embodiment of the invention, as shown in fig. 2a to fig. 3b, the eighth switching transistor M8 and the ninth switching transistor M9 may be N-type transistors.
In practical implementation, in the shift register provided in the embodiment of the present invention, when the eighth switching transistor is in a conducting state under the control of the signal at the second node, the signal at the second reference signal terminal may be provided to the first pole of the ninth switching transistor. The ninth switching transistor may supply a signal input to the first pole thereof to the signal output terminal when it is in a turned-on state under the control of the signal of the output control signal terminal.
Further, in order to improve the driving capability of the output signal, as shown in fig. 2b and fig. 3b, in the shift register provided in the embodiment of the present invention, the shift register may further include: a third inverter D3 and a fourth inverter D4; the first Output module 3 and the second Output module 4 are respectively connected with a driving signal Output end Output through a third inverter D3 and a fourth inverter D4;
the input end of the third inverter D3 is connected to the first output module 3 and the second output module 4, respectively, and the output end of the third inverter D3 is connected to the input end of the fourth inverter D4;
an Output terminal of the fourth inverter D4 is connected to the driving signal Output terminal Output.
In a specific implementation manner, in the shift register provided in the embodiment of the present invention, an input end of the third inverter is respectively connected to an output end of the transmission gate in the first output module and a second end of the ninth switching transistor in the second output module.
In practical implementation, in the shift register provided in the embodiment of the present invention, the third inverter may make a signal at an output terminal of the third inverter have an opposite potential to a signal at an input terminal of the third inverter. The fourth inverter may also have the signal at its output terminal opposite in potential to the signal at its input terminal. The third inverter and the fourth inverter may have the same structure as that in the prior art, and therefore, the structure thereof can be understood by those skilled in the art, and will not be described herein again.
Further, in a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 2b and fig. 3b, the shift register may further include: a tenth switching transistor M10 and an eleventh switching transistor M11;
a control electrode of the tenth switching transistor M10 is connected to the touch control signal terminal EN2, a first electrode of the tenth switching transistor M10 is connected to the second reference signal terminal V2, and a second electrode of the tenth switching transistor M10 is connected to the first node N1;
a control electrode of the eleventh switching transistor M11 is connected to the Output control signal terminal EN1, a first electrode of the eleventh switching transistor M11 is connected to the first reference signal terminal V1, and a second electrode of the eleventh switching transistor M11 is connected to the driving signal Output terminal Output.
In a specific implementation, in the shift register provided in the embodiment of the invention, as shown in fig. 2b and fig. 3b, the tenth switching transistor M10 may be an N-type transistor, and the eleventh switching transistor M11 may be a P-type transistor.
In a specific implementation, in the shift register provided in the embodiment of the present invention, when the tenth switching transistor is in a conducting state under the control of the signal at the touch control signal terminal, the signal at the second reference signal terminal may be provided to the first node. The eleventh switching transistor may supply the signal of the first reference signal terminal to the signal output terminal when it is in a turned-on state under the control of the signal of the output control signal terminal.
In a specific implementation, the shift register is generally applied to a display panel to input a scan signal to a gate line in the display panel, so that the display panel realizes a display function. Currently, the display panel generally has a touch function, and in order to avoid mutual interference between touch and display, the display and touch functions of the display panel are generally implemented by a touch and display time-sharing driving method. In the shift register provided in the embodiment of the present invention, a signal at the touch control signal end generally controls the tenth switching transistor to be turned off in the display stage, so that a normal scan signal is not affected, and display scanning is implemented. In the touch stage, the signal of the touch control signal terminal generally controls the tenth switching transistor to be turned on, so that the signal of the second node is a high-potential signal to control the transmission gate to be turned off, and the fifth switching transistor to be turned on, and the output control signal terminal also controls the fourth switching transistor to be turned on at this time, so that the driving signal output terminal can output a low-potential signal to stop display scanning for touch control.
In practical implementation, the signal of the output control signal terminal is generally a high-level signal. Only in a special case, the external control IC (Integrated Circuit) controls the signal of the output control signal terminal to become a low-level signal, so as to control the eleventh switching transistor to be turned on and provide the signal of the first reference signal terminal to the driving signal output terminal. The special case may be that the display panel is turned off when the power is off, or the display panel is powered off, which is that charges may remain in the pixels when the display screen is displayed, so that in order to avoid the charges remaining in the pixels from adversely affecting the display panel, the signals at the driving signal output end are changed into high-potential signals to control the charges remaining in the pixels to discharge.
Further, in the shift register according to the embodiment of the present invention, in a specific implementation, the N-type switching transistor is turned on by a high-potential signal and turned off by a low-potential signal; the P-type switching transistor is turned off under the action of a high potential signal and turned on under the action of a low potential signal.
It should be noted that the switching Transistor mentioned in the above embodiments of the present invention may be a Thin Film Transistor (TFT) or a Metal Oxide semiconductor field effect Transistor (MOS), and is not limited herein. In a specific implementation, the control electrode of each switching transistor is used as the gate electrode, and the first electrode can be used as the source electrode and the second electrode can be used as the drain electrode according to the type of the transistor and the difference of the input signal; or the first pole is used as the drain and the second pole is used as the source, which is not specifically distinguished here.
The following takes the structure of the shift register shown in fig. 2b as an example, and the operation process of the shift register provided by the embodiment of the present invention is described in detail with reference to the circuit timing diagram. In the following description, a high potential signal is denoted by 1, and a low potential signal is denoted by 0, where 1 and 0 represent logic potentials thereof, which are provided only for better explaining the operation of the shift register provided by the embodiment of the present invention, and are not potentials applied to the gates of the switching transistors in practical implementation. In the normal display input/output timing diagram of the shift register shown in fig. 2b, as shown in fig. 4, six stages T1, T2, T3, T4, T5 and T6 in fig. 4 are mainly selected. Moreover, the signal of the output control signal terminal EN1 is a high-level signal, and the signal of the touch control signal terminal is a low-level signal. The signal at the first reference signal terminal V1 is a high signal, and the signal at the second reference signal terminal V2 is a low signal.
In stage T1, Input is 1, CK is 0, and Reset is 0. Since Input is 1, the first nor gate NY1 outputs a low signal to control the second switching transistor M2 to be turned on and the third switching transistor M3 to be turned off. Since Reset is 0, the seventh switching transistor M7 is turned off and the first switching transistor M1 is turned on. The turned-on first and second switching transistors M1 and M2 provide the high signal of the first reference signal terminal V1 to the first node N1, so that the first node N1 is a high signal, and the signal of the second node N2 is a low signal due to the second inverter D2, thereby controlling the transmission gate TG to be turned on and the eighth switching transistor M8 to be turned off. The conducting transmission gate TG provides a low-potential signal of the clock signal terminal CK to the driving signal Output terminal Output, so that the driving signal Output terminal Output outputs a low-potential scanning signal.
In stage T2, Input is 0, CK is 0, and Reset is 0. Since Reset is 0, the seventh switching transistor M7 is turned off and the first switching transistor M1 is turned on. Therefore, the first node N1 is kept at the high signal, and the signal at the second node N2 is made to be the low signal, so that the transmission gate TG is controlled to be turned on, and the eighth switching transistor M8 is controlled to be turned off. The conducting transmission gate TG provides a low-potential signal of the clock signal terminal CK to the driving signal Output terminal Output, so that the driving signal Output terminal Output outputs a low-potential scanning signal.
In stage T3, Input is 0, CK is 1, and Reset is 0. Since Reset is 0, the seventh switching transistor M7 is turned off. Therefore, the first node N1 is kept at the high signal, and the signal at the second node N2 is made to be the low signal, so that the transmission gate TG is controlled to be turned on, and the eighth switching transistor M8 is controlled to be turned off. The conducting transmission gate TG provides a high-level signal of the clock signal terminal CK to the driving signal Output terminal Output, so that the driving signal Output terminal Output outputs a high-level scanning signal.
In stage T4, Input is 0, CK is 0, and Reset is 0. Since Reset is 0, the seventh switching transistor M7 is turned off. Therefore, the first node N1 is kept at the high signal, and the signal at the second node N2 is made to be the low signal, so that the transmission gate TG is controlled to be turned on, and the eighth switching transistor M8 is controlled to be turned off. The conducting transmission gate TG provides a low-potential signal of the clock signal terminal CK to the driving signal Output terminal Output, so that the driving signal Output terminal Output outputs a low-potential scanning signal.
In stage T5, Input is 0, CK is 0, and Reset is 1. Since Reset is 1, the seventh switching transistor M7 is turned on, and the first switching transistor M1 is turned off. The turned-on seventh switching transistor M7 provides a low-level signal of the Input signal terminal Input to the first node N1, so that the signal of the first node N1 is a potential signal, and the first nor gate NY1 outputs a high-level signal to control the second switching transistor M2 to be turned off and the third switching transistor M3 to be turned on. The turned-on third switching transistor M3 provides the low-level signal of the second reference signal terminal V2 to the first node N1, and further makes the signal at the first node N1 a low-level signal. Since the signal at the first node N1 is a low signal, the signal at the second node N2 is a high signal due to the second inverter D2, thereby controlling the transmission gate TG to be turned off and the eighth switching transistor M8 to be turned on. Since the signal of the output control signal terminal EN1 is a high level signal, the ninth switching transistor M9 is turned on. The turned-on eighth and ninth switching transistors M8 and M9 provide the low-level signal of the second reference signal terminal V2 to the driving signal Output terminal Output, so that the driving signal Output terminal Output outputs the scan signal with the low level.
In stage T6, Input is 0, CK is 0, and Reset is 0. Since Reset is 0, the seventh switching transistor M7 is turned off. Therefore, the first node N1 is kept at the low signal, the signal at the second node N2 is made to be the high signal by the second inverter N2, the transmission gate TG is controlled to be turned off, and the eighth switching transistor M8 is controlled to be turned on. Since the signal of the output control signal terminal EN1 is a high level signal, the ninth switching transistor M9 is turned on. The turned-on eighth and ninth switching transistors M8 and M9 provide the low-level signal of the second reference signal terminal V2 to the driving signal Output terminal Output, so that the driving signal Output terminal Output outputs the scan signal with the low level.
After the stage T6, the operation process of the stage T6 is repeatedly performed until the signal of the Input signal terminal Input becomes the high potential signal again.
The shift register provided by the embodiment of the invention can stably output the scanning signal through the simple structure and less signal lines, thereby simplifying the preparation process and reducing the production cost.
Based on the same inventive concept, an embodiment of the present invention further provides a gate driving circuit, as shown in fig. 5, including a plurality of cascaded shift registers SR (1), SR (2) … SR (N-1), SR (N) … SR (N-1), SR (N) (N shift registers, N is greater than or equal to 1 and less than or equal to N); wherein the content of the first and second substances,
an Input signal end Input of the first-stage shift register SR (1) is connected with a frame trigger signal end STV;
except for the first stage shift register SR (1), the Input signal ends Input of the other shift registers SR (n) are respectively connected with the drive signal Output ends Output of the adjacent previous stage shift register SR (n-1);
except the shift register SR (N) of the last stage, the Reset signal ends Reset of the shift registers SR (n) of the other stages are respectively connected with the driving signal output ends of the adjacent shift registers of the next stage.
Specifically, the gate driving circuit may be applied to a liquid crystal display panel, and may also be applied to an organic electroluminescence display panel, which is not limited herein. Moreover, the principle of the gate driving circuit to solve the problem is similar to that of the shift register, so the implementation of the gate driving circuit can refer to the implementation of the shift register, and the repeated parts are not described herein again.
In a specific implementation, in the gate driving circuit provided by the invention, the clock signal terminals of the 2k-1 th stage shift register are all connected with the same clock terminal, namely the first clock terminal ck 1; the clock signal ends of the 2 k-th stage shift register are connected with the same clock end, namely a second clock end ck 2; and k is a positive integer, and the period and the duty ratio of the signal of the first clock end and the signal of the second clock end are the same. And the output control signal end of each stage of shift register is connected with the same output control end, the first reference signal end of each stage of shift register is connected with the same first reference end, and the second reference signal end of each stage of shift register is connected with the same second reference end.
In specific implementation, when the shift register further includes a tenth switching transistor, the touch control signal terminals of the shift registers of the respective stages are all connected to the same touch control terminal.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the gate driving circuit provided by the embodiment of the invention. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention. The implementation of the display device can be seen in the embodiments of the gate driving circuit, and repeated descriptions are omitted.
The shift register, the gate driving circuit and the display device provided by the embodiment of the invention comprise: the device comprises a first control module, a second control module, a first output module and a second output module; the first control module is used for providing a signal of a first reference signal end to a first node under the common control of signals of the input signal end, the reset signal end and the first node, and providing a signal of a second reference signal end to the first node under the common control of the signals of the input signal end and the first node; the second control module is used for providing the signal of the input signal end to the first node under the control of the reset signal end; the first output module is used for controlling the potential of the signal of the second node to be opposite to the potential of the signal of the first node and supplying the signal of the clock signal end to the driving signal output end under the common control of the signal of the first node and the signal of the second node; the second output module is used for providing the signal of the second reference signal end to the driving signal output end under the common control of the output control signal end and the signal of the second node. Therefore, through the mutual matching of the four modules, the output of the driving signal output end can be realized through a simple structure and fewer signal lines, so that the preparation process is simplified, and the production cost is reduced.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (7)
1. A shift register, comprising: the device comprises a first control module, a second control module, a first output module and a second output module;
the first control module is respectively connected with an input signal end, a reset signal end, a first reference signal end, a second reference signal end and a first node, and is used for providing a signal of the first reference signal end to the first node under the common control of the signals of the input signal end, the reset signal end and the first node, and providing a signal of the second reference signal end to the first node under the common control of the signals of the input signal end and the first node;
the second control module is respectively connected with the input signal end, the reset signal end and the first node, and is used for providing the signal of the input signal end to the first node under the control of the reset signal end;
the first output module is respectively connected with a clock signal end, the first node, the second node and a drive signal output end of the shift register, and is used for controlling the potential of the signal of the second node to be opposite to the potential of the signal of the first node and supplying the signal of the clock signal end to the signal output end under the common control of the signal of the first node and the signal of the second node;
the second output module is respectively connected with an output control signal end, the second reference signal end, the second node and the driving signal output end, and is used for providing a signal of the second reference signal end to the driving signal output end under the common control of the signals of the output control signal end and the second node; the second control module includes: a seventh switching transistor; a control electrode of the seventh switching transistor is connected with the reset signal end, a first electrode of the seventh switching transistor is connected with the input signal end, and a second electrode of the seventh switching transistor is connected with the first node;
the first control module is: a first nor gate, a first switching transistor, a second switching transistor, and a third switching transistor; a first input end of the first nor gate is connected with the input signal end, a second input end of the first nor gate is connected with the first node, and an output end of the first nor gate is respectively connected with a control electrode of the second switching transistor and a control electrode of the third switching transistor; a control electrode of the first switching transistor is connected with the reset signal end, a first electrode of the first switching transistor is connected with the first reference signal end, and a second electrode of the first switching transistor is connected with a first electrode of the second switching transistor; a second pole of the second switching transistor is connected to the first node; a first pole of the third switching transistor is connected with the second reference signal terminal, and a second pole of the third switching transistor is connected with the first node; or the like, or, alternatively,
the first control module is: a second nor gate, the first inverter, the fourth switching transistor, the fifth switching transistor, and the sixth switching transistor; a first input end of the second nor gate is connected with the input signal end, a second input end of the second nor gate is connected with the first node, and an output end of the second nor gate is connected with an input end of the first phase inverter; the output end of the first inverter is connected with the control electrode of the fifth switching transistor and the control electrode of the sixth switching transistor respectively; a control electrode of the fourth switching transistor is connected with the reset signal end, a first electrode of the fourth switching transistor is connected with the first reference signal end, and a second electrode of the fourth switching transistor is connected with a first electrode of the fifth switching transistor; a second pole of the fifth switching transistor is connected to the first node; a first pole of the sixth switching transistor is connected to the second reference signal terminal, and a second pole of the sixth switching transistor is connected to the first node.
2. The shift register of claim 1, wherein the first output module comprises: a transmission gate and a second inverter;
the first control end of the transmission gate is connected with the first node, the second control end of the transmission gate is connected with the second node, the input end of the transmission gate is connected with the clock signal end, and the output end of the transmission gate is connected with the driving signal output end;
the input end of the second phase inverter is connected with the first node, and the output end of the second phase inverter is connected with the second node.
3. The shift register of claim 1, wherein the second output module comprises: an eighth switching transistor and a ninth switching transistor;
a control electrode of the eighth switching transistor is connected to the second node, a first electrode of the eighth switching transistor is connected to the second reference signal terminal, and a second electrode of the eighth switching transistor is connected to a first electrode of the ninth switching transistor;
and the control electrode of the ninth switching transistor is connected with the output control signal end, and the second electrode of the ninth switching transistor is connected with the driving signal output end.
4. The shift register of any of claims 1-3, further comprising: a third inverter and a fourth inverter; the first output module and the second output module are respectively connected with the driving signal output end through the third inverter and the fourth inverter;
the input end of the third phase inverter is connected with the first output module and the second output module respectively, and the output end of the third phase inverter is connected with the input end of the fourth phase inverter;
and the output end of the fourth phase inverter is connected with the driving signal output end.
5. The shift register of any of claims 1-2, further comprising: a tenth switching transistor and an eleventh switching transistor;
a control electrode of the tenth switching transistor is connected with a touch control signal end, a first electrode of the tenth switching transistor is connected with the second reference signal end, and a second electrode of the tenth switching transistor is connected with the first node;
a control electrode of the eleventh switching transistor is connected with the output control signal end, a first electrode of the eleventh switching transistor is connected with the first reference signal end, and a second electrode of the eleventh switching transistor is connected with the driving signal output end.
6. A gate drive circuit, comprising: a plurality of shift registers according to any one of claims 1 to 5 in cascade;
the input signal end of the first-stage shift register is connected with the frame trigger signal end;
except the first stage of shift register, the input signal end of each stage of shift register is respectively connected with the drive signal output end of the adjacent previous stage of shift register;
except the last stage of shift register, the reset signal end of each stage of shift register is respectively connected with the drive signal output end of the next stage of shift register adjacent to the reset signal end of the last stage of shift register.
7. A display device comprising the gate driver circuit according to claim 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710859739.1A CN107516492B (en) | 2017-09-21 | 2017-09-21 | Shifting register, grid driving circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710859739.1A CN107516492B (en) | 2017-09-21 | 2017-09-21 | Shifting register, grid driving circuit and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107516492A CN107516492A (en) | 2017-12-26 |
| CN107516492B true CN107516492B (en) | 2020-12-25 |
Family
ID=60725916
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710859739.1A Active CN107516492B (en) | 2017-09-21 | 2017-09-21 | Shifting register, grid driving circuit and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107516492B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107958649B (en) * | 2018-01-02 | 2021-01-26 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN108389559B (en) * | 2018-05-03 | 2020-08-21 | 京东方科技集团股份有限公司 | Shift register module, driving method, grid driving circuit and display device |
| CN110930951A (en) * | 2019-12-24 | 2020-03-27 | 昆山国显光电有限公司 | Gate drive circuit, display panel and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101255270B1 (en) * | 2006-08-14 | 2013-04-15 | 엘지디스플레이 주식회사 | Shift register and method for driving the same and display device using the same |
| CN104992662A (en) * | 2015-08-04 | 2015-10-21 | 京东方科技集团股份有限公司 | GOA (Gate Driver On Array) unit, driving method of GOA unit, GOA circuit and display device |
| CN106847223A (en) * | 2017-03-29 | 2017-06-13 | 武汉华星光电技术有限公司 | Scan drive circuit and liquid crystal display panel |
| CN107154235A (en) * | 2017-07-21 | 2017-09-12 | 京东方科技集团股份有限公司 | Scan shift circuit, touch-control shift circuit, driving method and relevant apparatus |
-
2017
- 2017-09-21 CN CN201710859739.1A patent/CN107516492B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101255270B1 (en) * | 2006-08-14 | 2013-04-15 | 엘지디스플레이 주식회사 | Shift register and method for driving the same and display device using the same |
| CN104992662A (en) * | 2015-08-04 | 2015-10-21 | 京东方科技集团股份有限公司 | GOA (Gate Driver On Array) unit, driving method of GOA unit, GOA circuit and display device |
| CN106847223A (en) * | 2017-03-29 | 2017-06-13 | 武汉华星光电技术有限公司 | Scan drive circuit and liquid crystal display panel |
| CN107154235A (en) * | 2017-07-21 | 2017-09-12 | 京东方科技集团股份有限公司 | Scan shift circuit, touch-control shift circuit, driving method and relevant apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107516492A (en) | 2017-12-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9747854B2 (en) | Shift register, gate driving circuit, method for driving display panel and display device | |
| US9847067B2 (en) | Shift register, gate driving circuit, display panel, driving method thereof and display device | |
| US10049609B2 (en) | Shift register, gate driving circuit, and display device | |
| US11011117B2 (en) | Shift register, drive method thereof, drive control circuit, and display apparatus | |
| EP3355309B1 (en) | Shift register, gate driving circuit and display device | |
| US20200013473A1 (en) | Shift register, method for driving the same, gate integrated driver circuit, and display device | |
| CN111445866B (en) | Shift register, driving method, driving control circuit and display device | |
| CN106504692B (en) | Shifting register, driving method thereof, grid driving circuit and display device | |
| CN110706656B (en) | Shift register, driving method thereof, driving circuit and display device | |
| US10467966B2 (en) | Shift register and a method for driving the same, a gate driving circuit and display apparatus | |
| US10559242B2 (en) | Shift register, driving method thereof, gate line integrated driving circuit and display device | |
| US10403210B2 (en) | Shift register and driving method, driving circuit, array substrate and display device | |
| CN107516492B (en) | Shifting register, grid driving circuit and display device | |
| US11423823B2 (en) | Shift register and driving method thereof, gate driving circuit and display device capabling reset the output terminal | |
| US11961582B2 (en) | Shift register unit, driving method thereof, and device | |
| CN107393499B (en) | Square wave corner cutting circuit, driving method thereof and display panel | |
| CN107123389B (en) | Shift register, grid drive circuit and display device | |
| CN109389926B (en) | Shift register, grid drive circuit and array substrate | |
| CN111223515B (en) | Shift register, driving method thereof, driving circuit and display device | |
| CN108511025B (en) | Shifting register unit, grid driving circuit and display device | |
| CN112037727B (en) | Shift register unit and gate drive circuit | |
| CN110085159B (en) | Shifting register unit, grid driving circuit and display device | |
| US10553140B2 (en) | Inversion control circuit, method for driving the same, display panel, and display device | |
| CN111462675A (en) | Shifting register, grid driving circuit and display device | |
| CN111489676B (en) | Array substrate, driving method and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |