CN107123389B - Shift register, grid drive circuit and display device - Google Patents
Shift register, grid drive circuit and display device Download PDFInfo
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- CN107123389B CN107123389B CN201710534889.5A CN201710534889A CN107123389B CN 107123389 B CN107123389 B CN 107123389B CN 201710534889 A CN201710534889 A CN 201710534889A CN 107123389 B CN107123389 B CN 107123389B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The invention discloses a shift register, a grid drive circuit and a display device, wherein the shift register comprises: the device comprises an input module, a reset module, a first control module, a first output module and a first noise reduction module. The shift register is matched with the five modules, when an input signal is normal within a frame time, the first noise reduction module is in a non-working state, and normal output of the shift register is not influenced; when at least two effective pulses appear in an input signal within a frame time, the first noise reduction module can provide a signal of the first reference signal end to the first node under the combined action of the signal of the input signal end and the second clock signal, and pull down the potential of the first node, so that the noise of the grid signal output end can be eliminated, and the stability of the signal output by the grid signal output end is ensured.
Description
Technical Field
The invention relates to the technical field of display, in particular to a shift register, a grid driving circuit and a display device.
Background
With the rapid development of display technology, displays have developed a trend of high integration and low cost. The GOA (Gate Driver on Array) technology integrates a TFT (Thin Film Transistor) Gate switch Circuit on an Array substrate of a display panel to form a scan drive for the display panel, so that a wiring space of a binding (Bonding) region and a Fan-out (Fan-out) region of a Gate Integrated Circuit (IC) can be omitted, and not only can the product cost be reduced in two aspects of material cost and manufacturing process, but also the display panel can be made to have an aesthetic design with two symmetrical sides and a narrow frame; moreover, the integration process can also omit the Bonding process in the direction of a grid scanning line, thereby improving the productivity and the yield.
The gate driving circuit also generally includes a plurality of cascaded shift registers, and each shift register sequentially outputs a scan signal under the control of a frame trigger signal. However, in the display panel with switchable refresh frequency, when the first frame image after switching the refresh frequency is displayed, the frame trigger signal is easy to be abnormal, that is, at least two effective pulses appear within one frame time, so that the potential of the pull-up node of the shift register is always high potential, and the partial switch transistor in the shift register is in a conducting state for a long time to malfunction, thereby causing the display panel to be scrapped.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a shift register, a gate driving circuit and a display device, so as to solve the problem of poor output of the conventional shift register.
Accordingly, an embodiment of the present invention provides a shift register, including: the device comprises an input module, a reset module, a first control module, a first output module and a first noise reduction module; wherein the content of the first and second substances,
the input module is used for controlling the potential of the first node according to an input signal of the input signal end;
the reset module is used for providing a signal of a first reference signal terminal to the first node under the control of a reset signal terminal;
the first control module is used for controlling the potentials of the first node and the second node;
the first output module is used for providing a first clock signal of a first clock signal end to the grid signal output end of the shift register under the control of the first node and providing a signal of the first reference signal end to the grid signal output end of the shift register under the control of the second node;
the first noise reduction module is used for providing a signal of the first reference signal end to the first node under the common control of an input signal of the input signal end and a second clock signal of a second clock signal end;
the second clock signal has the same clock period as the first clock signal, and the phase difference between the second clock signal and the first clock signal is 4 pi/3.
In a possible implementation manner, in a shift register provided in an embodiment of the present invention, the first noise reduction module includes: a first switching transistor and a second switching transistor; wherein the content of the first and second substances,
the grid electrode of the first switching transistor is connected with the second clock signal end, the first pole of the first switching transistor is connected with the first node, and the second pole of the first switching transistor is connected with the first pole of the second switching transistor;
and the grid electrode of the second switching transistor is connected with the input signal end, and the second pole of the second switching transistor is connected with the first reference signal end.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the shift register further includes: a second noise reduction module; wherein the content of the first and second substances,
the second noise reduction module is used for providing the signal of the first reference signal end to the grid signal output end of the shift register under the common control of the input signal end and the second clock signal of the second clock signal end.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the second noise reduction module includes: a third switching transistor and a fourth switching transistor; wherein the content of the first and second substances,
the grid electrode of the third switching transistor is connected with the second clock signal end, the first electrode of the third switching transistor is connected with the grid signal output end of the shift register, and the second electrode of the third switching transistor is connected with the first electrode of the fourth switching transistor;
and the grid electrode of the fourth switching transistor is connected with the input signal end, and the second pole of the fourth switching transistor is connected with the first reference signal end.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the input module includes: a fifth switching transistor; wherein the content of the first and second substances,
and the grid electrode and the first electrode of the fifth switching transistor are both connected with the input signal end, and the second electrode of the fifth switching transistor is connected with the first node.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the reset module includes: a sixth switching transistor; wherein the content of the first and second substances,
and the grid electrode of the sixth switching transistor is connected with the reset signal end, the first pole of the sixth switching transistor is connected with the first node, and the second pole of the sixth switching transistor is connected with the first reference signal end.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the first output module includes: a seventh switching transistor, an eighth switching transistor, and a capacitor; wherein the content of the first and second substances,
a gate of the seventh switching transistor is connected to the first node, a first pole of the seventh switching transistor is connected to the first clock signal terminal, and a second pole of the seventh switching transistor is connected to a gate signal output terminal of the shift register;
a gate of the eighth switching transistor is connected to the second node, a first pole of the eighth switching transistor is connected to a gate signal output end of the shift register, and a second pole of the eighth switching transistor is connected to the first reference signal end;
the capacitor is connected between the gate and the second pole of the seventh switching transistor.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the first control module includes: a ninth switching transistor, a tenth switching transistor, an eleventh switching transistor, a twelfth switching transistor, and a thirteenth switching transistor; wherein the content of the first and second substances,
a gate of the ninth switching transistor is connected to the second node, a first pole of the ninth switching transistor is connected to the first node, and a second pole of the ninth switching transistor is connected to the first reference signal terminal;
a gate and a first pole of the tenth switching transistor are both connected to the second reference signal terminal, and a second pole of the tenth switching transistor is respectively connected to the first pole of the twelfth switching transistor and the gate of the eleventh switching transistor;
a first terminal of the eleventh switching transistor is connected to the second reference signal terminal, and a second terminal thereof is connected to the second node;
a gate of the twelfth switching transistor is connected to the first node, and a second pole of the twelfth switching transistor is connected to the first reference signal terminal;
and the gate of the thirteenth switching transistor is connected with the first node, the first pole of the thirteenth switching transistor is connected with the second node, and the second pole of the thirteenth switching transistor is connected with the first reference signal end.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the shift register further includes: the second control module and the second output module; wherein the content of the first and second substances,
the second control module is used for controlling the electric potentials of the first node and the third node;
the second output module is used for providing the signal of the first reference signal end to the grid signal output end of the shift register under the control of the third node.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the second control module includes: a fourteenth switching transistor, a fifteenth switching transistor, a sixteenth switching transistor, a seventeenth switching transistor, and an eighteenth switching transistor; wherein the content of the first and second substances,
a gate and a first pole of the fourteenth switching transistor are both connected to a third reference signal terminal, and a second pole of the fourteenth switching transistor is respectively connected to the first pole of the sixteenth switching transistor and the gate of the fifteenth switching transistor;
a first pole of the fifteenth switching transistor is connected with the third reference signal terminal, and a second pole of the fifteenth switching transistor is connected with the third node;
a gate of the sixteenth switching transistor is connected to the first node, and a second pole of the sixteenth switching transistor is connected to the first reference signal terminal;
a gate of the seventeenth switching transistor is connected to the first node, a first pole of the seventeenth switching transistor is connected to the third node, and a second pole of the seventeenth switching transistor is connected to the first reference signal terminal;
and the gate of the eighteenth switching transistor is connected with the third node, the first pole of the eighteenth switching transistor is connected with the first node, and the second pole of the eighteenth switching transistor is connected with the first reference signal end.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, the second output module includes: a nineteenth switching transistor; wherein the content of the first and second substances,
and the gate of the nineteenth switching transistor is connected with the third node, the first pole of the nineteenth switching transistor is connected with the gate signal output end of the shift register, and the second pole of the nineteenth switching transistor is connected with the first reference signal end.
Correspondingly, the embodiment of the invention also provides a gate drive circuit, which comprises a plurality of cascaded shift registers provided by the embodiment of the invention; wherein the content of the first and second substances,
except the first stage of shift register, the input signal end of each stage of shift register is connected with the grid signal output end of the adjacent previous stage of shift register;
except the last stage of shift register, the reset signal end of each stage of shift register is connected with the grid signal output end of the next stage of shift register adjacent to the reset signal end of each stage of shift register.
Correspondingly, the embodiment of the invention also provides a display device which comprises the gate drive circuit provided by the embodiment of the invention.
The invention has the following beneficial effects:
the embodiment of the invention provides a shift register, a grid drive circuit and a display device, wherein the shift register comprises: the device comprises an input module, a reset module, a first control module, a first output module and a first noise reduction module; the input module is used for controlling the potential of the first node according to an input signal of the input signal end; the reset module is used for providing a signal of the first reference signal terminal to the first node under the control of the reset signal terminal; the first control module is used for controlling the electric potentials of the first node and the second node; the first output module is used for providing a first clock signal of a first clock signal end to a grid signal output end of the shift register under the control of a first node and providing a signal of a first reference signal end to the grid signal output end of the shift register under the control of a second node; the first noise reduction module is used for providing a signal of a first reference signal end to a first node under the common control of an input signal of the input signal end and a second clock signal of a second clock signal end; the second clock signal has the same clock period as the first clock signal, and the phase difference between the second clock signal and the first clock signal is 4 pi/3. The shift register is matched with the five modules, when an input signal is normal within a frame time, the first noise reduction module is in a non-working state, and normal output of the shift register is not influenced; when at least two effective pulses appear in an input signal within a frame time, the first noise reduction module can provide a signal of the first reference signal end to the first node under the combined action of the signal of the input signal end and the second clock signal, and pull down the potential of the first node, so that the noise of the grid signal output end can be eliminated, and the stability of the signal output by the grid signal output end is ensured.
Drawings
Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 2 is a second schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 3 is a third schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 4a is a schematic structural diagram of a shift register in which all transistors are N-type transistors according to an embodiment of the present invention;
FIG. 4b is a schematic diagram of a specific structure of a shift register in which all transistors are P-type transistors according to an embodiment of the present invention;
FIG. 5a is a timing diagram illustrating the normal input/output states of the shift register shown in FIG. 4 a;
FIG. 5b is a timing diagram illustrating the input/output of the shift register shown in FIG. 4a when the input is high at stage T2;
FIG. 5c is a timing diagram illustrating the input/output of the shift register shown in FIG. 4a when the input is high at stage T3;
FIG. 5d is a timing diagram illustrating the input/output states of the shift register shown in FIG. 4a when the input is high at stage T4;
FIG. 5e is a timing diagram illustrating the input/output states of the shift register shown in FIG. 4a when the input is high at stage T5;
fig. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention.
Detailed Description
The following describes in detail specific embodiments of a shift register, a gate driver circuit, and a display device according to embodiments of the present invention with reference to the accompanying drawings.
As shown in fig. 1, a shift register according to an embodiment of the present invention includes: the device comprises an input module 1, a reset module 2, a first control module 3, a first output module 4 and a first noise reduction module 5; wherein the content of the first and second substances,
the Input module 1 is used for controlling the potential of a first node A according to an Input signal of an Input signal end Input;
the Reset module 2 is used for providing a signal of a first reference signal terminal Vref1 to a first node a under the control of a Reset signal terminal Reset;
the first control module 3 is used for controlling the electric potentials of the first node A and the second node B;
the first Output module 4 is configured to provide a first clock signal of the first clock signal terminal CLK1 to the gate signal Output terminal Output of the shift register under the control of the first node a, and provide a signal of the first reference signal terminal Vref1 to the gate signal Output terminal Output of the shift register under the control of the second node B;
the first noise reduction module 5 is configured to provide a signal of a first reference signal terminal Vref1 to the first node a under common control of an Input signal of the Input signal terminal Input and a second clock signal of the second clock signal terminal CLK 2;
the second clock signal has the same clock period as the first clock signal, and the phase difference between the second clock signal and the first clock signal is 4 pi/3.
The shift register provided by the embodiment of the invention comprises: the device comprises an input module, a reset module, a first control module, a first output module and a first noise reduction module; the input module is used for controlling the potential of the first node according to an input signal of the input signal end; the reset module is used for providing a signal of the first reference signal terminal to the first node under the control of the reset signal terminal; the first control module is used for controlling the electric potentials of the first node and the second node; the first output module is used for providing a first clock signal of a first clock signal end to a grid signal output end of the shift register under the control of a first node and providing a signal of a first reference signal end to the grid signal output end of the shift register under the control of a second node; the first noise reduction module is used for providing a signal of a first reference signal end to a first node under the common control of an input signal of the input signal end and a second clock signal of a second clock signal end; the second clock signal has the same clock period as the first clock signal, and the phase difference between the second clock signal and the first clock signal is 4 pi/3. The shift register is matched with the five modules, when an input signal is normal within a frame time, the first noise reduction module is in a non-working state, and normal output of the shift register is not influenced; when at least two effective pulses appear in an input signal within a frame time, the first noise reduction module can provide a signal of the first reference signal end to the first node under the combined action of the signal of the input signal end and the second clock signal, and pull down the potential of the first node, so that the noise of the grid signal output end can be eliminated, and the stability of the signal output by the grid signal output end is ensured.
The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is for better explaining the present invention, but not limiting the present invention.
Preferably, in the shift register according to the embodiment of the present invention, as shown in fig. 4a and 4b, the first noise reduction module 5 may specifically include: a first switching transistor M1 and a second switching transistor M2; wherein the content of the first and second substances,
a first switching transistor M1 having a gate connected to the second clock signal terminal CLK2, a first pole connected to the first node a, and a second pole connected to the first pole of the second switching transistor M2;
a second switching transistor M2 has a gate connected to the Input signal terminal Input and a second pole connected to the first reference signal terminal Vref 1.
Specifically, in practical implementation, as shown in fig. 4a, the first switching transistor M1 and the second switching transistor M2 may be N-type transistors, or as shown in fig. 4b, the first switching transistor M1 and the second switching transistor M2 may also be P-type transistors, which is not limited herein.
The above is merely to illustrate a specific structure of the first noise reduction module in the shift register, and in the specific implementation, the specific structure of the first noise reduction module is not limited to the above structure provided in the embodiment of the present invention, and may also be other structures known to those skilled in the art, and is not limited herein.
Preferably, in an implementation, when a plurality of input signals with high voltage level appear in a frame time, the input signals and the output signals are high at the same time, in order to ensure that the gate signal output terminal can output normally, in the shift register provided in the embodiment of the present invention, as shown in fig. 2 and fig. 3, the shift register further includes: a second noise reduction module 6; wherein the content of the first and second substances,
the second noise reduction module 6 is configured to provide a signal of the first reference signal terminal Vref1 to the gate signal Output terminal Output of the shift register under common control of an Input signal of the Input signal terminal Input and a second clock signal of the second clock signal terminal CLK 2.
Preferably, in the shift register according to the embodiment of the present invention, as shown in fig. 4a and 4b, the second noise reduction module 6 may specifically include: a third switching transistor M3 and a fourth switching transistor M4; wherein the content of the first and second substances,
a third switching transistor M3, a gate of which is connected to the second clock signal terminal CLK2, a first pole of which is connected to the gate signal Output terminal Output of the shift register, and a second pole of which is connected to the first pole of the fourth switching transistor M4;
the fourth switching transistor M4 has a gate connected to the Input signal terminal Input, and a second pole connected to the first reference signal terminal Vref 1.
Specifically, in practical implementation, as shown in fig. 4a, the third switching transistor M3 and the fourth switching transistor M4 may be N-type transistors, or as shown in fig. 4b, the third switching transistor M3 and the fourth switching transistor M4 may also be P-type transistors, which is not limited herein.
The above is merely to illustrate the specific structure of the second noise reduction module in the shift register, and in the specific implementation, the specific structure of the second noise reduction module is not limited to the above structure provided in the embodiment of the present invention, and may also be other structures known to those skilled in the art, and is not limited herein.
Preferably, in the shift register according to the embodiment of the present invention, as shown in fig. 4a and 4b, the input module 1 may specifically include: a fifth switching transistor M5; wherein the content of the first and second substances,
a fifth switching transistor M5 has a gate and a first pole connected to the Input signal terminal Input, and a second pole connected to the first node a.
Specifically, in practical implementation, as shown in fig. 4a, the fifth switching transistor M5 may be an N-type transistor, or as shown in fig. 4b, the fifth switching transistor M5 may also be a P-type transistor, which is not limited herein.
The above is merely an example of the specific structure of the input module in the shift register, and in the specific implementation, the specific structure of the input module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
Preferably, in an implementation of the shift register provided in the embodiment of the present invention, as shown in fig. 4a and 4b, the reset module 2 may specifically include: a sixth switching transistor M6; wherein the content of the first and second substances,
the sixth switching transistor M6 has a gate connected to the Reset signal terminal Reset, a first pole connected to the first node a, and a second pole connected to the first reference signal terminal Vref 1.
Specifically, in practical implementation, as shown in fig. 4a, the sixth switching transistor M6 may be an N-type transistor, or as shown in fig. 4b, the sixth switching transistor M6 may also be a P-type transistor, which is not limited herein.
The above is merely an example of the specific structure of the reset module in the shift register, and in the specific implementation, the specific structure of the reset module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
Preferably, in the shift register according to the embodiment of the present invention, as shown in fig. 4a and 4b, the first output module 3 may include: a seventh switching transistor M7, an eighth switching transistor M8, and a capacitor C; wherein the content of the first and second substances,
a seventh switching transistor M7, having a gate connected to the first node a, a first pole connected to the first clock signal terminal CLK1, and a second pole connected to the gate signal Output terminal Output of the shift register;
an eighth switching transistor M8, having a gate connected to the second node B, a first pole connected to the gate signal Output terminal Output of the shift register, and a second pole connected to the first reference signal terminal Vref 1;
the capacitor C is connected between the gate and the second pole of the seventh switching transistor M7.
Specifically, in practical implementation, as shown in fig. 4a, the seventh switching transistor M7 and the eighth switching transistor M8 may be N-type transistors, or as shown in fig. 4b, the seventh switching transistor M7 and the eighth switching transistor M8 may also be P-type transistors, which is not limited herein.
The above is merely an example of the specific structure of the first output module in the shift register, and in the specific implementation, the specific structure of the first output module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a specific implementation, the first control module is configured to control the potentials of the first node and the second node, and taking an effective pulse signal of an input signal as a high potential signal as an example, the first control module is not limited herein as long as it can achieve the functions that the potential of the first node is a high potential and the potential of the second node is a low potential from the start of input to the end of output within one frame time, the potential of the first node is a low potential and the potential of the second node is a high potential from the end of output to the start of the next frame.
Preferably, in an implementation of the shift register provided in the embodiment of the present invention, as shown in fig. 4a and 4b, the first control module 4 may specifically include: a ninth switching transistor M9, a tenth switching transistor M10, an eleventh switching transistor M11, a twelfth switching transistor M12, and a thirteenth switching transistor M13; wherein the content of the first and second substances,
a ninth switching transistor M9 having a gate connected to the second node B, a first pole connected to the first node a, and a second pole connected to the first reference signal terminal Vref 1;
a tenth switching transistor M10 having a gate and a first pole both connected to the second reference signal terminal Vref2, and a second pole respectively connected to the first pole of the twelfth switching transistor M12 and the gate of the eleventh switching transistor M11;
an eleventh switching transistor M11 having a first pole connected to the second reference signal terminal Vref2 and a second pole connected to the second node B;
a twelfth switching transistor M12 having a gate connected to the first node a and a second pole connected to the first reference signal terminal Vref 1;
a thirteenth switching transistor M13 has a gate connected to the first node a, a first pole connected to the second node B, and a second pole connected to the first reference signal terminal Vref 1.
Specifically, in practical implementation, as shown in fig. 4a, the ninth to thirteenth switching transistors M9 to M13 may be N-type transistors, or as shown in fig. 4b, the ninth to thirteenth switching transistors M9 to M13 may also be P-type transistors, which is not limited herein.
In a specific implementation, the signal of the second reference signal terminal Vref2 is a dc source signal.
The above is merely an example of the specific structure of the first control module in the shift register, and in the specific implementation, the specific structure of the first control module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
Preferably, in a specific implementation, to avoid the problem of characteristic shift and even damage of the switching transistor of the first control module caused by long-time dc bias, as shown in fig. 3, the shift register provided in the embodiment of the present invention further includes: a second control module 7 and a second output module 8; wherein the content of the first and second substances,
the second control module 7 is used for controlling the electric potentials of the first node A and the third node D;
the second Output module 8 is configured to provide a signal of the first reference signal terminal Vref1 to the gate signal Output terminal Output of the shift register under the control of the third node D.
Preferably, in an implementation of the shift register provided in the embodiment of the present invention, as shown in fig. 4a and 4b, the second control module 7 may specifically include: a fourteenth switching transistor M14, a fifteenth switching transistor M15, a sixteenth switching transistor M16, a seventeenth switching transistor M17, and an eighteenth switching transistor M18; wherein the content of the first and second substances,
a fourteenth switching transistor M14 having a gate and a first pole both connected to the third reference signal terminal Vref3, and a second pole respectively connected to the first pole of the sixteenth switching transistor M16 and the gate of the fifteenth switching transistor M15;
a fifteenth switching transistor M15 having a first pole connected to the third reference signal terminal Vref3 and a second pole connected to the third node D;
a sixteenth switching transistor M16 having a gate connected to the first node a and a second pole connected to the first reference signal terminal Vref 1;
a seventeenth switching transistor M17 having a gate connected to the first node a, a first pole connected to the third node D, and a second pole connected to the first reference signal terminal Vref 1;
and an eighteenth switching transistor M18 having a gate connected to the third node D, a first pole connected to the first node a, and a second pole connected to the first reference signal terminal Vref 1.
Specifically, in practical implementation, as shown in fig. 4a, the fourteenth to eighteenth switching transistors M14 to M18 may be N-type transistors, or as shown in fig. 4b, the fourteenth to eighteenth switching transistors M14 to M18 may also be P-type transistors, which is not limited herein.
In a specific implementation, the signal of the third reference signal terminal Vref3 and the signal of the second reference signal terminal Vref2 are clock signals with opposite phases, and the period of the clock signals may be the same as or different from the period of the signal of the first clock signal terminal CLK1, which is not limited herein.
The above is merely an example of the specific structure of the second control module in the shift register, and in the specific implementation, the specific structure of the second control module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
Preferably, in the shift register according to the embodiment of the present invention, as shown in fig. 4a and 4b, the second output module 8 specifically includes: a nineteenth switching transistor M19; wherein the content of the first and second substances,
a nineteenth switching transistor M19 has a gate connected to the third node D, a first pole connected to the gate signal Output terminal Output of the shift register, and a second pole connected to the first reference signal terminal Vref 1.
Specifically, in practical implementation, as shown in fig. 4a, the nineteenth switching transistor M19 may be an N-type transistor, or as shown in fig. 4b, the nineteenth switching transistor M19 may also be a P-type transistor, which is not limited herein.
The above is merely an example of the specific structure of the second output module in the shift register, and in the specific implementation, the specific structure of the second output module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
It should be noted that the switching Transistor mentioned in the above embodiments of the present invention may be a Thin Film Transistor (TFT) or a Metal oxide semiconductor field effect Transistor (MOS), and is not limited herein. In a specific implementation, the first pole and the second pole of the switching transistors can be interchanged in function according to the type of the transistor and the input signal, and are not particularly distinguished here.
The operation of the shift register shown in fig. 4a, in which all the switching transistors are N-type, will be described in detail. In the following description, a high potential signal is denoted by 1, and a low potential signal is denoted by 0.
In the shift register shown in fig. 4a, all transistors are N-type transistors, and each N-type transistor is turned on under the action of a high potential and turned off under the action of a low potential; the signal of the first reference signal terminal is a low signal, and the corresponding input/output timing diagram is shown in fig. 5 a. Specifically, five stages of T1, T2, T3, T4, and T5 in the input-output timing diagram shown in fig. 5a are selected.
At stage T1, Input is 1, CLK1 is 0, CLK2 is from low to high, Vref2 is 1, Vref3 is 0, and Reset is 0. Since Vref2 is equal to 1 and Vref3 is equal to 0, the tenth switching transistor M10 and the eleventh switching transistor M11 are both turned on at the beginning, and the fourteenth switching transistor M14 and the fifteenth switching transistor M15 are both turned off. Since Input is 1, the fifth switching transistor M5 is turned on, a signal of the Input signal terminal Input at a high potential is transmitted to the first node a through the fifth switching transistor M5, the potential of the first node a is a high potential, both the twelfth switching transistor M12 and the thirteenth switching transistor M13 are turned on, so that the eleventh switching transistor M11 is turned off, a signal of the first reference signal terminal Vref1 at a low potential is transmitted to the second node B through the thirteenth switching transistor M13, the potential of the second node B is a low potential, and since the potential of the first node a is a high potential, the capacitor C starts to be charged, the seventh switching transistor M7 is turned on, a signal of the first clock signal terminal CLK1 at a low potential is Output to the gate signal terminal Output through the seventh switching transistor M7, and thus the gate signal terminal Output a low potential signal.
At stage T2, Input is 0, CLK is 1, CLK2 goes from high to low, Vref2 is 0, Vref3 is 1, and Reset is 0. According to the function of the capacitor, the potential of the first node a is further pulled high, the sixteenth switching transistor M16 and the seventeenth switching transistor M17 are both turned on, so that the fifteenth switching transistor M15 is turned off, the potential of the third node D is low, and since the potential of the first node a is high, the seventh switching transistor M7 is turned on, the signal of the clock signal terminal CLK at high potential is Output to the gate signal Output terminal Output through the seventh switching transistor M7, and therefore, the gate signal Output terminal Output outputs a high potential signal.
Assuming that the Input is high at this stage, the second switching transistor M2 and the fourth switching transistor M4 are both turned on, the potential of the first node a is high, and the Input/output timing diagram is shown in fig. 5 b; since the CLK2 goes from high to low, when the CLK2 goes high, the first switching transistor M1 and the third switching transistor M3 are both turned on, so that the signal of the first reference signal terminal Vref1 with low potential is transmitted to the first node a through the first switching transistor M1 and the second switching transistor M2, and is transmitted to the gate signal Output terminal Output through the third switching transistor M3 and the fourth switching transistor M4, the potentials of the first node a and the gate signal Output terminal Output are both pulled low, because in normal condition, when the CLK2 goes high, the gate signal Output terminal Output should Output a high potential signal, but at this time, a low potential signal is Output, but because the signal of the gate signal Output terminal Output is determined by the signal of the first clock signal terminal CLK1, when an abnormality occurs in the CLK2, the Output of the shift register at this stage is only abnormal, and the Output of the shift register at the latter stage is reset by the first clock signal of the first clock signal terminal CLK1, the normal output is recovered, and only this line of abnormality occurs within one frame time, which is short and is not noticeable to the human eye, and it is not necessary that the abnormality occurs at the high potential stage of CLK 2.
At stage T3, Input is 0, CLK1 is 0, CLK2 goes from low to high, Vref2 is 1, Vref3 is 0, and Reset is 1. Since Reset is 1, a signal of the first reference voltage terminal Vref1 having a low potential is Output to the first node a through the sixth switching transistor M6, the potential of the first node a is a low potential, since Vref2 is 1, the tenth switching transistor M10 and the eleventh switching transistor M11 are turned on, the potential of the second node B is a high potential, the eighth switching transistor M8 and the ninth switching transistor M9 are turned on, a signal of the first reference signal terminal Vref1 having a low potential is Output to the gate signal Output terminal Output through the eighth switching transistor M8, and thus the gate signal Output terminal Output outputs a low potential signal.
Assuming that the Input is high at this stage, the second switching transistor M2 and the fourth switching transistor M4 are both turned on, the potential of the first node a is high, and the Input/output timing diagram is shown in fig. 5 c; since the CLK2 goes from low to high, at this stage, when the CLK2 goes low, the first switching transistor M1 and the third switching transistor M3 are both turned off, and since the CLK1 is equal to 0, the gate signal Output terminal Output outputs a low-level signal; when the CLK2 is at a high level, the first switching transistor M1 and the third switching transistor M3 are both turned on, so that a signal of the first reference signal terminal Vref1 at a low level is transmitted to the first node a through the first switching transistor M1 and the second switching transistor M2, the potential of the first node a is pulled down, and the seventh switching transistor M7 is in a turned-off state, thereby ensuring that the gate signal Output terminal Output outputs normally.
At stage T4, Input is 0, CLK is 1, CLK2 goes from high to low, Vref2 is 0, Vref3 is 1, and Reset is 0. Since Vref3 is equal to 1, both the fourteenth switching transistor M14 and the fifteenth switching transistor M15 are turned on. Since Input is 0, the potential of the first node a is at a low potential, the seventh switching transistor M7, the twelfth switching transistor M12, and the thirteenth switching transistor M13 are all turned off, the potential of the third node D is at a high potential, the eighteenth switching transistor M18 and the nineteenth switching transistor M19 are all turned on, and a signal of the first reference signal terminal Vref1 at a low potential is transmitted to the first node a and the gate signal Output terminal Output through the eighteenth switching transistor M18 and the nineteenth switching transistor M19, so that noise is released from the first node a and the gate signal Output terminal Output, and therefore, the gate signal Output terminal Output outputs a low potential signal.
Assuming that the Input is high at this stage, the second switching transistor M2 and the fourth switching transistor M4 are both turned on, the potential of the first node a is high, and the Input/output timing diagram is shown in fig. 5 d; since the CLK2 goes from high to low, at this stage, when the CLK2 goes high, the first switching transistor M1 and the third switching transistor M3 are both turned on, so that the signal of the first reference signal terminal Vref1 with low potential is transmitted to the first node a through the first switching transistor M1 and the second switching transistor M2, the potential of the first node a is pulled low, so that noise reduction can be performed on the first node a, the signal of the first reference signal terminal Vref1 with low potential is transmitted to the gate signal Output terminal Output through the third switching transistor M3 and the fourth switching transistor M4, and the gate signal Output terminal Output normally outputs low potential; when the CLK2 is at a low level, the first switching transistor M1 and the third switching transistor M3 are both turned off, and although the first node a is at a high level at the beginning of this stage due to an input abnormality, Reset is exactly the Reset stage for the next-stage shift register at this stage, so that the signal of the first reference voltage terminal Vref1 at the low level is Output to the first node a through the sixth switching transistor M6, the potential of the first node a is pulled down, and the gate signal Output terminal Output of the next stage still outputs a low-level signal normally, that is, only the Output of the first-stage shift register has an abnormality and does not affect the normal Output of the other stages of shift registers.
At stage T5, Input is 0, CLK2 goes from low to high, Vref2 is 1, Vref3 is 0, and Reset is 0. Since Vref2 is equal to 1, both the tenth switching transistor M10 and the eleventh switching transistor M11 are turned on. Since Input is equal to 0, the potential of the first node a is still at a low potential, the seventh switching transistor M7, the twelfth switching transistor M12 and the thirteenth switching transistor M13 are all turned off, the potential of the second node B is at a high potential, the eighth switching transistor M8 and the ninth switching transistor M9 are all turned on, and the signal of the first reference signal terminal Vref1 at the low potential is transmitted to the gate signal Output terminal Output and the first node a through the eighth switching transistor M8 and the ninth switching transistor M9, so that noise is released from the first node a and the gate signal Output terminal Output, and therefore, the gate signal Output terminal Output outputs a low potential signal.
Assuming that the Input is high at this stage, the second switching transistor M2 and the fourth switching transistor M4 are both turned on, the potential of the first node a is high, and the Input/output timing diagram is shown in fig. 5 e; since the CLK2 goes from low to high, at this stage, when the CLK2 goes low, the first switching transistor M1 and the third switching transistor M3 are both turned off, but since the CLK is equal to 0, the gate signal Output terminal Output normally outputs a low-level signal; when the CLK2 is at a high level, the first switching transistor M1 and the third switching transistor M3 are both turned on, so that a signal of the first reference signal terminal Vref1 at a low level is transmitted to the first node a through the first switching transistor M1 and the second switching transistor M2, and the potential of the first node a is pulled down, so that the first node a can be denoised and the gate signal Output terminal Output is normally Output.
The period T5 is maintained until the next frame arrives, the potential at the first node a is at the low potential, and the potential at the second node B is at the high potential until the signal at the Input signal terminal Input of the next frame becomes the high potential.
In summary, the shift register provided in the embodiments of the present invention can not only achieve the normal Output function of the conventional shift register, but also transmit the signal of the first reference signal end to the first node and the gate signal Output end through the first noise reduction module under the combined action of the signal of the input signal end and the signal of the second clock signal end to pull down the potential of the first node even when the input is high at a certain stage, so as to avoid the problem that the display panel is scrapped due to the failure of part of the switching transistors caused by the long-time on state of the switching transistors when the input of the shift register is high, unlike the conventional shift register which makes the first node always be high when the input is high. In addition, even when the input is high when the second clock signal of the second clock signal terminal CLK2 is high in the stage T2, the output of the shift register is not normal at this stage, the output of the shift register after that is reset by the first clock signal of the first clock signal terminal CLK1, and the normal output is recovered, and only the line is abnormal within one frame time, the time is short, the line is not noticeable to human eyes, and the line is not necessarily abnormal when the second clock signal of the second clock signal terminal CLK2 is high; when the second clock signal at the second clock signal terminal CLK2 is at the low level and the input is high at the stage T4, although the first node a is at the high level at the beginning of this stage due to the input abnormality, this stage is just the Reset stage, i.e., Reset is equal to 1, for the next-stage shift register, so the signal at the low level of the first reference voltage terminal Vref1 can pull down the potential of the first node a, and therefore the next-stage gate signal Output terminal Output is still outputting the low-level signal normally, i.e., only the first-stage shift register Output has abnormality and does not affect the normal Output of the other shift registers.
Based on the same inventive concept, an embodiment of the present invention further provides a gate driving circuit, as shown in fig. 6, including a plurality of cascaded shift registers provided in the embodiment of the present invention: SR (1), SR (2) … SR (N-1), SR (N) … SR (N-1), SR (N) (N shift registers in total, N is more than or equal to 1 and less than or equal to N, N is a positive integer), an Input signal end Input _1 of the first stage shift register SR (1) is connected with a frame trigger signal end STV, except for the first stage shift register SR (1), an Input signal end Input _ N of each stage of shift register SR (N) is connected with a gate signal Output end Output _ N-1 of the adjacent previous stage shift register SR (N-1); except for the last stage of shift register SR (n), the Reset signal terminal Reset of each stage of shift register SR (n-1) is connected to the gate signal Output terminal Output _ n of the next stage of shift register SR (n) adjacent thereto.
Specifically, each shift register in the gate driving circuit is identical to the shift register provided in the embodiment of the present invention in function and structure, and repeated descriptions are omitted.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the gate driving circuit. The display device may be: the display panel of any product with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The implementation of the display device can be seen in the embodiments of the gate driving circuit, and repeated descriptions are omitted.
The embodiment of the invention provides a shift register, a grid drive circuit and a display device, wherein the shift register comprises: the device comprises an input module, a reset module, a first control module, a first output module and a first noise reduction module; the input module is used for controlling the potential of the first node according to an input signal of the input signal end; the reset module is used for providing a signal of the first reference signal terminal to the first node under the control of the reset signal terminal; the first control module is used for controlling the electric potentials of the first node and the second node; the first output module is used for providing a first clock signal of a first clock signal end to a grid signal output end of the shift register under the control of a first node and providing a signal of a first reference signal end to the grid signal output end of the shift register under the control of a second node; the first noise reduction module is used for providing a signal of a first reference signal end to a first node under the common control of an input signal of the input signal end and a second clock signal of a second clock signal end; the second clock signal has the same clock period as the first clock signal, and the phase difference between the second clock signal and the first clock signal is 4 pi/3. The shift register is matched with the five modules, when an input signal is normal within a frame time, the first noise reduction module is in a non-working state, and normal output of the shift register is not influenced; when at least two effective pulses appear in an input signal within a frame time, the first noise reduction module can provide a signal of the first reference signal end to the first node under the combined action of the signal of the input signal end and the second clock signal, and pull down the potential of the first node, so that the noise of the grid signal output end can be eliminated, and the stability of the signal output by the grid signal output end is ensured.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (13)
1. A shift register, comprising: the device comprises an input module, a reset module, a first control module, a first output module and a first noise reduction module; wherein the content of the first and second substances,
the input module is used for controlling the potential of the first node according to an input signal of the input signal end;
the reset module is used for providing a signal of a first reference signal terminal to the first node under the control of a reset signal terminal;
the first control module is used for controlling the potentials of the first node and the second node;
the first output module is used for providing a first clock signal of a first clock signal end to the grid signal output end of the shift register under the control of the first node and providing a signal of the first reference signal end to the grid signal output end of the shift register under the control of the second node;
the first noise reduction module is used for providing a signal of the first reference signal end to the first node under the common control of an input signal of the input signal end and a second clock signal of a second clock signal end;
the second clock signal has the same clock period as the first clock signal, and the phase difference between the second clock signal and the first clock signal is 4 pi/3.
2. The shift register of claim 1, wherein the first noise reduction module comprises: a first switching transistor and a second switching transistor; wherein the content of the first and second substances,
the grid electrode of the first switching transistor is connected with the second clock signal end, the first pole of the first switching transistor is connected with the first node, and the second pole of the first switching transistor is connected with the first pole of the second switching transistor;
and the grid electrode of the second switching transistor is connected with the input signal end, and the second pole of the second switching transistor is connected with the first reference signal end.
3. The shift register of claim 1, further comprising: a second noise reduction module; wherein the content of the first and second substances,
the second noise reduction module is used for providing the signal of the first reference signal end to the grid signal output end of the shift register under the common control of the input signal end and the second clock signal of the second clock signal end.
4. The shift register of claim 3, wherein the second noise reduction module comprises: a third switching transistor and a fourth switching transistor; wherein the content of the first and second substances,
the grid electrode of the third switching transistor is connected with the second clock signal end, the first electrode of the third switching transistor is connected with the grid signal output end of the shift register, and the second electrode of the third switching transistor is connected with the first electrode of the fourth switching transistor;
and the grid electrode of the fourth switching transistor is connected with the input signal end, and the second pole of the fourth switching transistor is connected with the first reference signal end.
5. The shift register of any one of claims 1-4, wherein the input module comprises: a fifth switching transistor; wherein the content of the first and second substances,
and the grid electrode and the first electrode of the fifth switching transistor are both connected with the input signal end, and the second electrode of the fifth switching transistor is connected with the first node.
6. The shift register of any of claims 1-4, wherein the reset module comprises: a sixth switching transistor; wherein the content of the first and second substances,
and the grid electrode of the sixth switching transistor is connected with the reset signal end, the first pole of the sixth switching transistor is connected with the first node, and the second pole of the sixth switching transistor is connected with the first reference signal end.
7. The shift register of any of claims 1-4, wherein the first output module comprises: a seventh switching transistor, an eighth switching transistor, and a capacitor; wherein the content of the first and second substances,
a gate of the seventh switching transistor is connected to the first node, a first pole of the seventh switching transistor is connected to the first clock signal terminal, and a second pole of the seventh switching transistor is connected to a gate signal output terminal of the shift register;
a gate of the eighth switching transistor is connected to the second node, a first pole of the eighth switching transistor is connected to a gate signal output end of the shift register, and a second pole of the eighth switching transistor is connected to the first reference signal end;
the capacitor is connected between the gate and the second pole of the seventh switching transistor.
8. The shift register of any one of claims 1-4, wherein the first control module comprises: a ninth switching transistor, a tenth switching transistor, an eleventh switching transistor, a twelfth switching transistor, and a thirteenth switching transistor; wherein the content of the first and second substances,
a gate of the ninth switching transistor is connected to the second node, a first pole of the ninth switching transistor is connected to the first node, and a second pole of the ninth switching transistor is connected to the first reference signal terminal;
a gate and a first pole of the tenth switching transistor are both connected to the second reference signal terminal, and a second pole of the tenth switching transistor is respectively connected to the first pole of the twelfth switching transistor and the gate of the eleventh switching transistor;
a first terminal of the eleventh switching transistor is connected to the second reference signal terminal, and a second terminal thereof is connected to the second node;
a gate of the twelfth switching transistor is connected to the first node, and a second pole of the twelfth switching transistor is connected to the first reference signal terminal;
and the gate of the thirteenth switching transistor is connected with the first node, the first pole of the thirteenth switching transistor is connected with the second node, and the second pole of the thirteenth switching transistor is connected with the first reference signal end.
9. The shift register of claim 8, further comprising: the second control module and the second output module; wherein the content of the first and second substances,
the second control module is used for controlling the electric potentials of the first node and the third node;
the second output module is used for providing the signal of the first reference signal end to the grid signal output end of the shift register under the control of the third node.
10. The shift register of claim 9, wherein the second control module comprises: a fourteenth switching transistor, a fifteenth switching transistor, a sixteenth switching transistor, a seventeenth switching transistor, and an eighteenth switching transistor; wherein the content of the first and second substances,
a gate and a first pole of the fourteenth switching transistor are both connected to a third reference signal terminal, and a second pole of the fourteenth switching transistor is respectively connected to the first pole of the sixteenth switching transistor and the gate of the fifteenth switching transistor;
a first pole of the fifteenth switching transistor is connected with the third reference signal terminal, and a second pole of the fifteenth switching transistor is connected with the third node;
a gate of the sixteenth switching transistor is connected to the first node, and a second pole of the sixteenth switching transistor is connected to the first reference signal terminal;
a gate of the seventeenth switching transistor is connected to the first node, a first pole of the seventeenth switching transistor is connected to the third node, and a second pole of the seventeenth switching transistor is connected to the first reference signal terminal;
and the gate of the eighteenth switching transistor is connected with the third node, the first pole of the eighteenth switching transistor is connected with the first node, and the second pole of the eighteenth switching transistor is connected with the first reference signal end.
11. The shift register of claim 9, wherein the second output module comprises: a nineteenth switching transistor; wherein the content of the first and second substances,
and the gate of the nineteenth switching transistor is connected with the third node, the first pole of the nineteenth switching transistor is connected with the gate signal output end of the shift register, and the second pole of the nineteenth switching transistor is connected with the first reference signal end.
12. A gate driver circuit comprising a plurality of shift registers according to any one of claims 1 to 11 in cascade; wherein the content of the first and second substances,
except the first stage of shift register, the input signal end of each stage of shift register is connected with the grid signal output end of the adjacent previous stage of shift register;
except the last stage of shift register, the reset signal end of each stage of shift register is connected with the grid signal output end of the next stage of shift register adjacent to the reset signal end of each stage of shift register.
13. A display device comprising the gate driver circuit according to claim 12.
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