CN106652875A - Shifting register, driving method thereof, grid integrated drive circuit and display device - Google Patents
Shifting register, driving method thereof, grid integrated drive circuit and display device Download PDFInfo
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- CN106652875A CN106652875A CN201710005646.2A CN201710005646A CN106652875A CN 106652875 A CN106652875 A CN 106652875A CN 201710005646 A CN201710005646 A CN 201710005646A CN 106652875 A CN106652875 A CN 106652875A
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- 230000002159 abnormal effect Effects 0.000 abstract description 6
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- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 18
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 17
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Shift Register Type Memory (AREA)
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Abstract
The invention discloses a shifting register, a driving method of the shifting register, a grid integrated drive circuit and a display device. A noise reducing module is additionally arranged in the existing shifting register, under the control of effective pulse signals input by a signal input end, the noises of a signal output end are eliminated by utilizing a reference signal end; meanwhile, in the grid integrated drive circuit composed of a plurality of cascaded shifting registers provided by the embodiment of the invention, by utilizing the connecting relation between the noise reducing modules of the shifting registers of different levels and signal output ends, when the output of the signal output end of one shifting register is abnormal, the noises can be coupled to the noise reducing module of the shifting register adjacent to the abnormal shifting register, the noises are then coupled and released to the reference signal end through the noise reducing module and are finally eliminated, therefore, the noises of the signal output ends of the shifting registers of different levels are cancelled out, and meanwhile, while the denoising capacity of the shifting registers is improved, the stability of grid scanning signals output by the grid integrated drive circuit is improved.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, a gate integrated driving circuit and a display device.
Background
The gate on array (goa) is a technology for integrating a gate integrated driving circuit on a thin film transistor substrate, and the gate integrated driving circuit provides gate scanning signals to the gates of the thin film transistors in a pixel region, and turns on the thin film transistors row by row, so as to input data signals of the pixel unit.
In the prior art, the shift register as a component of the gate integrated driving circuit has a basic structure as shown in fig. 1a, and includes 15 thin film transistors, namely, a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6, a seventh thin film transistor M7, and an eighth thin film transistor M8, a ninth thin film transistor M9, a tenth thin film transistor M10, an eleventh thin film transistor M11, a twelfth thin film transistor M12, a thirteenth thin film transistor M13, a fourteenth thin film transistor M14, a fifteenth thin film transistor M15, a storage capacitor C, a clock signal terminal CLK, two control signal terminals VDD1 and VDD2, a signal INPUT terminal INPUT, a RESET signal terminal RESET, a reference signal terminal VSS, and a signal output terminal G [ N ].
In addition, the structure of the gate integrated driving circuit composed of cascaded shift registers is shown in fig. 1b, and the signal output terminal of the nth stage shift register outputs a gate scan signal and simultaneously provides a reset signal to the reset signal terminal of the (N + 2) th stage shift register and simultaneously provides an effective pulse signal to the signal input terminal of the (N-1) th stage shift register.
In general, for a row of pixels of the display panel, most of the time in a frame is the holding state of the pixel voltage, i.e., the potential output by the signal output terminal G [ N ] of the shift register is kept at a low level; meanwhile, for the gate integrated drive circuit, if a signal output by the signal output end of one shift register is abnormal, the signal output ends of the upper and lower shift registers connected with the shift register can be abnormal in output; therefore, it is particularly important to improve the noise removal capability of the shift register.
Therefore, it is an urgent technical problem to be solved by those skilled in the art how to improve the noise removing capability of the shift register.
Disclosure of Invention
The shift register, the driving method thereof, the gate integrated driving circuit and the display device provided by the embodiment of the invention are used for improving the noise removing capability of the shift register and improving the stability of the gate scanning signal output by the shift register.
An embodiment of the present invention provides a shift register, including: the input module is connected between a signal input end and a first node and is used for providing an effective pulse signal to the first node under the control of the effective pulse signal input by the signal input end; the output control module is connected among the first node, the clock signal end and the signal output end and is used for providing the clock signal of the clock signal end to the signal output end under the control of the first node; the reset module is connected among a reset signal end, a reference signal end and the first node and is used for providing a reference signal of the reference signal end to the first node under the control of the reset signal end; further comprising:
and the noise reduction module is connected among the signal input end, the reference signal end and the signal output end and is used for providing a reference signal of the reference signal end to the signal output end under the control of an effective pulse signal input by the signal input end.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the noise reduction module includes: a first thin film transistor; wherein,
and the grid electrode of the first thin film transistor is connected with the signal input end, the source electrode of the first thin film transistor is connected with the reference signal end, and the drain electrode of the first thin film transistor is connected with the signal output end.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the input module includes: a second thin film transistor; wherein,
and the grid electrode and the source electrode of the second thin film transistor are both connected with the signal input end, and the drain electrode of the second thin film transistor is connected with the first node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the output control module includes: a third thin film transistor and a capacitor; wherein,
the grid electrode of the third thin film transistor is connected with the first node, the source electrode of the third thin film transistor is connected with the clock signal end, and the drain electrode of the third thin film transistor is connected with the signal output end;
the capacitor is connected between the first node and the signal output end.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the reset module includes: a fourth thin film transistor; wherein,
and the grid electrode of the fourth thin film transistor is connected with the reset signal end, the source electrode of the fourth thin film transistor is connected with the reference signal end, and the drain electrode of the fourth thin film transistor is connected with the first node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the shift register further includes:
a first pull-down control module connected among a first control signal terminal, the first node, the reference signal terminal, and the signal output terminal, and configured to provide a reference signal of the reference signal terminal to a second node under the control of the first node, and provide reference signals of the reference signal terminal to the first node and the signal output terminal, respectively, when the second node is a first control signal input by the first control signal terminal;
a second pull-down control module connected among a second control signal terminal, the first node, the reference signal terminal, and the signal output terminal, and configured to provide a reference signal of the reference signal terminal to a fourth node under the control of the first node, and provide reference signals of the reference signal terminal to the first node and the signal output terminal, respectively, when the fourth node is a second control signal input by the second control signal terminal;
the first control signal end and the second control signal end alternately input control signals.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the first pull-down control module includes: a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, and a tenth thin film transistor; wherein,
the grid electrode and the source electrode of the fifth thin film transistor are both connected with the first control signal end, and the drain electrode of the fifth thin film transistor is connected with the third node;
a grid electrode of the sixth thin film transistor is connected with the third node, a source electrode of the sixth thin film transistor is connected with the first control signal end, and a drain electrode of the sixth thin film transistor is connected with the second node;
a grid electrode of the seventh thin film transistor is connected with the first node, a source electrode of the seventh thin film transistor is connected with the reference signal end, and a drain electrode of the seventh thin film transistor is connected with the third node;
a grid electrode of the eighth thin film transistor is connected with the first node, a source electrode of the eighth thin film transistor is connected with the reference signal end, and a drain electrode of the eighth thin film transistor is connected with the second node;
a grid electrode of the ninth thin film transistor is connected with the second node, a source electrode of the ninth thin film transistor is connected with the reference signal end, and a drain electrode of the ninth thin film transistor is connected with the first node;
a grid electrode of the tenth thin film transistor is connected with the second node, a source electrode of the tenth thin film transistor is connected with the reference signal end, and a drain electrode of the tenth thin film transistor is connected with the signal output end;
the second pull-down control module comprising: an eleventh thin film transistor, a twelfth thin film transistor, a thirteenth thin film transistor, a fourteenth thin film transistor, a fifteenth thin film transistor, and a sixteenth thin film transistor; wherein,
a grid electrode and a source electrode of the eleventh thin film transistor are both connected with the second control signal end, and a drain electrode of the eleventh thin film transistor is connected with a fifth node;
a grid electrode of the twelfth thin film transistor is connected with the fifth node, a source electrode of the twelfth thin film transistor is connected with the second control signal end, and a drain electrode of the twelfth thin film transistor is connected with the fourth node;
a gate of the thirteenth thin film transistor is connected to the first node, a source of the thirteenth thin film transistor is connected to the reference signal terminal, and a drain of the thirteenth thin film transistor is connected to the fifth node;
a grid electrode of the fourteenth thin film transistor is connected with the first node, a source electrode of the fourteenth thin film transistor is connected with the reference signal end, and a drain electrode of the fourteenth thin film transistor is connected with the fourth node;
a grid electrode of the fifteenth thin film transistor is connected with the fourth node, a source electrode of the fifteenth thin film transistor is connected with the reference signal end, and a drain electrode of the fifteenth thin film transistor is connected with the first node;
and the grid electrode of the sixteenth thin film transistor is connected with the fourth node, the source electrode of the sixteenth thin film transistor is connected with the reference signal end, and the drain electrode of the sixteenth thin film transistor is connected with the signal output end.
The embodiment of the invention also provides a grid integrated driving circuit, which comprises a plurality of cascaded shift registers provided by the embodiment of the invention; wherein,
and the signal output end of the Nth-stage shift register inputs a reset signal to the reset signal end of the (N + 1) th-stage shift register, or inputs a reset signal to the reset signal end of the (N + 2) th-stage shift register, and inputs an effective pulse signal to the signal input end of the (N-1) th-stage shift register, wherein N is an integer greater than 1.
The embodiment of the invention also provides a display device which comprises the grid integrated drive circuit provided by the embodiment of the invention.
The embodiment of the present invention further provides a driving method of the shift register provided in the embodiment of the present invention, including:
in a first time period, the input module provides an effective pulse signal of a signal input end to a first node under the control of the effective pulse signal input by the signal input end; the noise reduction module is used for providing a reference signal of a reference signal end to a signal output end under the control of the effective pulse signal input by the signal input end;
in a second time period, the output control module provides a clock signal of a clock signal end to the signal output end under the control of the first node;
in a fourth time period, the reset module provides the reference signal of the reference signal terminal to the first node under the control of the reset signal terminal.
The invention has the following beneficial effects:
the shift register comprises an input module, a first node and a second node, wherein the input module is used for providing an effective pulse signal to the first node under the control of the effective pulse signal input by a signal input end; the output control module is used for providing a clock signal of the clock signal end to the signal output end under the control of the first node; the reset module is used for providing a reference signal of a reference signal end to a first node under the control of a reset signal end; the noise reduction module is connected among the signal input end, the reference signal end and the signal output end and used for providing a reference signal of the reference signal end to the signal output end under the control of an effective pulse signal input by the signal input end; therefore, by additionally arranging a noise reduction module in the existing shift register, under the control of an effective pulse signal input by a signal input end, the noise interference on a signal output end is reduced by using a reference signal of a reference signal end; meanwhile, in the gate integrated drive circuit composed of a plurality of cascaded shift registers provided by the embodiments of the present invention, by using the connection relationship between the noise reduction module in each shift register and the signal output terminal of each shift register, when the signal output terminal of one shift register is abnormal, noise can be coupled to the noise reduction module in the shift register adjacent to the shift register, and the noise coupling is released to the reference signal terminal through the noise reduction module, so as to eliminate noise, so that the noise at the signal output terminals of each shift register is cancelled, and the stability of the gate scanning signal output by the gate integrated drive circuit is improved while the capability of removing noise of the shift register is improved.
Drawings
FIG. 1a is a schematic diagram of a shift register in the prior art;
FIG. 1b is a schematic diagram of a gate integrated driving circuit in the prior art;
fig. 2a to 2d are schematic structural diagrams of a shift register according to an embodiment of the present invention;
FIG. 3 is a timing diagram of an input/output of a shift register according to an embodiment of the present invention;
FIGS. 4a and 4b are schematic diagrams illustrating simulation results of signals output from signal output terminals of a shift register according to an embodiment of the present invention and a shift register in the prior art;
fig. 5 is a schematic structural diagram of a gate integrated driving circuit according to an embodiment of the present invention;
fig. 6 is a schematic diagram illustrating a connection relationship between a signal output end of each shift register stage and an equivalent capacitor of a noise reduction module according to an embodiment of the present invention.
Detailed Description
The following describes in detail specific embodiments of a shift register, a driving method thereof, a gate integrated driving circuit, and a display device according to embodiments of the present invention with reference to the accompanying drawings.
An embodiment of the present invention provides a shift register, as shown in fig. 2a, which may include: an INPUT block 10 connected between the signal INPUT terminal INPUT and a first node P1, for providing an effective pulse signal to the first node P1 under the control of the effective pulse signal inputted from the signal INPUT terminal INPUT; an output control module 20 connected between the first node P1, the clock signal terminal CLK, and the signal output terminal G [ N ], for providing the clock signal of the clock signal terminal CLK to the signal output terminal G [ N ] under the control of the first node P1; a RESET module 30 connected between the RESET signal terminal RESET, the reference signal terminal VSS, and the first node P1, for providing a reference signal of the reference signal terminal VSS to the first node P1 under the control of a RESET signal of the RESET signal terminal RESET; the method can also comprise the following steps:
and a noise reduction module 40 connected between the signal INPUT terminal INPUT, the reference signal terminal VSS, and the signal output terminal gn, for providing a reference signal of the reference signal terminal VSS to the signal output terminal gn under the control of the active pulse signal INPUT from the signal INPUT terminal INPUT.
In the shift register provided by the embodiment of the invention, the noise reduction module 40 is additionally arranged among the signal INPUT end INPUT, the reference signal end VSS and the signal output end GN in the existing shift register, and the reference signal of the reference signal end VSS is utilized under the control of the effective pulse signal INPUT by the signal INPUT end INPUT to reduce the noise interference on the signal output end GN, improve the noise removal capability of the shift register and further improve the stability of the grid scanning signal output by the shift register.
Specifically, the active pulse signal and the clock signal are high level signals, the potential of the first node P1 is high level, and the reference signal is a low level signal; alternatively, the active pulse signal and the clock signal are low level signals, the potential of the first node P1 is low level, and the reference signal is a high level signal.
In a specific implementation, in order to eliminate noise interference at the signal output terminal G [ N ], in the shift register provided in the embodiment of the present invention, as shown in fig. 2b, the noise reduction module 40 may specifically include: a first thin film transistor M1; wherein,
the first TFT M1 has a gate connected to the signal INPUT terminal INPUT, a source connected to the reference signal terminal VSS, and a drain connected to the signal output terminal GN.
Specifically, the first thin film transistor M1 outputs the reference signal of the reference signal terminal VSS to the signal output terminal G [ N ] under the control of the active pulse signal inputted from the signal INPUT terminal INPUT.
Further, in order to greatly improve the noise reduction capability of the noise reduction module 40, in the shift register provided in the embodiment of the present invention, the resistance of the first thin film transistor M1 in the noise reduction module 40 needs to be determined according to the load in the pixel region, that is, the resistance of the first thin film transistor M1 needs to be adjusted according to the parasitic capacitance between the gate line and the signal line in the pixel region and the resistance of the gate line, so that the noise reduction capability of the noise reduction module 40 is maximized, and the stability of the gate scan signal output by the shift register is ensured.
Specifically, the first thin film transistor M1 may be a P-type thin film transistor, or an N-type thin film transistor, as shown in fig. 2b, which is not limited herein. When the first thin film transistor M1 is a P-type thin film transistor, the effective pulse signal INPUT by the signal INPUT terminal INPUT needs to be a low level signal; when the first thin film transistor M1 is an N-type thin film transistor, the active pulse signal inputted from the signal INPUT terminal INPUT needs to be a high level signal.
The above is only an example of the specific structure of the noise reduction module 40, and in the specific implementation, the specific structure of the noise reduction module 40 is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known by those skilled in the art, which are not described herein again.
In practical implementation, in order to provide the valid pulse signal at the signal INPUT terminal INPUT to the first node P1, in the shift register provided in the embodiment of the present invention, as shown in fig. 2b, the INPUT module 10 may specifically include: a second thin film transistor M2; wherein,
the gate and source of the second thin film transistor M2 are connected to the signal INPUT terminal INPUT, and the drain is connected to the first node P1.
Specifically, the second thin film transistor M2 outputs an active pulse signal to the first node P1 under the control of the active pulse signal INPUT from the signal INPUT terminal INPUT.
Specifically, the second thin film transistor M2 may be a P-type thin film transistor or an N-type thin film transistor, as shown in fig. 2b, which is not limited herein. When the second thin film transistor M2 is a P-type thin film transistor, the effective pulse signal INPUT by the signal INPUT terminal INPUT needs to be a low level signal; when the second thin film transistor M2 is an N-type thin film transistor, the active pulse signal inputted from the signal INPUT terminal INPUT needs to be a high level signal.
The above is only an example of the specific structure of the input module 10, and in the specific implementation, the specific structure of the input module 10 is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known by those skilled in the art, which are not described herein again.
In a specific implementation, in order to realize that the signal output terminal G [ N ] outputs the gate scan signal, as shown in fig. 2b, in the shift register provided in the embodiment of the present invention, the output control module 20 may specifically include: a third thin film transistor M3, and a capacitor C; wherein,
a gate of the third thin film transistor M3 is connected to the first node P1, a source thereof is connected to the clock signal terminal CLK, and a drain thereof is connected to the signal output terminal gn;
the capacitor C is connected between the first node P1 and the signal output terminal G [ N ].
Specifically, the third tft M3 outputs a clock signal from the clock signal terminal CLK to the signal output terminal gn under the control of the first node P1, so that the signal output terminal gn outputs a gate scan signal, and through the nth row of gate lines corresponding to the shift register, all tfts in the display region of the liquid crystal panel on the nth row of gate lines are turned on, and the data line starts to write a signal.
Specifically, the third thin film transistor M3 may be a P-type thin film transistor or an N-type thin film transistor, as shown in fig. 2b, which is not limited herein. When the third thin film transistor M3 is a P-type thin film transistor, the potential of the first node P1 needs to be low; when the third thin film transistor M3 is an N-type thin film transistor, the potential of the first node P1 needs to be high level.
The above is only an example of the specific structure of the output control module 20, and in the specific implementation, the specific structure of the output control module 20 is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known by those skilled in the art, which are not described herein again.
In a specific implementation, in order to reset the potential of the first node P1, as shown in fig. 2b, in the shift register provided in the embodiment of the present invention, the reset module 30 may specifically include: a fourth thin film transistor M4; wherein,
the fourth thin film transistor M4 has a gate connected to a RESET signal terminal RESET, a source connected to a reference signal terminal VSS, and a drain connected to the first node P1.
Specifically, the fourth thin film transistor M4 outputs the reference signal of the reference signal terminal VSS to the first node P1 under the control of the RESET signal terminal RESET, and realizes the RESET of the potential of the first node P1.
Specifically, the fourth thin film transistor M4 may be a P-type thin film transistor or an N-type thin film transistor, as shown in fig. 2b, which is not limited herein. When the fourth thin film transistor M4 is a P-type thin film transistor, the RESET signal of the RESET signal terminal RESET needs to be a low level signal; when the fourth thin film transistor M4 is an N-type thin film transistor, the RESET signal of the RESET signal terminal RESET needs to be a high level signal.
The above is only an example of the specific structure of the reset module 30, and in the specific implementation, the specific structure of the reset module 30 is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known by those skilled in the art, which are not described herein again.
In a specific implementation, in order to eliminate noise at the signal output terminal G [ N ], as shown in fig. 2c, the shift register provided in the embodiment of the present invention may further include:
a first pull-down control module 50 connected among the first control signal terminal VDD1, the first node P1, the reference signal terminal VSS, and the signal output terminal G [ N ], for providing the reference signal of the reference signal terminal VSS to a second node P2 (not shown in FIG. 2 c) under the control of the first node P1, and providing the reference signal of the reference signal terminal VSS to the first node P1 and the signal output terminal G [ N ] respectively when the second node P2 is the first control signal inputted from the first control signal terminal VDD 1;
a second pull-down control module 60 connected among the second control signal terminal VDD2, the first node P1, the reference signal terminal VSS, and the signal output terminal gn, for providing the reference signal of the reference signal terminal VSS to a fourth node P4 (not shown in fig. 2 c) under the control of the first node P1, and providing the reference signal of the reference signal terminal VSS to the first node P1 and the signal output terminal gn respectively when the fourth node P4 is the second control signal inputted from the second control signal terminal VDD 2;
the first control signal terminal VDD1 and the second control signal terminal VDD2 alternately input the control signals.
Specifically, in the shift register provided in the embodiment of the present invention, as shown in fig. 2d, the first pull-down control module 50 may specifically include: a fifth thin film transistor M5, a sixth thin film transistor M6, a seventh thin film transistor M7, an eighth thin film transistor M8, a ninth thin film transistor M9, and a tenth thin film transistor M10; wherein,
a gate and a source of the fifth thin film transistor M5 are both connected to the first control signal terminal VDD1, and a drain thereof is connected to the third node P3;
a gate electrode of the sixth thin film transistor M6 is connected to the third node P3, a source electrode thereof is connected to the first control signal terminal VDD1, and a drain electrode thereof is connected to the second node P2;
a gate electrode of the seventh thin film transistor M7 is connected to the first node P1, a source electrode thereof is connected to the reference signal terminal VSS, and a drain electrode thereof is connected to the third node P3;
the eighth thin film transistor M8 has a gate connected to the first node P1, a source connected to the reference signal terminal VSS, and a drain connected to the second node P2;
a gate electrode of the ninth thin film transistor M9 is connected to the second node P2, a source electrode thereof is connected to the reference signal terminal VSS, and a drain electrode thereof is connected to the first node P1;
a tenth thin film transistor M10 having a gate connected to the second node P2, a source connected to the reference signal terminal VSS, and a drain connected to the signal output terminal gn;
the second pull-down control module 60 may specifically include: an eleventh thin film transistor M11, a twelfth thin film transistor M12, a thirteenth thin film transistor M13, a fourteenth thin film transistor M14, a fifteenth thin film transistor M15, and a sixteenth thin film transistor M16; wherein,
a gate and a source of the eleventh thin film transistor M11 are both connected to the second control signal terminal VDD2, and a drain thereof is connected to the fifth node P5;
a twelfth thin film transistor M12 having a gate connected to the fifth node P5, a source connected to the second control signal terminal VDD2, and a drain connected to the fourth node P4;
a gate electrode of the thirteenth thin film transistor M13 is connected to the first node P1, a source electrode thereof is connected to the reference signal terminal VSS, and a drain electrode thereof is connected to the fifth node P5;
a gate electrode of the fourteenth thin film transistor M14 is connected to the first node P1, a source electrode thereof is connected to the reference signal terminal VSS, and a drain electrode thereof is connected to the fourth node P4;
a gate electrode of the fifteenth thin film transistor M15 is connected to the fourth node P4, a source electrode thereof is connected to the reference signal terminal VSS, and a drain electrode thereof is connected to the first node P1;
the sixteenth thin film transistor M16 has a gate connected to the fourth node P4, a source connected to the reference signal terminal VSS, and a drain connected to the signal output terminal G [ N ].
Specifically, the fifth thin film transistor M5 outputs the first control signal to the third node P3 under the control of the first control signal input from the first control signal terminal VDD 1; the sixth thin film transistor M6 outputs the first control signal of the first control signal terminal VDD1 to the second node P2 under the control of the third node P3; the seventh thin film transistor M7 outputs the reference signal of the reference signal terminal VSS to the third node P3 under the control of the first node P1; the eighth thin film transistor M8 outputs the reference signal of the reference signal terminal VSS to the second node P2 under the control of the first node P1; the ninth thin film transistor M9 outputs the reference signal of the reference signal terminal VSS to the first node P1 when the second node P2 is the first control signal inputted from the first control signal terminal VDD 1; the tenth thin film transistor M10 outputs the reference signal of the reference signal terminal VSS to the signal output terminal gn when the second node P2 is the first control signal inputted from the first control signal terminal VDD 1; the eleventh thin film transistor M11 outputs the second control signal to the fifth node P5 under the control of the second control signal input from the second control signal terminal VDD 2; the twelfth thin film transistor M12 outputs the second control signal of the second control signal terminal VDD2 to the fourth node P4 under the control of the fifth node P5; the thirteenth thin film transistor M13 outputs the reference signal of the reference signal terminal VSS to the fifth node P5 under the control of the first node P1; the fourteenth thin film transistor M14 outputs the reference signal of the reference signal terminal VSS to the fourth node P4 under the control of the first node P1; the fifteenth thin film transistor M15 outputs the reference signal of the reference signal terminal VSS to the first node P1 when the fourth node P4 is the second control signal inputted from the second control signal terminal VDD 2; the sixteenth thin film transistor M16 outputs the reference signal of the reference signal terminal VSS to the signal output terminal G [ N ] when the fourth node P4 is the second control signal inputted from the second control signal terminal VDD 2.
Specifically, the fifth thin film transistor M5, the sixth thin film transistor M6, the seventh thin film transistor M7, the eighth thin film transistor M8, the ninth thin film transistor M9, the tenth thin film transistor M10, the eleventh thin film transistor M11, the twelfth thin film transistor M12, the thirteenth thin film transistor M13, the fourteenth thin film transistor M14, the fifteenth thin film transistor M15, and the sixteenth thin film transistor M16 may be P-type thin film transistors or N-type thin film transistors, as shown in fig. 2d, which is not limited herein.
Specifically, in the shift register provided in the embodiment of the present invention, the first control signal terminal VDD1 and the second control signal terminal VDD2 alternately input the control signal to control the first pull-down control module 50 and the second pull-down control module 60 to alternately operate. Of course, the time length of the control signal alternately input to the first control signal terminal VDD1 and the second control signal terminal VDD2 may be an integer multiple of the time length of the Frame scan (Frame), and may be the same as or an integer multiple of the period of the clock signal input to the clock signal terminal CLK, which is not limited herein.
In addition, the first pull-down control module 50 and the second pull-down control module 60 are both used to eliminate noise interference of the first node P1 and the signal output terminal G [ N ], and the two pull-down control modules work alternately, so that one of the pull-down control modules can always be ensured to be in a working state, and the stability of the potentials of the first node P1 and the signal output terminal G [ N ] is maintained; meanwhile, the two pull-down control modules work alternately, so that the service life of the shift register is prolonged, and the stability of the shift register is improved.
The above description is only for illustrating specific structures of the first pull-down control module 50 and the second pull-down control module 60, and in the specific implementation, the specific structures of the first pull-down control module 50 and the second pull-down control module 60 are not limited to the above structures provided in the embodiment of the present invention, and may also be other structures known by those skilled in the art, and are not described herein again.
The operation of the shift register provided by the embodiment of the present invention is described below with reference to the shift register shown in fig. 2d and the input/output timing diagram shown in fig. 3.
As shown in FIG. 3, the input/output timing diagram of the shift register of the present embodiment is selected from the four stages T1-T4; in the following description, a high level is represented by 1, and a low level signal is represented by 0.
In stage T1, INPUT is 1, CLK is 0, VDD1 is 1, VDD2 is 0, and RESET is 0. When INPUT is equal to 1, the second thin film transistor M2 is turned on, and outputs the valid pulse signal INPUT by the signal INPUT terminal INPUT to the first node P1, charges the first node P1, and pulls the potential of the first node P1 high; meanwhile, the first thin film transistor M1 is turned on, the reference signal of the reference signal terminal VSS is output to the signal output terminal G [ N ], so that the signal output terminal G [ N ] outputs low level, and the noise reduction processing of the signal output terminal G [ N ] in the time period is realized; when the potential of the first node P1 is at a high level, the seventh thin film transistor M7, the eighth thin film transistor M8, the thirteenth thin film transistor M13, and the fourteenth thin film transistor M14 are turned on, and the reference signal of the reference signal terminal VSS is output to the second node P2, the third node P3, the fourth node P4, and the fifth node P5, respectively, so that the potentials of all the four nodes are kept at a low level.
In stage T2, INPUT is 0, CLK is 1, VDD1 is 1, VDD2 is 0, and RESET is 0. When CLK is 1, the potential of the first node P1 is at a high level, the third tft M3 is turned on, the clock signal at the clock signal terminal CLK is output to the signal output terminal G [ N ], so that the signal output terminal G [ N ] outputs a high level signal, and all tfts located on the nth row of gate lines in the display region of the liquid crystal panel are turned on through the nth row of gate lines corresponding to the shift register, and the data line starts to write a signal; meanwhile, the potential of the first node P1 is further pulled high due to the bootstrap action of the capacitor C; the stage T2 is therefore the open stage of the shift register.
In stage T3, INPUT is 0, CLK is 0, VDD1 is 1, VDD2 is 0, and RESET is 0. When CLK is equal to 0 and the potential of the first node P1 is at a high level, the third tft M3 remains turned on, and outputs the clock signal from the clock signal terminal CLK to the signal output terminal G [ N ], so that the signal output terminal G [ N ] outputs a low level signal; at the same time, the potential of the first node P1 is pulled down to a normal high level due to the bootstrap action of the capacitor C.
In stage T4, INPUT is 0, CLK is 0, VDD1 is 1, VDD2 is 0, and RESET is 1. When RESET is 1, the fourth thin film transistor M4 is turned on, and outputs the reference signal of the reference signal terminal VSS to the first node P1, pulling the potential of the first node P1 low; meanwhile, since VDD1 is equal to 1, the fifth thin film transistor M5 is turned on, and outputs the first control signal of the first control signal terminal VDD1 to the third node P3; when the potential of the third node P3 is at a high level, the sixth thin film transistor M6 is turned on, and the first control signal of the first control signal terminal VDD1 is output to the second node P2; at this time, when the second node P2 is the first control signal of the first control signal terminal VDD1, the ninth thin film transistor M9 and the tenth thin film transistor M10 are turned on, and the reference signal of the reference signal terminal VSS is respectively output to the first node P1 and the signal output terminal G [ N ], so that the noise reduction processing of the first node P1 and the signal output terminal G [ N ] is realized; in addition, since VDD2 is equal to 0, the eleventh thin film transistor M11 and the twelfth thin film transistor M12 are in an off state, so that the potentials of the fourth node P4 and the fifth node P5 are both low, and the fifteenth thin film transistor M15 and the sixteenth thin film transistor M16 are in an off state.
After that, until the next T1 stage, that is, INPUT is 1, CLK is 0, VDD1 is 1, VDD2 is 0, and RESET is 0, the first thin film transistor M1 outputs the reference signal of the reference signal terminal VSS to the signal output terminal G [ N ], thereby reducing noise at the signal output terminal G [ N ] and improving stability of the gate scan signal output from the signal output terminal G [ N ].
The above illustration is only performed by using the shift register shown in fig. 2d, and the shift register provided in the embodiment of the present invention can be implemented by adding the noise reduction module 40 to any shift register in the prior art, which is not limited herein.
Specifically, in order to prove the stability of the gate scan signal outputted from the signal output terminal G [ N ] of the shift register provided in the embodiment of the present invention, the output signal simulation is performed on the signal output terminals of the shift register provided in the embodiment of the present invention and the shift register in the prior art, and the result is shown in fig. 4a and 4 b; wherein, fig. 4a is a simulation result at room temperature, an inset shows an enlarged view of the simulation result with time between 75 microseconds and 105 microseconds, fig. 4b is a simulation result at room temperature after 10000 hours of normal operation, an inset shows an enlarged view of the simulation result with time between 60 microseconds and 85 microseconds, abscissa time(s) in fig. 4a and 4b both show the time of signal output from the signal output terminal of the shift register, and ordinate voltage (v) both show the magnitude of signal output from the signal output terminal of the shift register; by comparing simulation results, at the holding stage of the pixel voltage, the signal noise output by the signal output end of the shift register provided by the embodiment of the invention is obviously lower than that output by the signal output end of the shift register in the prior art, and after the shift register normally works for 10000 hours, the signal noise output by the signal output end of the shift register provided by the embodiment of the invention is still small, and the signal is relatively stable; therefore, the noise reduction module 40 effectively reduces the noise of the shift register in the holding stage of the pixel voltage, and improves the stability of the gate scan signal output by the signal output terminal G [ N ] of the shift register.
Based on the same inventive concept, the embodiment of the present invention further provides a gate integrated driving circuit, which may include a plurality of cascaded shift registers provided by the embodiments of the present invention; wherein,
and the signal output end of the Nth-stage shift register inputs a reset signal to the reset signal end of the (N + 1) th-stage shift register, or inputs a reset signal to the reset signal end of the (N + 2) th-stage shift register, and inputs an effective pulse signal to the signal input end of the (N-1) th-stage shift register, wherein N is an integer greater than 1.
Specifically, for convenience of explaining the functions and the connection relationships of the noise reduction modules 40 in the shift registers of each stage, in the gate integrated drive circuit provided in the embodiment of the present invention, as shown in fig. 5, the first clock signal terminal CLK1 and the second clock signal terminal CLK2 respectively provide clock signals for the shift registers of each stage, the first control signal terminal VDD1 and the second control signal terminal VDD2 provide control signals for the shift registers of each stage, and the reference signal terminal VSS provides a reference signal for the shift registers of each stage; moreover, only five shift registers are shown in fig. 5, which are respectively an N-2 th stage shift register, an N-1 th stage shift register, an nth stage shift register, an N +1 th stage shift register, and an N +2 th stage shift register; wherein, the signal output end G [ N ] of the Nth level shift register not only INPUTs a RESET signal to the RESET signal end RESET of the (N + 2) th level shift register, but also INPUTs an effective pulse signal to the signal INPUT end INPUT of the (N-1) th level shift register; and simultaneously, the effective pulse signal is utilized to control a noise reduction module 40 in the shift register of the (N-1) th level, the potential of the signal output end G [ N-1] of the shift register of the (N-1) th level is maintained to be low level in the holding stage of the pixel voltage, and the interference of noise on the signal output end G [ N-1] of the shift register of the (N-1) th level is eliminated.
In addition, fig. 6 shows a schematic diagram of a connection relationship between the signal output end of each shift register stage and the equivalent capacitor of the noise reduction module, wherein noise at the signal output end of each shift register stage can be coupled and released to the reference signal terminal VSS through the equivalent capacitor of the noise reduction module in the shift register stage, so that the potential at the signal output end of the shift register stage can be stably maintained at a low level; in addition, when the noise reduction module in the nth stage shift register loses the noise reduction function, noise can be coupled to the nth-1 stage shift register or the (N + 1) th stage shift register connected with the nth stage shift register through capacitance, the noise is coupled and released to the reference signal terminal VSS through the noise reduction module in the nth-1 stage shift register or the (N + 1) th stage shift register, the noise is eliminated, and therefore mutual cancellation (shielding) of the noise of the signal output ends of the shift registers of all stages is achieved, and stability of grid scanning signals output by the whole grid integrated drive circuit is improved.
Specifically, the specific structure of each shift register in the gate integrated driver circuit provided in the embodiment of the present invention is the same as the shift register provided in the embodiment of the present invention in function and structure, and repeated descriptions are omitted.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, which may include the gate integrated driving circuit provided in the embodiment of the present invention, and specific implementation thereof may refer to the description of the gate integrated driving circuit provided in the embodiment of the present invention, and details of the same are not repeated.
In specific implementation, an embodiment of the present invention further provides a method for driving a shift register, where, in combination with the shift register shown in fig. 2c and the input/output timing diagram shown in fig. 3, the method includes:
in the first time period, the INPUT module 10 provides the valid pulse signal of the signal INPUT terminal INPUT to the first node P1 under the control of the valid pulse signal INPUT by the signal INPUT terminal INPUT; the noise reduction module 40 provides a reference signal of a reference signal terminal VSS to a signal output terminal GN under the control of an effective pulse signal inputted from a signal INPUT terminal INPUT;
in a second time period, the output control module 20 provides the clock signal of the clock signal terminal CLK to the signal output terminal G [ N ] under the control of the first node P1;
during the fourth period, the RESET module 30 supplies the reference signal of the reference signal terminal VSS to the first node P1 under the control of the RESET signal terminal RESET.
Specifically, in the driving method of the shift register provided in the embodiment of the present invention, in combination with the shift register shown in fig. 2c and fig. 2d and the input/output timing chart shown in fig. 3, the method may further include:
in the first, second, and third periods, the first pull-down control module 50 provides the reference signal of the reference signal terminal VSS to the second node P2 when the first node P1 is the active pulse signal INPUT from the signal INPUT terminal INPUT;
during the fourth period, the first pull-down control module 50 provides the reference signal of the reference signal terminal VSS to the first node P1 and the signal output terminal G [ N ], respectively, when the second node P2 is the first control signal inputted from the first control signal terminal VDD 1.
The embodiment of the invention provides a shift register, a driving method thereof, a grid integrated driving circuit and a display device, wherein the shift register comprises an input module, a first node and a second node, wherein the input module is used for providing an effective pulse signal to the first node under the control of the effective pulse signal input by a signal input end; the output control module is used for providing a clock signal of the clock signal end to the signal output end under the control of the first node; the reset module is used for providing a reference signal of a reference signal end to a first node under the control of a reset signal end; the noise reduction module is connected among the signal input end, the reference signal end and the signal output end and used for providing a reference signal of the reference signal end to the signal output end under the control of an effective pulse signal input by the signal input end; therefore, by additionally arranging a noise reduction module in the existing shift register, under the control of an effective pulse signal input by a signal input end, the noise interference on a signal output end is reduced by using a reference signal of a reference signal end; meanwhile, in the gate integrated drive circuit composed of a plurality of cascaded shift registers provided by the embodiments of the present invention, by using the connection relationship between the noise reduction module in each shift register and the signal output terminal of each shift register, when the signal output terminal of one shift register is abnormal, noise can be coupled to the noise reduction module in the shift register adjacent to the shift register, and the noise coupling is released to the reference signal terminal through the noise reduction module, so as to eliminate noise, so that the noise at the signal output terminals of each shift register is cancelled, and the stability of the gate scanning signal output by the gate integrated drive circuit is improved while the capability of removing noise of the shift register is improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A shift register, comprising: the input module is connected between a signal input end and a first node and is used for providing an effective pulse signal to the first node under the control of the effective pulse signal input by the signal input end; the output control module is connected among the first node, the clock signal end and the signal output end and is used for providing the clock signal of the clock signal end to the signal output end under the control of the first node; the reset module is connected among a reset signal end, a reference signal end and the first node and is used for providing a reference signal of the reference signal end to the first node under the control of the reset signal end; it is characterized by also comprising:
and the noise reduction module is connected among the signal input end, the reference signal end and the signal output end and is used for providing a reference signal of the reference signal end to the signal output end under the control of an effective pulse signal input by the signal input end.
2. The shift register of claim 1, wherein the noise reduction module comprises: a first thin film transistor; wherein,
and the grid electrode of the first thin film transistor is connected with the signal input end, the source electrode of the first thin film transistor is connected with the reference signal end, and the drain electrode of the first thin film transistor is connected with the signal output end.
3. The shift register of claim 1, wherein the input module comprises: a second thin film transistor; wherein,
and the grid electrode and the source electrode of the second thin film transistor are both connected with the signal input end, and the drain electrode of the second thin film transistor is connected with the first node.
4. The shift register of claim 1, wherein the output control module comprises: a third thin film transistor and a capacitor; wherein,
the grid electrode of the third thin film transistor is connected with the first node, the source electrode of the third thin film transistor is connected with the clock signal end, and the drain electrode of the third thin film transistor is connected with the signal output end;
the capacitor is connected between the first node and the signal output end.
5. The shift register of claim 1, wherein the reset module comprises: a fourth thin film transistor; wherein,
and the grid electrode of the fourth thin film transistor is connected with the reset signal end, the source electrode of the fourth thin film transistor is connected with the reference signal end, and the drain electrode of the fourth thin film transistor is connected with the first node.
6. The shift register of any one of claims 1-5, further comprising:
a first pull-down control module connected among a first control signal terminal, the first node, the reference signal terminal, and the signal output terminal, and configured to provide a reference signal of the reference signal terminal to a second node under the control of the first node, and provide reference signals of the reference signal terminal to the first node and the signal output terminal, respectively, when the second node is a first control signal input by the first control signal terminal;
a second pull-down control module connected among a second control signal terminal, the first node, the reference signal terminal, and the signal output terminal, and configured to provide a reference signal of the reference signal terminal to a fourth node under the control of the first node, and provide reference signals of the reference signal terminal to the first node and the signal output terminal, respectively, when the fourth node is a second control signal input by the second control signal terminal;
the first control signal end and the second control signal end alternately input control signals.
7. The shift register of claim 6, wherein the first pull-down control module comprises: a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, and a tenth thin film transistor; wherein,
the grid electrode and the source electrode of the fifth thin film transistor are both connected with the first control signal end, and the drain electrode of the fifth thin film transistor is connected with the third node;
a grid electrode of the sixth thin film transistor is connected with the third node, a source electrode of the sixth thin film transistor is connected with the first control signal end, and a drain electrode of the sixth thin film transistor is connected with the second node;
a grid electrode of the seventh thin film transistor is connected with the first node, a source electrode of the seventh thin film transistor is connected with the reference signal end, and a drain electrode of the seventh thin film transistor is connected with the third node;
a grid electrode of the eighth thin film transistor is connected with the first node, a source electrode of the eighth thin film transistor is connected with the reference signal end, and a drain electrode of the eighth thin film transistor is connected with the second node;
a grid electrode of the ninth thin film transistor is connected with the second node, a source electrode of the ninth thin film transistor is connected with the reference signal end, and a drain electrode of the ninth thin film transistor is connected with the first node;
a grid electrode of the tenth thin film transistor is connected with the second node, a source electrode of the tenth thin film transistor is connected with the reference signal end, and a drain electrode of the tenth thin film transistor is connected with the signal output end;
the second pull-down control module comprising: an eleventh thin film transistor, a twelfth thin film transistor, a thirteenth thin film transistor, a fourteenth thin film transistor, a fifteenth thin film transistor, and a sixteenth thin film transistor; wherein,
a grid electrode and a source electrode of the eleventh thin film transistor are both connected with the second control signal end, and a drain electrode of the eleventh thin film transistor is connected with a fifth node;
a grid electrode of the twelfth thin film transistor is connected with the fifth node, a source electrode of the twelfth thin film transistor is connected with the second control signal end, and a drain electrode of the twelfth thin film transistor is connected with the fourth node;
a gate of the thirteenth thin film transistor is connected to the first node, a source of the thirteenth thin film transistor is connected to the reference signal terminal, and a drain of the thirteenth thin film transistor is connected to the fifth node;
a grid electrode of the fourteenth thin film transistor is connected with the first node, a source electrode of the fourteenth thin film transistor is connected with the reference signal end, and a drain electrode of the fourteenth thin film transistor is connected with the fourth node;
a grid electrode of the fifteenth thin film transistor is connected with the fourth node, a source electrode of the fifteenth thin film transistor is connected with the reference signal end, and a drain electrode of the fifteenth thin film transistor is connected with the first node;
and the grid electrode of the sixteenth thin film transistor is connected with the fourth node, the source electrode of the sixteenth thin film transistor is connected with the reference signal end, and the drain electrode of the sixteenth thin film transistor is connected with the signal output end.
8. A gate integrated driver circuit comprising a plurality of shift registers according to any one of claims 1 to 7 in cascade; wherein,
and the signal output end of the Nth-stage shift register inputs a reset signal to the reset signal end of the (N + 1) th-stage shift register, or inputs a reset signal to the reset signal end of the (N + 2) th-stage shift register, and inputs an effective pulse signal to the signal input end of the (N-1) th-stage shift register, wherein N is an integer greater than 1.
9. A display device comprising the gate integrated driver circuit according to claim 8.
10. A driving method of a shift register according to any one of claims 1 to 7, comprising:
in a first time period, the input module provides an effective pulse signal of a signal input end to a first node under the control of the effective pulse signal input by the signal input end; the noise reduction module is used for providing a reference signal of a reference signal end to a signal output end under the control of the effective pulse signal input by the signal input end;
in a second time period, the output control module provides a clock signal of a clock signal end to the signal output end under the control of the first node;
in a fourth time period, the reset module provides the reference signal of the reference signal terminal to the first node under the control of the reset signal terminal.
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Application publication date: 20170510 |