CN106652875A - Shifting register, driving method thereof, grid integrated drive circuit and display device - Google Patents
Shifting register, driving method thereof, grid integrated drive circuit and display device Download PDFInfo
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- CN106652875A CN106652875A CN201710005646.2A CN201710005646A CN106652875A CN 106652875 A CN106652875 A CN 106652875A CN 201710005646 A CN201710005646 A CN 201710005646A CN 106652875 A CN106652875 A CN 106652875A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Liquid Crystal Display Device Control (AREA)
- Shift Register Type Memory (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a shifting register, a driving method of the shifting register, a grid integrated drive circuit and a display device. A noise reducing module is additionally arranged in the existing shifting register, under the control of effective pulse signals input by a signal input end, the noises of a signal output end are eliminated by utilizing a reference signal end; meanwhile, in the grid integrated drive circuit composed of a plurality of cascaded shifting registers provided by the embodiment of the invention, by utilizing the connecting relation between the noise reducing modules of the shifting registers of different levels and signal output ends, when the output of the signal output end of one shifting register is abnormal, the noises can be coupled to the noise reducing module of the shifting register adjacent to the abnormal shifting register, the noises are then coupled and released to the reference signal end through the noise reducing module and are finally eliminated, therefore, the noises of the signal output ends of the shifting registers of different levels are cancelled out, and meanwhile, while the denoising capacity of the shifting registers is improved, the stability of grid scanning signals output by the grid integrated drive circuit is improved.
Description
Technical field
The present invention relates to display technology field, espespecially a kind of shift register, its driving method, grid integrated drive electronics
And display device.
Background technology
GOA (Gate on Array) is a kind of skill being integrated in grid integrated drive electronics on thin film transistor base plate
Art, gated sweep signal is provided by grid integrated drive electronics to the grid of each thin film transistor (TFT) of pixel region, is opened line by line
Each thin film transistor (TFT) is opened, the data-signal input of pixel cell is realized.
In the prior art, shift register as grid integrated drive electronics part, basic structure such as Fig. 1 a
It is shown, including 15 thin film transistor (TFT)s, respectively first film transistor M1, the second thin film transistor (TFT) M2, the 3rd film crystal
Pipe M3, the 4th thin film transistor (TFT) M4, the 5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7, the 8th
It is thin film transistor (TFT) M8, the 9th thin film transistor (TFT) M9, the tenth thin film transistor (TFT) M10, the 11st thin film transistor (TFT) M11, the 12nd thin
Film transistor M12, the 13rd thin film transistor (TFT) M13, the 14th thin film transistor (TFT) M14, the 15th thin film transistor (TFT) M15, one
Storage capacitance C, a clock signal terminal CLK, two control signal ends VDD1 and VDD2, a signal input part INPUT, one
Reset signal end RESET, a reference signal end VSS and a signal output part G [N].
Additionally, the structure of the grid integrated drive electronics being made up of the above-mentioned shift register for cascading is as shown in Figure 1 b, N
The signal output part of level shift register is believed while gated sweep signal is exported to the reset of N+2 level shift registers
Number end provide reset signal, while to N-1 level shift registers signal input part provide effective impulse signal.
Typically for the one-row pixels of display floater, the most of the time of a frame in is the hold mode of pixel voltage, i.e.,
The current potential of signal output part G [N] outputs of shift register keeps low level；Simultaneously for grid integrated drive electronics, if
The abnormal signal of the signal output part output of one of shift register, then can cause connected the superior and the subordinate's shift LD
The signal output part of device occurs output abnormality；Therefore, the ability of raising shift register removal noise seems and is even more important.
Based on this, the ability that shift register removes noise how is improved, be those skilled in the art's skill urgently to be resolved hurrily
Art problem.
The content of the invention
A kind of shift register provided in an embodiment of the present invention, its driving method, grid integrated drive electronics and display dress
Put, to solve how to improve the ability that shift register removes noise, improve the gated sweep signal of shift register output
Stability.
A kind of shift register is embodiments provided, including：It is connected between signal input part and first node
Input module, under the control of the effective impulse signal that the signal input part is input into, effective impulse signal being provided
To the first node；It is connected to the first node, the output control mould between clock signal terminal and signal output part
Block, under the control of the first node, the clock signal of the clock signal terminal being provided to the signal output part；
The reseting module being connected between reset signal end, reference signal end and the first node, in the reset signal
Under the control of the reset signal at end, the reference signal at the reference signal end is provided to the first node；Also include：
The noise reduction module being connected between the signal input part, the reference signal end and the signal output part,
For under the control of the effective impulse signal that the signal input part is input into, the reference signal at the reference signal end being provided
To the signal output part.
In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, the noise reduction
Module, including：First film transistor；Wherein,
The grid of the first film transistor is connected with the signal input part, source electrode and reference signal end phase
Even, drain electrode is connected with the signal output part.
In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, the input
Module, including：Second thin film transistor (TFT)；Wherein,
The grid and source electrode of second thin film transistor (TFT) is connected with the signal input part, drains and the first segment
Point is connected.
In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, the output
Control module, including：3rd thin film transistor (TFT) and electric capacity；Wherein,
The grid of the 3rd thin film transistor (TFT) is connected with the first node, and source electrode is connected with the clock signal terminal,
Drain electrode is connected with the signal output part；
Capacitance connection is between the first node and the signal output part.
In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, the reset
Module, including：4th thin film transistor (TFT)；Wherein,
The grid of the 4th thin film transistor (TFT) is connected with the reset signal end, source electrode and reference signal end phase
Even, drain electrode is connected with the first node.
In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, also include：
Be connected to the first control signal end, the first node, the reference signal end and the signal output part it
Between the first drop-down control module, under the control of the first node, the reference signal at the reference signal end being carried
Section Point is supplied to, in the first control signal that the Section Point is the first control signal end input, by the ginseng
The reference signal for examining signal end is provided respectively to the first node and the signal output part；
Be connected to the second control signal end, the first node, the reference signal end and the signal output part it
Between the second drop-down control module, under the control of the first node, the reference signal at the reference signal end being carried
Fourth node is supplied to, in the second control signal that the fourth node is the second control signal end input, by the ginseng
The reference signal for examining signal end is provided respectively to the first node and the signal output part；
First control signal end replaces input control signal with second control signal end.
In a kind of possible embodiment, in above-mentioned shift register provided in an embodiment of the present invention, described first
Drop-down control module, including：5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th film crystal
Pipe, the 9th thin film transistor (TFT) and the tenth thin film transistor (TFT)；Wherein,
The grid and source electrode of the 5th thin film transistor (TFT) is connected with first control signal end, drains and Section three
Point is connected；
The grid of the 6th thin film transistor (TFT) is connected with the 3rd node, source electrode and the first control signal end phase
Even, drain electrode is connected with the Section Point；
The grid of the 7th thin film transistor (TFT) is connected with the first node, and source electrode is connected with the reference signal end,
Drain electrode is connected with the 3rd node；
The grid of the 8th thin film transistor (TFT) is connected with the first node, and source electrode is connected with the reference signal end,
Drain electrode is connected with the Section Point；
The grid of the 9th thin film transistor (TFT) is connected with the Section Point, and source electrode is connected with the reference signal end,
Drain electrode is connected with the first node；
The grid of the tenth thin film transistor (TFT) is connected with the Section Point, and source electrode is connected with the reference signal end,
Drain electrode is connected with the signal output part；
The second drop-down control module, including：It is 11st thin film transistor (TFT), the 12nd thin film transistor (TFT), the 13rd thin
Film transistor, the 14th thin film transistor (TFT), the 15th thin film transistor (TFT) and the 16th thin film transistor (TFT)；Wherein,
The grid of the 11st thin film transistor (TFT) is connected with source electrode with second control signal end, drain electrode and the 5th
Node is connected；
The grid of the 12nd thin film transistor (TFT) is connected with the 5th node, source electrode and second control signal end
It is connected, drain electrode is connected with the fourth node；
The grid of the 13rd thin film transistor (TFT) is connected with the first node, source electrode and reference signal end phase
Even, drain electrode is connected with the 5th node；
The grid of the 14th thin film transistor (TFT) is connected with the first node, source electrode and reference signal end phase
Even, drain electrode is connected with the fourth node；
The grid of the 15th thin film transistor (TFT) is connected with the fourth node, source electrode and reference signal end phase
Even, drain electrode is connected with the first node；
The grid of the 16th thin film transistor (TFT) is connected with the fourth node, source electrode and reference signal end phase
Even, drain electrode is connected with the signal output part.
The embodiment of the present invention additionally provides a kind of grid integrated drive electronics, including multiple embodiment of the present invention of cascade are carried
For above-mentioned shift register；Wherein,
The signal output part of N level shift registers resets to the reset signal end input of N+1 level shift registers and believes
Number, or reset signal is input into the reset signal end of N+2 level shift registers, and to the signal of N-1 level shift registers
Input is input into effective impulse signal, and N is the integer more than 1.
The embodiment of the present invention additionally provides a kind of display device, including the integrated drive of above-mentioned grid provided in an embodiment of the present invention
Dynamic circuit.
The embodiment of the present invention additionally provides a kind of driving method of above-mentioned shift register provided in an embodiment of the present invention, bag
Include：
In first time period, input module under the control of the effective impulse signal that signal input part is input into, by the letter
The effective impulse signal of number input is provided to first node；Noise reduction module is believed in the effective impulse that the signal input part is input into
Number control under, the reference signal at reference signal end is provided to signal output part；
In second time period, output control module believes on the clock of clock signal terminal under the control of the first node
Number provide to the signal output part；
In the 4th time period, reseting module under the control of the reset signal at reset signal end, by the reference signal end
Reference signal provide to the first node.
The present invention has the beneficial effect that：
A kind of shift register provided in an embodiment of the present invention, its driving method, grid integrated drive electronics and display dress
Put, the shift register includes input module, under the control for the effective impulse signal being input in signal input part, will be effective
Pulse signal is provided to first node；Output control module, under the control of first node, by the clock of clock signal terminal
Signal is provided to signal output part；Reseting module, under the control of the reset signal at reset signal end, by reference signal end
Reference signal provide to first node；Also include being connected between signal input part, reference signal end and signal output part
Noise reduction module, under the control for the effective impulse signal being input in signal input part, by the reference signal at reference signal end
There is provided to signal output part；Therefore, by setting up noise reduction module in existing shift register, in signal input part input
Under the control of effective impulse signal, using the reference signal at reference signal end, the noise jamming to signal output part is reduced；Together
When, in the grid integrated drive electronics being made up of the above-mentioned shift register multiple provided in an embodiment of the present invention for cascading, profit
With the annexation between the signal output part of the noise reduction module in shift registers at different levels and shift register at different levels, when one
During the signal output part output abnormality of shift register, noise coupling extremely can be posted with this grade of adjacent displacement of shift register
Noise reduction module in storage, reference signal end is discharged into by the noise reduction module by noise coupling, eliminates noise, makes displacements at different levels
The noise of the signal output part of register is cancelled out each other, and while the ability of shift register removal noise is improved, improves grid
The stability of the gated sweep signal of pole integrated drive electronics output.
Description of the drawings
Fig. 1 a are the structural representation of shift register in prior art；
Fig. 1 b are the structural representation of grid integrated drive electronics in prior art；
Fig. 2 a to 2d are a kind of structural representation of shift register provided in an embodiment of the present invention；
Fig. 3 is a kind of input and output sequential chart of shift register provided in an embodiment of the present invention；
Fig. 4 a and 4b are the letter of a kind of shift register provided in an embodiment of the present invention and shift register in prior art
The schematic diagram of the analog result of number output end output signal；
Fig. 5 is a kind of structural representation of grid integrated drive electronics provided in an embodiment of the present invention；
Fig. 6 is the signal output part and noise reduction module equivalent capacity of shift register at different levels provided in an embodiment of the present invention
Annexation schematic diagram.
Specific embodiment
Below in conjunction with the accompanying drawings, to a kind of shift register provided in an embodiment of the present invention, its driving method, the integrated drive of grid
The specific embodiment of dynamic circuit and display device is described in detail.
A kind of shift register is embodiments provided, as shown in Figure 2 a, can be included：It is connected to signal input part
Input module 10 between INPUT and first node P1, the control of the effective impulse signal for being input in signal input part INPUT
Under system, effective impulse signal is provided to first node P1；It is connected to first node P1, clock signal terminal CLK and signal defeated
Go out to hold the output control module 20 between G [N], under the control of first node P1, the clock of clock signal terminal CLK being believed
Number provide to signal output part G [N]；Be connected to reset signal end RESET, between reference signal end VSS and first node P1
Reseting module 30, under the control of the reset signal of reset signal end RESET, the reference of reference signal end VSS is believed
Number provide to first node P1；Can also include：
The noise reduction module being connected between signal input part INPUT, reference signal end VSS and signal output part G [N]
40, under the control of the effective impulse signal that signal input part INPUT is input into, by the reference signal of reference signal end VSS
There is provided to signal output part G [N].
Above-mentioned shift register provided in an embodiment of the present invention, by the signal input part in existing shift register
Noise reduction module 40 is set up between INPUT, reference signal end VSS and signal output part G [N], it is defeated in signal input part INPUT
Under the control of the effective impulse signal for entering, using the reference signal of reference signal end VSS, reduction is made an uproar to signal output part G [N]
Acoustic jamming, improve shift register remove noise ability, and then improve shift register output gated sweep signal it is steady
It is qualitative.
Specifically, effective impulse signal and clock signal are high level signal, and the current potential of first node P1 is high level, is joined
Signal is examined for low level signal；Or, effective impulse signal and clock signal are low level signal, the current potential of first node P1 is low
Level, reference signal is high level signal.
In the specific implementation, in order to eliminate the noise jamming of signal output part G [N], provide in the embodiment of the present invention
Above-mentioned shift register in, as shown in Figure 2 b, noise reduction module 40 can be specifically included：First film transistor M1；Wherein,
The grid of first film transistor M1 is connected with signal input part INPUT, and source electrode is connected with reference signal end VSS,
Drain electrode is connected with signal output part G [N].
Specifically, first film transistor M1, will under the control of the effective impulse signal that signal input part INPUT is input into
The reference signal of reference signal end VSS is exported to signal output part G [N].
Further, in order to significantly improve the noise reduction capability of noise reduction module 40, provided in an embodiment of the present invention above-mentioned
In shift register, need to determine that the resistance of first film transistor M1 in noise reduction module 40 is big according to the load in pixel region
It is little, i.e., according to the parasitic capacitance in pixel region between grid line and holding wire, and the resistance of grid line, adjust the first film crystal
The resistance sizes of pipe M1 so that noise reduction module 40 removes the ability of noise and reaches maximum, it is ensured that the grid of shift register output
The stability of scanning signal.
Specifically, first film transistor M1 can be P-type TFT, or N-type TFT, such as scheme
Shown in 2b, here is not limited.When first film transistor M1 is P-type TFT, signal input part INPUT inputs
Effective impulse signal is needed for low level signal；When first film transistor M1 is N-type TFT, signal input part
The effective impulse signal of INPUT inputs is needed for high level signal.
The above is only the concrete structure for illustrating noise reduction module 40, in the specific implementation, the concrete knot of noise reduction module 40
Structure is not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other structures, here
Do not repeat.
In the specific implementation, first node P1 is supplied in order to realize the effective impulse signal for inputting a signal into end INPUT,
In above-mentioned shift register provided in an embodiment of the present invention, as shown in Figure 2 b, input module 10 can be specifically included：Second
Thin film transistor (TFT) M2；Wherein,
The grid and source electrode of the second thin film transistor (TFT) M2 is connected with signal input part INPUT, drains and first node P1
It is connected.
Specifically, the second thin film transistor (TFT) M2, will under the control of the effective impulse signal that signal input part INPUT is input into
Effective impulse signal is exported to first node P1.
Specifically, the second thin film transistor (TFT) M2 can be P-type TFT, or N-type TFT, such as scheme
Shown in 2b, here is not limited.When the second thin film transistor (TFT) M2 is P-type TFT, signal input part INPUT inputs
Effective impulse signal is needed for low level signal；When the second thin film transistor (TFT) M2 is N-type TFT, signal input part
The effective impulse signal of INPUT inputs is needed for high level signal.
The above is only the concrete structure for illustrating input module 10, in the specific implementation, the concrete knot of input module 10
Structure is not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other structures, here
Do not repeat.
In the specific implementation, gated sweep signal is exported in order to realize signal output part G [N], is carried in the embodiment of the present invention
For above-mentioned shift register in, as shown in Figure 2 b, output control module 20 can be specifically included：3rd thin film transistor (TFT) M3,
And electric capacity C；Wherein,
The grid of the 3rd thin film transistor (TFT) M3 is connected with first node P1, and source electrode is connected with clock signal terminal CLK, drain electrode with
Signal output part G [N] is connected；
Electric capacity C is connected between first node P1 and signal output part G [N].
Specifically, the 3rd thin film transistor (TFT) M3 is under the control of first node P1, by the clock signal of clock signal terminal CLK
Export to signal output part G [N], make signal output part G [N] export gated sweep signal, by corresponding with the shift register
Nth row grid line, make in the viewing area of liquid crystal panel be located at Nth row grid line on all thin film transistor (TFT)s open, data wire
Start write signal.
Specifically, the 3rd thin film transistor (TFT) M3 can be P-type TFT, or N-type TFT, such as scheme
Shown in 2b, here is not limited.When the 3rd thin film transistor (TFT) M3 is P-type TFT, the current potential of first node P1 needs
For low level；When the 3rd thin film transistor (TFT) M3 is N-type TFT, the current potential of first node P1 is needed for high level.
The above is only the concrete structure for illustrating output control module 20, in the specific implementation, output control module 20
Concrete structure be not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other knot
Structure, therefore not to repeat here.
In the specific implementation, in order to realize resetting the current potential of first node P1, provided in an embodiment of the present invention
In above-mentioned shift register, as shown in Figure 2 b, reseting module 30 can be specifically included：4th thin film transistor (TFT) M4；Wherein,
The grid of the 4th thin film transistor (TFT) M4 is connected with reset signal end RESET, and source electrode is connected with reference signal end VSS,
Drain electrode is connected with first node P1.
Specifically, the 4th thin film transistor (TFT) M4 is under the control of the reset signal of reset signal end RESET, by reference signal
The reference signal of end VSS exports the reset that the current potential to first node P1 is realized to first node P1.
Specifically, the 4th thin film transistor (TFT) M4 can be P-type TFT, or N-type TFT, such as scheme
Shown in 2b, here is not limited.When the 4th thin film transistor (TFT) M4 is P-type TFT, the reset of reset signal end RESET
Signal demand is low level signal；When the 4th thin film transistor (TFT) M4 is N-type TFT, reset signal end RESET's answers
Position signal demand is high level signal.
The above is only the concrete structure for illustrating reseting module 30, in the specific implementation, the concrete knot of reseting module 30
Structure is not limited to said structure provided in an embodiment of the present invention, can also be skilled person will appreciate that other structures, here
Do not repeat.
In the specific implementation, in order to eliminate the noise of signal output part G [N], in above-mentioned shifting provided in an embodiment of the present invention
In bit register, as shown in Figure 2 c, can also include：
It is connected to the first control signal end VDD1, first node P1, reference signal end VSS and signal output part G [N]
Between the first drop-down control module 50, under the control of first node P1, the reference signal of reference signal end VSS being carried
Section Point P2 (not shown in Fig. 2 c) is supplied to, in the first control letter that Section Point P2 is the input of the first control signal end VDD1
Number when, the reference signal of reference signal end VSS is provided respectively to first node P1 and signal output part G [N]；
It is connected to the second control signal end VDD2, first node P1, reference signal end VSS and signal output part G [N]
Between the second drop-down control module 60, under the control of first node P1, the reference signal of reference signal end VSS being carried
Fourth node P4 (not shown in Fig. 2 c) is supplied to, in the second control letter that fourth node P4 is the input of the second control signal end VDD2
Number when, the reference signal of reference signal end VSS is provided respectively to first node P1 and signal output part G [N]；
First control signal end VDD1 replaces input control signal with the second control signal end VDD2.
Specifically, in above-mentioned shift register provided in an embodiment of the present invention, as shown in Figure 2 d, the first drop-down control mould
Block 50, can specifically include：5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7, the 8th film
Transistor M8, the 9th thin film transistor (TFT) M9 and the tenth thin film transistor (TFT) M10；Wherein,
The grid and source electrode of the 5th thin film transistor (TFT) M5 is connected with the first control signal end VDD1, drains and the 3rd node
P3 is connected；
The grid of the 6th thin film transistor (TFT) M6 is connected with the 3rd node P3, and source electrode is connected with the first control signal end VDD1,
Drain electrode is connected with Section Point P2；
The grid of the 7th thin film transistor (TFT) M7 is connected with first node P1, and source electrode is connected with reference signal end VSS, drain electrode with
3rd node P3 is connected；
The grid of the 8th thin film transistor (TFT) M8 is connected with first node P1, and source electrode is connected with reference signal end VSS, drain electrode with
Section Point P2 is connected；
The grid of the 9th thin film transistor (TFT) M9 is connected with Section Point P2, and source electrode is connected with reference signal end VSS, drain electrode with
First node P1 is connected；
The grid of the tenth thin film transistor (TFT) M10 is connected with Section Point P2, and source electrode is connected with reference signal end VSS, drain electrode
It is connected with signal output part G [N]；
Second drop-down control module 60, can specifically include：11st thin film transistor (TFT) M11, the 12nd thin film transistor (TFT)
M12, the 13rd thin film transistor (TFT) M13, the 14th thin film transistor (TFT) M14, the 15th thin film transistor (TFT) M15 and the 16th are thin
Film transistor M16；Wherein,
The grid of the 11st thin film transistor (TFT) M11 is connected with source electrode with the second control signal end VDD2, drain electrode and the 5th
Node P5 is connected；
The grid of the 12nd thin film transistor (TFT) M12 is connected with the 5th node P5, source electrode and the second control signal end VDD2 phase
Even, drain electrode is connected with fourth node P4；
The grid of the 13rd thin film transistor (TFT) M13 is connected with first node P1, and source electrode is connected with reference signal end VSS, leakage
Pole is connected with the 5th node P5；
The grid of the 14th thin film transistor (TFT) M14 is connected with first node P1, and source electrode is connected with reference signal end VSS, leakage
Pole is connected with fourth node P4；
The grid of the 15th thin film transistor (TFT) M15 is connected with fourth node P4, and source electrode is connected with reference signal end VSS, leakage
Pole is connected with first node P1；
The grid of the 16th thin film transistor (TFT) M16 is connected with fourth node P4, and source electrode is connected with reference signal end VSS, leakage
Pole is connected with signal output part G [N].
Specifically, the control of the first control signal that the 5th thin film transistor (TFT) M5 is input in the first control signal end VDD1
Under, the first control signal is exported to the 3rd node P3；6th thin film transistor (TFT) M6 under the control of the 3rd node P3, by first
First control signal of control signal end VDD1 is exported to Section Point P2；Controls of the 7th thin film transistor (TFT) M7 in first node P1
Under system, the reference signal of reference signal end VSS is exported to the 3rd node P3；8th thin film transistor (TFT) M8 is first node P1's
Under control, the reference signal of reference signal end VSS is exported to Section Point P2；9th thin film transistor (TFT) M9 is in Section Point P2
For the first control signal end VDD1 input the first control signal when, the reference signal of reference signal end VSS is exported to first
Node P1；Tenth thin film transistor (TFT) M10 Section Point P2 be the first control signal end VDD1 input the first control signal when,
The reference signal of reference signal end VSS is exported to signal output part G [N]；11st thin film transistor (TFT) M11 is in the second control letter
Number end VDD2 input the second control signal control under, the second control signal is exported to the 5th node P5；12nd film
Transistor M12 exports the second control signal of the second control signal end VDD2 to Section four under the control of the 5th node P5
Point P4；13rd thin film transistor (TFT) M13 under the control of first node P1, by the reference signal of reference signal end VSS export to
5th node P5；14th thin film transistor (TFT) M14 under the control of first node P1, by the reference signal of reference signal end VSS
Export to fourth node P4；15th thin film transistor (TFT) M15 is in that fourth node P4 is the input of the second control signal end VDD2
During two control signals, the reference signal of reference signal end VSS is exported to first node P1；16th thin film transistor (TFT) M16 exists
When fourth node P4 is the second control signal of the second control signal end VDD2 input, by the reference signal of reference signal end VSS
Export to signal output part G [N].
Specifically, the 5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7, the 8th film are brilliant
Body pipe M8, the 9th thin film transistor (TFT) M9, the tenth thin film transistor (TFT) M10, the 11st thin film transistor (TFT) M11, the 12nd film crystal
Pipe M12, the 13rd thin film transistor (TFT) M13, the 14th thin film transistor (TFT) M14, the 15th thin film transistor (TFT) M15 and the 16th
Thin film transistor (TFT) M16 can be P-type TFT, also can be N-type TFT, and as shown in Figure 2 d, here is not
Limit.
Specifically, in above-mentioned shift register provided in an embodiment of the present invention, the first control signal end VDD1 and second
Control signal end VDD2 is alternately input into control signal, and the first drop-down control module 50 of control and the second drop-down control module 60 replace
Work.Certainly, the duration of the first control signal end VDD1 and the second control signal end VDD2 alternately control signal of input can be with
The integral multiple of the duration of frame scan (Frame), can with the cycle phase of clock signal that is input into clock signal terminal CLK with or
Person is its integral multiple, and here is not limited.
Additionally, the first drop-down control module 50 and the second drop-down control module 60 are used to eliminate first node P1 and signal
The noise jamming of output end G [N], two drop-down control module alternations always ensure that one of them drop-down control mould
Block is in running order, and the current potential for maintaining first node P1 and signal output part G [N] is stablized；Meanwhile, two drop-down control moulds
Block alternation, is conducive to improving the working life of shift register, and then improves the stability of shift register.
The above is only the concrete structure for illustrating the first drop-down control module 50 and the second drop-down control module 60, in tool
When body is implemented, the concrete structure of the first drop-down control module 50 and the second drop-down control module 60 is not limited to the embodiment of the present invention and carries
For said structure, can also be skilled person will appreciate that other structures, therefore not to repeat here.
With reference to the input and output sequential chart shown in the shift register and Fig. 3 shown in Fig. 2 d, to the embodiment of the present invention
The course of work of the above-mentioned shift register for providing is described.
As shown in figure 3, for the input and output sequential chart of shift register in the present embodiment, choosing T1-T4 four-stages；
In explained below, high level is represented with 1,0 represents low level signal.
In T1 stages, INPUT=1, CLK=0, VDD1=1, VDD2=0, RESET=0.Because of INPUT=1, the second film
Transistor M2 is opened, and the effective impulse signal for inputting a signal into end INPUT inputs is exported to first node P1, is first node P1
Charge, the current potential of first node P1 is drawn high to high level；Meanwhile, first film transistor M1 is opened, by reference signal end VSS
Reference signal export to signal output part G [N], make signal output part G [N] export low level, realize the time period to letter
The noise reduction process of number output end G [N]；Additionally, when the current potential of first node P1 is high level, the 7th thin film transistor (TFT) M7, the
Eight thin film transistor (TFT) M8, the 13rd thin film transistor (TFT) M13 and the 14th thin film transistor (TFT) M14 are opened, respectively by reference signal
The reference signal of end VSS is exported to Section Point P2, the 3rd node P3, fourth node P4 and the 5th node P5, makes this four
The current potential of node keeps low level.
In T2 stages, INPUT=0, CLK=1, VDD1=1, VDD2=0, RESET=0.Because of CLK=1, first node P1
Current potential be high level, the 3rd thin film transistor (TFT) M3 open, the clock signal of clock signal terminal CLK is exported to signal output part
G [N], makes signal output part G [N] export high level signal, and by Nth row grid line corresponding with the shift register, opens
The all thin film transistor (TFT)s being located in the viewing area of liquid crystal panel on Nth row grid line, data wire starts write signal；Meanwhile,
Because of the boot strap of electric capacity C, the current potential of first node P1 is further pulled up；Therefore the T2 stages are the opening of the shift register
Stage.
In T3 stages, INPUT=0, CLK=0, VDD1=1, VDD2=0, RESET=0.Because of CLK=0, and first node
The current potential of P1 is high level, and the 3rd thin film transistor (TFT) M3 keeps it turned on, the clock signal of clock signal terminal CLK is exported to signal
Output end G [N], makes signal output part G [N] export low level signal；Simultaneously as the boot strap of electric capacity C, by first node
The current potential of P1 is pulled low to normal high level.
In T4 stages, INPUT=0, CLK=0, VDD1=1, VDD2=0, RESET=1.Because of RESET=1, the 4th film
Transistor M4 is opened, and the reference signal of reference signal end VSS is exported to first node P1, and the current potential of first node P1 is dragged down
To low level；Meanwhile, because of VDD1=1, the 5th thin film transistor (TFT) M5 is opened, by the first control letter of the first control signal end VDD1
Number export to the 3rd node P3；Because the current potential of the 3rd node P3 is high level, the 6th thin film transistor (TFT) M6 is opened, by the first control
First control signal of signal end VDD1 processed is exported to Section Point P2；Now, it is the first control signal end in Section Point P2
During first control signal of VDD1, the 9th thin film transistor (TFT) M9 and the tenth thin film transistor (TFT) M10 is opened, by reference signal end VSS
Reference signal export respectively to first node P1 and signal output part G [N], realize to first node P1 and signal output part G
The noise reduction process of [N]；In addition, because of VDD2=0, the 11st thin film transistor (TFT) M11 and the 12nd thin film transistor (TFT) M12 is in cut-off
State so that the current potential of fourth node P4 and the 5th node P5 is low level, so cause the 15th thin film transistor (TFT) M15 and
16th thin film transistor (TFT) M16 is in cut-off state.
Hereafter, until the appearance in T1 stages next time, i.e. INPUT=1, CLK=0, VDD1=1, VDD2=0, RESET
=0, the reference signal of reference signal end VSS is exported to signal output part G [N] using first film transistor M1, it is right to realize
The noise reduction process of signal output part G [N], improves the stability of the gated sweep signal of signal output part G [N] outputs.
Illustrate above and simply illustrated with the shift register shown in Fig. 2 d, it is provided in an embodiment of the present invention
Shift register can realize that here is not limited by increasing noise reduction module 40 in the shift register of any prior art
It is fixed.
Specifically, in order to prove above-mentioned shift register provided in an embodiment of the present invention signal output part G [N] export
The stability of gated sweep signal, by above-mentioned shift register provided in an embodiment of the present invention and shift LD of the prior art
The signal output part of device carries out output signal simulation, as a result as shown in Figs. 4a and 4b；Wherein, Fig. 4 a are simulation knot at room temperature
Really, illustration represents enlarged drawing of the time in 75 microseconds to the analog result between 105 microseconds, and Fig. 4 b are that normal work 10000 is little
When after analog result under room temperature, illustration represents enlarged drawing of the time in 60 microseconds to the analog result between 85 microseconds, and schemes
Abscissa time (s) in 4a and 4b represents the time of the signal output part output signal of shift register, ordinate
Voltage (V) represents the signal magnitude of the signal output part output of shift register；By comparative simulation result, in pixel
In the holding stage of voltage, the signal noise of the signal output part output of above-mentioned shift register provided in an embodiment of the present invention will
It is and little in normal work 10000 significantly lower than the signal noise that the signal output part of shift register of the prior art is exported
Shi Hou, the signal noise of the signal output part output of above-mentioned shift register provided in an embodiment of the present invention is still less, and believes
It is number relatively stable；Therefore, the setting of noise reduction module 40, significantly reduces holding stage of the shift register in pixel voltage
Noise, while improve the stability of the gated sweep signal of signal output part G [N] outputs of shift register.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of grid integrated drive electronics, can include level
The above-mentioned shift register multiple provided in an embodiment of the present invention of connection；Wherein,
The signal output part of N level shift registers resets to the reset signal end input of N+1 level shift registers and believes
Number, or reset signal is input into the reset signal end of N+2 level shift registers, and to the signal of N-1 level shift registers
Input is input into effective impulse signal, and N is the integer more than 1.
Specifically, noise reduction module 40 for convenience of explanation in shift registers at different levels is between shift registers at different levels
Effect and annexation, in above-mentioned grid integrated drive electronics provided in an embodiment of the present invention, as shown in figure 5, the first clock
Signal end CLK1 and second clock signal end CLK2 are respectively shift registers at different levels and provide clock signal, the first control signal end
VDD1 and the second control signal end VDD2 provide control signal for shift registers at different levels, and reference signal end VSS is displacements at different levels
Register provides reference signal；Also, illustrate only five shift registers in Fig. 5, respectively N-2 levels shift register,
N-1 level shift registers, N level shift registers, N+1 level shift registers, N+2 level shift registers；Wherein,
The signal output part G [N] of N level shift registers not only resets to the reset signal end RESET inputs of N+2 level shift registers
Signal, is also input into effective impulse signal to the signal input part INPUT of N-1 level shift registers；Effective arteries and veins is utilized simultaneously
Signal is rushed, the noise reduction module 40 in N-1 level shift registers is controlled, the signal output part G of N-1 level shift registers is maintained
The current potential of [N-1] is low level in the holding stage of pixel voltage, eliminates signal output of the noise to N-1 level shift registers
The interference at end G [N-1].
Additionally, Fig. 6 gives the signal output part of shift registers at different levels and the annexation of noise reduction module equivalent capacity
Schematic diagram, wherein, the noise of the signal output part of every grade of shift register can be by noise reduction mould in this grade of shift register
The equivalent capacity coupling of block is discharged into reference signal end VSS, makes the current potential of signal output part of this grade of shift register stably
Maintain low level；In addition, when the noise reduction module in N level shift registers loses decrease of noise functions, noise can be by electricity
In holding coupled to the N-1 levels shift register that is connected with N level shift registers or N+1 level shift registers, by the
Noise coupling is discharged into reference signal end VSS by the noise reduction module in N-1 levels shift register or N+1 level shift registers,
Noise is eliminated, so as to realize that the noise of signal output part of shift registers at different levels is cancelled out each other (sharing), and then is improved whole
Individual grid integrated drive electronics exports the stability of gated sweep signal.
Specifically, each shift register in above-mentioned grid integrated drive electronics provided in an embodiment of the present invention is concrete
Structure and above-mentioned shift register all same in function and structure provided in an embodiment of the present invention, repeat part and repeat no more.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display device, can include present invention enforcement
The above-mentioned grid integrated drive electronics that example is provided, it is embodied as can be found in the integrated drive of above-mentioned grid provided in an embodiment of the present invention
Dynamic circuit description, something in common is repeated no more.
In the specific implementation, the embodiment of the present invention additionally provides a kind of driving method of shift register, with reference to Fig. 2 c institutes
Input and output sequential chart shown in the shift register for showing and Fig. 3, can include：
In first time period, input module 10, will under the control of the effective impulse signal that signal input part INPUT is input into
The effective impulse signal of signal input part INPUT is provided to first node P1；Noise reduction module 40 is input in signal input part INPUT
Effective impulse signal control under, the reference signal of reference signal end VSS is provided to signal output part G [N]；
In second time period, output control module 20 under the control of first node P1, by the clock of clock signal terminal CLK
Signal is provided to signal output part G [N]；
In the 4th time period, reseting module 30 under the control of the reset signal of reset signal end RESET, by reference signal
The reference signal of end VSS is provided to first node P1.
Specifically, in the driving method of above-mentioned shift register provided in an embodiment of the present invention, with reference to Fig. 2 c and Fig. 2 d
Input and output sequential chart shown in shown shift register and Fig. 3, can also include：
In first time period, second time period and the 3rd time period, the first drop-down control module 50 is in first node P1
For signal input part INPUT input effective impulse signal when, the reference signal of reference signal end VSS is provided to Section Point
P2；
In the 4th time period, the first drop-down control module 50 is the input of the first control signal end VDD1 in Section Point P2
During the first control signal, the reference signal of reference signal end VSS is provided respectively to first node P1 and signal output part G [N].
Embodiments provide a kind of shift register, its driving method, grid integrated drive electronics and show dress
Put, the shift register includes input module, under the control for the effective impulse signal being input in signal input part, will be effective
Pulse signal is provided to first node；Output control module, under the control of first node, by the clock of clock signal terminal
Signal is provided to signal output part；Reseting module, under the control of the reset signal at reset signal end, by reference signal end
Reference signal provide to first node；Also include being connected between signal input part, reference signal end and signal output part
Noise reduction module, under the control for the effective impulse signal being input in signal input part, by the reference signal at reference signal end
There is provided to signal output part；Therefore, by setting up noise reduction module in existing shift register, in signal input part input
Under the control of effective impulse signal, using the reference signal at reference signal end, the noise jamming to signal output part is reduced；Together
When, in the grid integrated drive electronics being made up of the above-mentioned shift register multiple provided in an embodiment of the present invention for cascading, profit
With the annexation between the signal output part of the noise reduction module in shift registers at different levels and shift register at different levels, when one
During the signal output part output abnormality of shift register, noise coupling extremely can be posted with this grade of adjacent displacement of shift register
Noise reduction module in storage, reference signal end is discharged into by the noise reduction module by noise coupling, eliminates noise, makes displacements at different levels
The noise of the signal output part of register is cancelled out each other, and while the ability of shift register removal noise is improved, improves grid
The stability of the gated sweep signal of pole integrated drive electronics output.
Obviously, those skilled in the art can carry out the essence of various changes and modification without deviating from the present invention to the present invention
God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising these changes and modification.
Claims (10)
1. a kind of shift register, including：The input module being connected between signal input part and first node, for described
Under the control of the effective impulse signal of signal input part input, effective impulse signal is provided to the first node；It is connected to
The first node, the output control module between clock signal terminal and signal output part, in the first node
Under control, the clock signal of the clock signal terminal is provided to the signal output part；It is connected to reset signal end, reference letter
Reseting module number between end and the first node, under the control of the reset signal at the reset signal end, will
The reference signal at the reference signal end is provided to the first node；Characterized in that, also including：
The noise reduction module being connected between the signal input part, the reference signal end and the signal output part, is used for
Under the control of the effective impulse signal of signal input part input, the reference signal at the reference signal end is provided to institute
State signal output part.
2. shift register as claimed in claim 1, it is characterised in that the noise reduction module, including：The first film crystal
Pipe；Wherein,
The grid of the first film transistor is connected with the signal input part, and source electrode is connected with the reference signal end, leakage
Pole is connected with the signal output part.
3. shift register as claimed in claim 1, it is characterised in that the input module, including：Second film crystal
Pipe；Wherein,
The grid and source electrode of second thin film transistor (TFT) is connected with the signal input part, drains and the first node phase
Even.
4. shift register as claimed in claim 1, it is characterised in that the output control module, including：3rd film is brilliant
Body pipe and electric capacity；Wherein,
The grid of the 3rd thin film transistor (TFT) is connected with the first node, and source electrode is connected with the clock signal terminal, drain electrode
It is connected with the signal output part；
Capacitance connection is between the first node and the signal output part.
5. shift register as claimed in claim 1, it is characterised in that the reseting module, including：4th film crystal
Pipe；Wherein,
The grid of the 4th thin film transistor (TFT) is connected with the reset signal end, and source electrode is connected with the reference signal end, leakage
Pole is connected with the first node.
6. the shift register as described in any one of claim 1-5, it is characterised in that also include：
It is connected between the first control signal end, the first node, the reference signal end and the signal output part
First drop-down control module, under the control of the first node, by the reference signal at the reference signal end provide to
Section Point, in the first control signal that the Section Point is the first control signal end input, by described with reference to letter
Number end reference signal provide respectively to the first node and the signal output part；
It is connected between the second control signal end, the first node, the reference signal end and the signal output part
Second drop-down control module, under the control of the first node, by the reference signal at the reference signal end provide to
Fourth node, in the second control signal that the fourth node is the second control signal end input, by described with reference to letter
Number end reference signal provide respectively to the first node and the signal output part；
First control signal end replaces input control signal with second control signal end.
7. shift register as claimed in claim 6, it is characterised in that the first drop-down control module, including：5th is thin
Film transistor, the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th thin film transistor (TFT), the 9th thin film transistor (TFT) and the tenth
Thin film transistor (TFT)；Wherein,
The grid and source electrode of the 5th thin film transistor (TFT) is connected with first control signal end, drains and the 3rd node phase
Even；
The grid of the 6th thin film transistor (TFT) is connected with the 3rd node, and source electrode is connected with first control signal end,
Drain electrode is connected with the Section Point；
The grid of the 7th thin film transistor (TFT) is connected with the first node, and source electrode is connected with the reference signal end, drain electrode
It is connected with the 3rd node；
The grid of the 8th thin film transistor (TFT) is connected with the first node, and source electrode is connected with the reference signal end, drain electrode
It is connected with the Section Point；
The grid of the 9th thin film transistor (TFT) is connected with the Section Point, and source electrode is connected with the reference signal end, drain electrode
It is connected with the first node；
The grid of the tenth thin film transistor (TFT) is connected with the Section Point, and source electrode is connected with the reference signal end, drain electrode
It is connected with the signal output part；
The second drop-down control module, including：11st thin film transistor (TFT), the 12nd thin film transistor (TFT), the 13rd film are brilliant
Body pipe, the 14th thin film transistor (TFT), the 15th thin film transistor (TFT) and the 16th thin film transistor (TFT)；Wherein,
The grid of the 11st thin film transistor (TFT) is connected with source electrode with second control signal end, drains and the 5th node
It is connected；
The grid of the 12nd thin film transistor (TFT) is connected with the 5th node, source electrode and the second control signal end phase
Even, drain electrode is connected with the fourth node；
The grid of the 13rd thin film transistor (TFT) is connected with the first node, and source electrode is connected with the reference signal end, leakage
Pole is connected with the 5th node；
The grid of the 14th thin film transistor (TFT) is connected with the first node, and source electrode is connected with the reference signal end, leakage
Pole is connected with the fourth node；
The grid of the 15th thin film transistor (TFT) is connected with the fourth node, and source electrode is connected with the reference signal end, leakage
Pole is connected with the first node；
The grid of the 16th thin film transistor (TFT) is connected with the fourth node, and source electrode is connected with the reference signal end, leakage
Pole is connected with the signal output part.
8. a kind of grid integrated drive electronics, it is characterised in that including the multiple as described in any one of claim 1-7 of cascade
Shift register；Wherein,
The signal output part of N level shift registers to the reset signal end of N+1 level shift registers is input into reset signal, or
Reset signal is input into the reset signal end of N+2 level shift registers, and to the signal input part of N-1 level shift registers
Input effective impulse signal, and N is the integer more than 1.
9. a kind of display device, it is characterised in that including grid integrated drive electronics as claimed in claim 8.
10. a kind of driving method of the shift register as described in any one of claim 1-7, it is characterised in that include：
In first time period, input module is defeated by the signal under the control of the effective impulse signal that signal input part is input into
The effective impulse signal for entering end is provided to first node；The effective impulse signal that noise reduction module is input in the signal input part
Under control, the reference signal at reference signal end is provided to signal output part；
In second time period, output control module carries the clock signal of clock signal terminal under the control of the first node
It is supplied to the signal output part；
In the 4th time period, reseting module under the control of the reset signal at reset signal end, by the ginseng at the reference signal end
Examine signal to provide to the first node.
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Application publication date: 20170510 |