CN110782940A - Shift register unit, gate drive circuit, array substrate and display device - Google Patents

Shift register unit, gate drive circuit, array substrate and display device Download PDF

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Publication number
CN110782940A
CN110782940A CN201911121155.XA CN201911121155A CN110782940A CN 110782940 A CN110782940 A CN 110782940A CN 201911121155 A CN201911121155 A CN 201911121155A CN 110782940 A CN110782940 A CN 110782940A
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China
Prior art keywords
pull
node
thin film
film transistor
circuit
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CN201911121155.XA
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Chinese (zh)
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CN110782940B (en
Inventor
曹诚英
谢勇贤
蒋学兵
周纪登
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Abstract

The embodiment of the application provides a shift register unit, a gate drive circuit, an array substrate and a display device. The shift register comprises an input sub-circuit, a cut-off sub-circuit, an output sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit and a first reset sub-circuit. This application is through increasing the sub-circuit that cuts off between input sub-circuit and output sub-circuit, it can selectively switch on or break to cut off the sub-circuit, consequently, both can make first pull-up node and second pull-up node connect and be in same electric potential through making cut off the sub-circuit and switch on, also can control and cut off the sub-circuit disconnection so that first pull-up node and second pull-up node are in the off-state, thereby make the electric potential of second pull-up node not receive the influence of second pull-down sub-circuit, consequently, even thin film transistor in the pull-down sub-circuit takes place the drift, the condition that the second pull-up node can not take place to charge inadequately, thereby make the output can normal output signal.

Description

Shift register unit, gate drive circuit, array substrate and display device
Technical Field
The application relates to the technical field of display, in particular to a shift register unit, a gate drive circuit, an array substrate and a display device.
Background
The goa (gate Driver On array) technology is an array substrate line driving technology, which is a driving method for manufacturing a gate driving circuit of a display area On a Thin Film Transistor (TFT) array substrate to scan the display area line by line, and has the advantages of reducing production cost and realizing a narrow frame design of a panel, and has been widely applied to various display devices.
The gate driving circuit generally includes a plurality of cascaded shift register units including a plurality of TFTs, and the characteristics of the TFTs inevitably drift with the lapse of usage time. When the characteristics of some TFTs in the shift register unit drift, the voltage of the pull-up node cannot be sufficiently raised in the pull-up stage, so that the subsequent signal output is affected, i.e., the problem of insufficient charging of the pull-up node is caused, which is a serious stubborn problem of the GOA product.
Disclosure of Invention
The application provides a shift register unit, a gate driving circuit, an array substrate and a display device aiming at the defects of the prior art, and aims to solve the technical problem that a pull-up node in the shift register unit is not charged sufficiently in the prior art.
In a first aspect, an embodiment of the present application provides a shift register unit, including:
an input sub-circuit, respectively connected to an input terminal and a first pull-up node, configured to be turned on or off based on a signal received by the input terminal, so as to determine whether to pass a signal received by the receiving terminal to the first pull-up node;
a turn-off sub-circuit respectively connected to the input terminal, the first pull-up node, the second pull-up node, and the pull-down node, and configured to be turned on or off based on a received signal of the input terminal or based on a potential of the pull-down node, thereby controlling connection or disconnection of the first pull-up node and the second pull-up node;
an output sub-circuit connected to the second pull-up node, the first clock signal terminal, and the output terminal, respectively, and configured to control whether a signal received by the first clock signal terminal is output by the output terminal based on a potential of the second pull-up node;
the pull-down control sub-circuit comprises a first pull-down control sub-circuit and a second pull-down control sub-circuit, wherein the first pull-down control sub-circuit is respectively connected with a second clock signal terminal and the pull-down node and is configured to be switched on or switched off based on a signal received by the second clock signal terminal so as to transmit the signal received by the second clock signal terminal to the pull-down node or not; the second pull-down control sub-circuit is respectively connected with the first pull-up node, the pull-down node and a power supply low-voltage end, and is configured to control whether the pull-down node and the power supply low-voltage end are conducted or not based on the potential of the first pull-up node, so as to control whether the potential of the pull-down node is pulled down or not;
a pull-down sub-circuit, respectively connected to the first pull-up node, the pull-down node, the output terminal, and the power low-voltage terminal, and configured to control whether to conduct between the first pull-up node and the power low-voltage terminal and between the output terminal and the power low-voltage terminal based on a potential of the pull-down node, so as to control whether potentials of the first pull-up node and the output terminal are pulled down;
the first reset sub-circuit is respectively connected with the first reset terminal, the first pull-up node and the power low-voltage terminal, and is configured to control whether the first pull-up node and the power low-voltage terminal are conducted or not based on a signal received by the first reset terminal, so as to control whether the potential of the first pull-up node is pulled down or not, wherein the signal received by the first reset terminal is the same as a gate drive signal output by the next-stage shift register unit.
In a second aspect, an embodiment of the present application provides a gate driving circuit, where the gate driving circuit includes a plurality of cascaded shift register units as described above; the plurality of cascaded shift register units comprise an (n-k) th stage shift register unit, an nth stage shift register unit and an (n + k) th stage shift register unit, wherein the input end of the nth stage shift register unit is connected with the output end of the (n-k) th stage, the output end of the nth stage shift register unit is connected with the input end of the (n + k) th stage, k is an integer greater than or equal to 1, and n is an integer greater than or equal to 2.
In a third aspect, the present application provides an array substrate, and the gate driving circuit of the array substrate is provided.
In a fourth aspect, an embodiment of the present application provides a display device, which includes a power supply, a driving chip, and the array substrate.
The technical scheme provided by the embodiment of the application has the following beneficial technical effects:
the application provides a shift register unit, gate drive circuit, array substrate and display device, through increase the end subcircuit between input subcircuit and output subcircuit, end subcircuit can selectively switch on or break off, therefore, can enough make first pull-up node and second pull-up node connect so that first pull-up node and second pull-up node are in same electric potential, also can make first pull-up node and second pull-up node be in the off-state, so that the electric potential of second pull-up node can not receive the influence of the pull-down subcircuit of being connected with first pull-up node, consequently, even the characteristic of the thin film transistor in the pull-down subcircuit drifts, the condition that the second pull-up node can not take place the undercharge yet, thereby guarantee that the output can normally output signal.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a diagram illustrating a shift register unit according to the related art;
FIG. 2 is a timing diagram illustrating a shift register unit according to the related art;
fig. 3 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of another shift register unit according to an embodiment of the present disclosure;
FIG. 5 is a circuit diagram of a shift register unit according to an embodiment of the present disclosure;
FIG. 6 is a driving timing diagram corresponding to the shift register unit shown in FIG. 5; FIG. 7 is a circuit diagram of another shift register unit according to an embodiment of the present disclosure;
FIG. 8 is a driving timing diagram corresponding to the shift register unit shown in FIG. 7;
fig. 9 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure;
fig. 10 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present application.
Reference numerals:
10-an input sub-circuit; 20-a cut-off sub-circuit; 30-an output sub-circuit; 40-a pull-down control sub-circuit; 401-a first pull-down control sub-circuit; 402-a second pull-down control sub-circuit; 50-a pull-down sub-circuit; 60-a first reset sub-circuit; 70-a second reset sub-circuit;
Input-Input; an OUT-output terminal; OUT1 — a first output; OUT2 — second output terminal; PU1 — first pull-up node; PU2 — second pull-up node; PD-a pull-down node; PD _ CN-pull-down control node; VGL-Power Low Voltage terminal; VGL1 — first power supply low voltage terminal; VGL 2-second supply low voltage terminal; CLK 1-the first clock signal terminal, CLK 2-the second clock signal terminal;
t1 — first thin film transistor; t2 — a second thin film transistor; t3 — a third thin film transistor; t4 — fourth thin film transistor; t5 — fifth thin film transistor; t6-a sixth thin film transistor; t7-seventh thin film transistor; t8-eighth thin film transistor; t9 — ninth thin film transistor; t10-tenth thin film transistor; t11-eleventh filmA film transistor; t12 — a twelfth thin film transistor; t is dg-a double gate thin film transistor; c-storage capacitance;
unit-shift register Unit; GL-gate line signal lines; a DL-data line; TD-thin film transistor of the drive sub-pixel; p-sub-pixel.
Detailed Description
Reference will now be made in detail to the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. In addition, if a detailed description of the known art is not necessary for illustrating the features of the present application, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
The inventor of the present application considers that the characteristics of the TFTs inevitably drift with the use time, and when the characteristics of some TFTs in the shift register unit drift, the voltage of the pull-up node cannot be sufficiently raised in the pull-up stage, i.e. the pull-up node is insufficiently charged, which may affect the subsequent signal output of the GOA circuit.
Taking the shift register unit shown in fig. 1 as an example, the shift register unit includes thin film transistors M1, M2, M3, and M4, and a storage capacitor C.
Referring to fig. 1 and fig. 2, the driving process mainly includes the following stages: in the first stage I, the Input terminal Input inputs a high level, M1 is turned on and precharges the pull-up node PU, the pull-up node PU is at a high level, the gate of M2 and the pull-up node are at the same potential, that is, the gate of M2 is also at a high level, so that M2 is turned on; in the second stage II, the clock signal terminal CLK inputs a high level, and M2 is still turned on, so that the high level of the clock signal can be Output from the Output terminal Output, and in this process, due to the bootstrap effect of the storage capacitor C, the voltage of the pull-up node PU is further increased; in the third phase III, the Reset terminal Reset inputs a high level, M3 and M4 turn on and write the power low voltage signal VGL to the pull-up node PU, thereby resetting the voltage of the pull-up node PU.
As the TFT has a characteristic that drifts with the increase of the using time, for example, if M4 drifts, so that M4 is turned on in the first stage I or the second stage II, the low voltage terminal VGL of the power supply is turned on with the pull-up node PU, and the voltage of the pull-up node PU is pulled down, so that the pull-up node PU is insufficiently charged, that is, the potential of the pull-up node PU in the first stage I is not enough to turn on M2, so that the Output terminal Output cannot Output a corresponding signal, and the pixels in the corresponding row cannot be normally driven.
The shift register unit, the gate driving circuit, the array substrate and the display device provided by the embodiment of the application aim to solve the above technical problems in the prior art.
The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.
The embodiment of the present application provides a shift register unit, as shown in fig. 3, the shift register unit includes an input sub-circuit 10, an off sub-circuit 20, an output sub-circuit 30, a pull-down control sub-circuit 40, a pull-down sub-circuit 50, and a first reset sub-circuit 60.
The Input sub-circuit 10 is respectively connected to the Input terminal Input and the first pull-up node PU1, and is configured to control whether to transmit a signal received by the receiving terminal Input to the first pull-up node PU1 based on whether a signal received by the Input terminal Input is turned on or off. Specifically, when the signal Input by the Input terminal is an enable signal, the Input sub-circuit 10 is turned on and transmits the enable signal to the first pull-up node PU1 to charge the first pull-up node PU 1.
The turn-off sub-circuit 20 is respectively connected to the Input terminal Input, the first pull-up node PU1, the second pull-up node PU2, and the pull-down node PD, and configured to turn on or off based on a signal of the Input terminal Input or based on a potential of the pull-down node PD, thereby controlling connection or disconnection of the first pull-up node PU1 and the second pull-up node PU 2. Since the cut-off sub-circuit 20 and the Input sub-circuit 10 are controlled by the signal received by the Input terminal Input at the same time, the Input sub-circuit 20 and the cut-off sub-circuit 20 can be turned on at the same time, so that the first pull-up node PU1 is connected to the second pull-up node PU2, and the second pull-up node PU2 keeps the same potential as the first pull-up node in the process; when the Input sub-circuit 10 is turned off by a signal received by the Input terminal, the turn-off sub-circuit 20 is turned on or off according to the potential of the pull-down node PD.
The output sub-circuit 30, respectively connected to the second pull-up node PU2, the first clock signal terminal CLK1, and the input terminal OUT, is configured to control whether the signal received by the first clock signal terminal CLK1 is output from the output terminal OUT based on the potential of the second pull-up node PU 2. Specifically, when the output sub-circuit 30 is turned on by the potential of the second pull-up node PU2, the output terminal OUT outputs the current signal of the first clock signal terminal CLK, for example, the TFT controlling the pixel to be turned on is an N-type TFT, and when the output sub-circuit 30 is turned on by the potential of the second pull-up node PU2, the first clock signal output by the output terminal OUT should include a high level as the gate driving signal, and the gate driving signal also serves as the on signal of the input terminal of the next stage of shift register unit.
The pull-down control sub-circuit 40 includes a first pull-down control sub-circuit 401 and a second pull-down control sub-circuit 402, the first pull-down control sub-circuit 401 is respectively connected to the second clock signal terminal CLK2 and the pull-down node PD, and is configured to control whether to transfer a signal received by the second clock signal terminal to the pull-down node PD based on turning on or off of a signal received by the second clock signal terminal CLK2, the second pull-down control sub-circuit 402 is respectively connected to the first pull-up node PU1, the pull-down node PD, and the power low-voltage terminal VGL, and is configured to control whether the pull-down node PD is turned on with the power low-voltage terminal VGL based on a potential of the first pull-up node PU1, so as to control whether a potential of the pull-down node PD is pulled down.
Specifically, when the first pull-down control sub-circuit 401 is turned on to transmit the second clock signal to the pull-down structure PD to charge the pull-down node PD, and the second pull-down control sub-circuit 402 controlled by the first pull-up node PU1 is turned off, the potential of the pull-down node PD can rise, and as long as the second pull-down control sub-circuit 402 is in the on state, the potential of the pull-down node PD is at a low level regardless of whether the first pull-down control sub-circuit 401 charges the pull-down node PD or not, because the pull-down node PD is connected to the power supply voltage input terminal VGL.
It should be noted that the potential of the signal received by the second clock terminal CLK2 is usually opposite to the potential of the signal received by the first clock terminal CKL1, i.e., the signal received by the second clock terminal CLK2 is at a low level when the signal received by the first clock terminal CLK1 is at a high level, and the signal received by the second clock terminal CLK2 is at a high level when the signal received by the first clock terminal CLK1 is at a low level.
The pull-down sub-circuit 50 is respectively connected to the first pull-up node PU1, the pull-down node PD, the output terminal OUT and the power low-voltage terminal VGL, and configured to control whether conduction is performed between the first pull-up node PU1 and the power low-voltage terminal VGL and between the output terminal OUT and the power low-voltage terminal VGL based on the potential of the pull-down node PD, so as to control whether potentials of the first pull-up node PU1 and the output terminal OUT are pulled down. Specifically, both the cut-off sub-circuit 20 and the pull-down sub-circuit 50 can be controlled by the pull-down node PD, and therefore, the cut-off sub-circuit 20 and the pull-down sub-circuit 50 can be turned on simultaneously, wherein the cut-off sub-circuit 20 is turned on to connect the first pull-up node PU1 and the second pull-up node PU2, and the pull-down sub-circuit 50 is turned on to turn on the first pull-up node PU1 and the power low-voltage terminal VGL and the output terminal OUT and the power low-voltage terminal VGL, so that the potentials of the first pull-up node PU1, the second pull-up node PU2 and the output terminal OUT can be simultaneously pulled down to implement noise reduction of the shift register unit.
The first Reset sub-circuit 60 is respectively connected to the first Reset terminal Reset, the first pull-up node PU1 and the power low voltage terminal VGL, and is configured to control whether the first pull-up node PU1 and the power low voltage terminal VGL are turned on based on a signal received by the first Reset terminal Reset, so as to control whether the potential of the first pull-up node PU1 is pulled down. The first Reset terminal Reset receives the same signal as the gate driving signal output by the next stage of shift register unit.
In the shift register unit of the embodiment, the cut-off sub-circuit 20 is added between the input sub-circuit 10 and the output sub-circuit 30, and the cut-off sub-circuit 20 can be selectively turned on or off, so that the first pull-up node PU1 and the second pull-up node PU2 can be connected to make the first pull-up node PU1 and the second pull-up node PU2 at the same potential, and the first pull-up node PU1 and the second pull-up node PU2 can be in a cut-off state, so that the potential of the second pull-up node PU2 is not affected by the pull-down sub-circuit 50 connected to the first pull-up node PU1, and therefore, even if the characteristics of the thin film transistor in the pull-down sub-circuit 50 drift, the second pull-up node PU2 will not be under-charged, and the explosion output terminal OUT can normally output signals.
Further, as shown in fig. 4, the shift register unit of the present embodiment further includes a second reset sub-circuit 70, where the second reset sub-circuit 70 is respectively connected to the second reset terminal TRST, the first pull-up node PU1 and the power low voltage terminal VGL, and is configured to control whether the first pull-up node PU1 and the power low voltage terminal VGL are turned on or not based on a signal received by the second reset terminal TRST; the signal received by the second reset terminal TRST is a total reset signal when the display of one frame of picture is completed.
In the shift register units provided in this embodiment, the second reset sub-circuit 70 is arranged to perform a total reset on all the shift register units once again when the display of each frame is completed, and if the potential of the first pull-up node PU1 in some shift register units is not pulled down sufficiently, the first pull-up structure PU1 is connected to the power low voltage terminal VGL by a total reset signal, so that the potential of the PU1 of the first pull-up node in the shift register units that are not pulled down sufficiently can be further pulled down to further reduce noise.
The shift register unit shown in fig. 3 can be embodied as the circuit configuration shown in fig. 5. The specific structure of each sub-circuit in the shift register unit of the present embodiment will be described in detail below with reference to fig. 5.
As shown in FIG. 5, the turn-off sub-circuit 20 includes a double-gate thin film transistor T dgDouble-grid thin film transistor T dgThe first grid g1, the second grid g2, the first electrode S and the second electrode D are included, the first grid g1 is connected with the Input end Input, the second grid g2 is connected with the pull-down node PD, the first electrode S is connected with the first pull-up node PU1, and the second electrode D is connected with the second pull-up node PU 2.
As shown in fig. 5, the Input sub-circuit 10 includes a first thin film transistor T1, a gate and a first electrode of the first thin film transistor T1 are both connected to the Input terminal Input, and a second electrode of the first thin film transistor T1 is connected to the first pull-up node PU 1.
As shown in fig. 5, the first Reset sub-circuit 60 includes a second thin film transistor T2, a gate of the second thin film transistor T2 is connected to the first Reset terminal Reset, a first electrode of the second thin film transistor T2 is connected to the first pull-up node PU1, and a second electrode of the second thin film transistor T2 is connected to the power supply low voltage terminal VGL.
As shown in fig. 5, the output sub-circuit 30 includes a third tft T3 and a storage capacitor C, a gate of the third tft T3 is connected to the second pull-up node PU2, a first electrode of the third tft T3 is connected to the first clock signal terminal CLK1, and a second electrode of the third tft T3 is connected to the output terminal OUT; a first electrode of the storage capacitor C is connected to the second pull-up node PU2, and a second electrode of the storage capacitor C is connected to the second electrode of the third thin film transistor T3.
As shown in fig. 5, the pull-down sub-circuit 50 includes a fourth thin film transistor T4 and a fifth thin film transistor T5. A gate of the fourth thin film transistor T4 is connected to the pull-down node PD, a first electrode of the fourth thin film transistor T4 is connected to the output terminal OUT, and a second electrode of the fourth thin film transistor T4 is connected to the power supply low voltage terminal VGL; a gate of the fifth thin film transistor T5 is connected to the pull-down node PD, a first electrode of the fifth thin film transistor T5 is connected to the first pull-up node PU1, and a second electrode of the fifth thin film transistor T5 is connected to the power source low voltage terminal VGL.
As shown in fig. 5, the first pull-down control sub-circuit 401 includes a sixth thin film transistor T6, a gate and a first electrode of the sixth thin film transistor T6 are connected to the second clock signal terminal CLK2, and a second electrode of the sixth thin film transistor T6 is connected to the pull-down node PD.
As shown in fig. 5, the second pull-down control sub-circuit 402 includes a seventh thin film transistor T7, a gate of the seventh thin film transistor T7 is connected to the first pull-up node PU1, a first electrode of the seventh thin film transistor T7 is connected to the pull-down node PD, and a second electrode of the seventh thin film transistor T7 is connected to the power low voltage terminal VGL.
It should be noted that the circuit structure shown in fig. 5 is only an exemplary illustration, and the shift register unit shown in fig. 3 can be implemented as other circuit structures, for example, the GOA architecture of 15T1C, the GOA architecture of 17T1C, the GOA architecture of 18T1C, the GOA architecture of 19T1C, and the like, which are not listed herein.
Fig. 6 shows a timing diagram of the shift register unit shown in fig. 5, and the operation of the shift register unit shown in fig. 5 will be described in detail below with reference to fig. 5 and 6 by taking the example that each thin film transistor is an N-type transistor. The driving process of the shift register unit shown in FIG. 5 mainly includes a first stage I, a second stage II and a third stage III.
As shown in fig. 5 and 6, in the first stage I, the Input terminal Input inputs a high level, the first thin film transistor T1 and the dual gate thin film transistor T dgAre turned on, the Input terminal inputs charges the storage capacitor C, and precharges the first pull-up node PU1 and the second pull-up node PU2, so that the voltages of the first pull-up node PU1 and the second pull-up node PU2 are at a high level. And the voltage of the second pull-up node PU2 is at a high level so that the third thin film transistor T3 is turned on, thereby outputting a low level inputted from the first clock signal terminal CLK1 from the output terminal OUT.
In this process, the second clock signal terminal CLK2 is inputted with a high level, the sixth thin film transistor T6 is turned on, the pull-down node PD is charged, the first pull-up node PU1 is also at a high level, and the potential of the first pull-up node PU1 and the potential of the pull-down node PD are in a competition relationship, at this time, whether the seventh thin film transistor T7 controlled by the first pull-up node PU1 is turned on or the fourth thin film transistor T4 and the fifth thin film transistor T5 controlled by the pull-down node PD are turned on will determine whether the potential of the first pull-up node PU1 is pulled low or the potential of the pull-down node PD is pulled low in the competition relationship.
For a thin film transistor, the aspect ratio of the channel is one of the important factors affecting the performance of the thin film transistor, and it is generally considered that the larger the aspect ratio of the channel, the easier carriers are to migrate, and the easier the thin film transistor is to turn on. In the present embodiment, by designing the width-to-length ratio of each thin film transistor, it can be ensured that the potential of the pull-down node PD is pulled down and the first pull-up node PU1 is pulled up to a desired potential in the first stage I. For example, setting the width-to-length ratio of the channel of the seventh thin film transistor T7 to be greater than the width-to-length ratios of the channels of the fourth thin film transistor T4 and the fifth thin film transistor T5 enables the seventh thin film transistor T7 to be preferentially turned on in the above contention, thereby connecting the pull-down node PD with the power supply low voltage terminal VGL to pull down the potential of the pull-down node PD, so that the fourth thin film transistor T4 and the fifth thin film transistor T5 controlled by the pull-down node PD are in an off state in the first period I.
As shown in fig. 5 and 6, in the second placeStage II, inputting low level at Input terminal, first TFT T1 and double-gate TFT T dgIs turned off, the first pull-up node PU1 remains high for the first phase I.
In this process, the third tft T3 controlled by the second pull-up node PU2 is still turned on, so that the high level inputted from the first clock signal terminal CLK1 is outputted from the output terminal OUT, and since the second electrode of the storage capacitor C is connected to the output terminal OUT, the second pull-up node PU2 connected to the first electrode of the storage capacitor C is further boosted by the bootstrap effect of the storage capacitor C.
In this process, the sixth tft T6 is turned off when the second clock signal terminal CLK2 inputs a low level, the seventh tft T7 is turned on when the first pull-up node PU1 is at a high level, and the pull-down node PD is turned on with the power low-voltage terminal VGL, so that the pull-down node PD and the power low-voltage terminal VGL are at the same potential, that is, the pull-down node PD is still at a low level, and the fourth tft T4 and the fifth tft T5 are turned off.
As shown in fig. 5 and 6, in the third stage III, the Input terminal Input inputs a low level, the first thin film transistor T1 and the dual gate thin film transistor T dgAre all closed.
In this process, the first Reset terminal Reset writes a high level to turn on the second thin film transistor T2, so that the first pull-up node PU1 is turned on with the power low voltage terminal VGL to rapidly pull down the potential of the first pull-up node PU1, and further turn off the seventh thin film transistor T7 controlled by the first pull-up node PU 1; the sixth thin film transistor T6 is turned on by the high input from the second clock signal terminal CLK2, and thus charges the pull-down node PD, thereby raising the voltage of the pull-down node PD to the high input from the second clock signal terminal CLK 2.
In this process, the pull-down node PD is at a high level, so that the dual-gate tft Tdg is turned on, and thus the first pull-up node PU1 and the second pull-up node PU2 are at the same potential, and the pull-down node PD is at a high level, so that the fourth tft T4 and the fifth tft T5 are turned on, wherein the fourth tft T4 is turned on so that the output terminal OUT is turned on with the power low voltage terminal VGL, so that the voltage of the output terminal OUT is pulled down to a low level; and the fifth thin film transistor T5 is turned on, so that the first pull-up node PU1 and the second pull-down node PU2 are both turned on with the low voltage terminal VGL of the power supply, so as to pull down the voltages of the first pull-up node and the second pull-up node more quickly and sufficiently, thereby performing a function of sufficiently reducing noise.
In this process, the second pull-down node PU2 is at a low level, so that the third tft T3 is turned off, and the output terminal OUT outputs a low level of the power low voltage terminal VGL input.
The shift register unit shown in fig. 4 can be embodied as the circuit configuration shown in fig. 7. The specific structure of each sub-circuit in the shift register unit of the present embodiment will be described in detail below with reference to fig. 7.
As shown in FIG. 7, the turn-off sub-circuit 20 includes a double-gate thin film transistor T dgDouble-grid thin film transistor T dgThe first grid g1, the second grid g2, the first electrode S and the second electrode D are included, the first grid g1 is connected with the Input end Input, the second grid g2 is connected with the pull-down node PD, the first electrode S is connected with the first pull-up node PU1, and the second electrode D is connected with the second pull-up node PU 2.
As shown in fig. 7, the power low-voltage terminal VGL includes a first power low-voltage terminal VGL1 and a second power low-voltage terminal VGL2, and the input of the first power low-voltage terminal VGL1 and the second power low-voltage terminal VGL2 are both low level.
As shown in fig. 7, the Input sub-circuit 10 includes a first thin film transistor T1, a gate and a first electrode of the first thin film transistor T1 are both connected to the Input terminal Input, and a second electrode of the first thin film transistor T is connected to the first pull-up node PU 1.
As shown in fig. 7, the first Reset sub-circuit 60 includes a second thin film transistor T2, a gate of the second thin film transistor T2 is connected to the first Reset terminal Reset, a first electrode of the second thin film transistor T2 is connected to the first pull-up node PU1, and a second electrode of the second thin film transistor T2 is connected to the power supply low voltage terminal VGL.
As shown in fig. 7, the first pull-down control sub-circuit 401 includes a sixth thin film transistor T6 and a tenth thin film transistor T10, a gate and a first electrode of the tenth thin film transistor T10 are connected to the second clock signal terminal CLK2, and a second electrode of the tenth thin film transistor T10 is connected to a gate of the sixth thin film transistor T6; a first electrode of the sixth thin film transistor T6 is connected to the second clock signal terminal CLK2, and a second electrode of the sixth thin film transistor T6 is connected to the pull-down node PD.
As shown in fig. 7, the second pull-down control sub-circuit 402 includes a seventh thin film transistor T7 and an eleventh thin film transistor T11; a gate electrode of the seventh thin film transistor T7 is connected to the first pull-up node PU1, a first electrode of the seventh thin film transistor T7 is connected to the pull-down node PD, and a second electrode of the seventh thin film transistor T7 is connected to the first power low voltage terminal VGL 1; a gate of the eleventh thin film transistor T11 is connected to the first pull-up node PU1, a first electrode of the eleventh thin film transistor T11 is connected to a second electrode of the tenth thin film transistor T10, and a second electrode of the eleventh thin film transistor T11 is connected to the first power low voltage terminal VGL 1.
Specifically, a first electrode of the eleventh thin film transistor T11, a second electrode of the tenth thin film transistor T10, and a gate of the sixth thin film transistor T6 are connected to the pull-down control node PD _ CN, and a potential of the pull-down control node PD _ CN controls whether the sixth thin film transistor T6 is turned on, and whether the sixth thin film transistor T6 is turned on controls a potential of the pull-down node PD.
As shown in fig. 7, the output terminals OUT include a first output terminal OUT1 and a second output terminal OUT2, the first output terminal OUT1 is connected to the corresponding gate signal line, the second output terminal OUT2 is connected to the input terminal of the next stage of shift register unit, and the first output terminal OUT1 and the second output terminal OUT2 output the same signal.
As shown in fig. 7, the output sub-circuit 20 includes a third thin film transistor T3, an eighth thin film transistor T8, and a storage capacitor C; a first pole of the storage capacitor C is connected to the second pull-up node PU2, and a second pole of the storage capacitor C is connected to the first output terminal OUT 1; a gate of the third thin film transistor T3 is connected to the second pull-up node PU2, a first electrode of the third thin film transistor T3 is connected to the first clock signal terminal CLK1, and a second electrode of the third thin film transistor T3 is connected to the first output terminal OUT 1; a gate of the eighth tft T8 is connected to the second pull-up node PU2, a first electrode of the eighth tft T8 is connected to the first clock signal terminal CLK1, and a second electrode of the eighth tft T8 is connected to the second output terminal OUT 2.
As shown in fig. 7, the pull-down sub-circuit 50 includes a fourth thin film transistor T4, a fifth thin film transistor T5, and a ninth thin film transistor T9. A gate of the fourth thin film transistor T4 is connected to the pull-down node PD, a first electrode of the fourth thin film transistor T4 is connected to the first output terminal OUT1, and a second electrode of the fourth thin film transistor T4 is connected to the second power low voltage terminal VGL 2; a gate electrode of the fifth thin film transistor T5 is connected to the pull-down node PD, a first electrode of the fifth thin film transistor T5 is connected to the first pull-up node PU1, and a second electrode of the fifth thin film transistor T5 is connected to the first power low voltage terminal VGL 1; a gate of the ninth thin film transistor T9 is connected to the pull-down node PD, a first electrode of the ninth thin film transistor T9 is connected to the second output terminal OUT2, and a second electrode of the ninth thin film transistor T9 is connected to the first power low voltage terminal VGL 1.
As shown in fig. 7, the second reset sub-circuit 70 includes a twelfth thin film transistor T12, a gate of the twelfth thin film transistor T12 is connected to the second reset terminal TRST, a first electrode of the twelfth thin film transistor T12 is connected to the first pull-up node PU1, and a second electrode of the twelfth thin film transistor T12 is connected to the first power low voltage terminal VGL 1.
In the circuit diagram shown in fig. 7, the second electrode of the first thin film transistor T1 and the double-gate thin film transistor T dgThe connection line between the first poles of the first transistors is a pull-up signal line L1, the potentials of all points on the pull-up signal line L1 are equal, and any point on the pull-up signal line L1 can be used as a first pull-up node PU 1; a connection line between the gate of the fifth thin film transistor T5 and the gate of the fourth thin film transistor T4 is a pull-down signal line L2, potentials of points on the pull-down signal line L2 are equal, and any point on the pull-down signal line L2 can be used as a pull-down node PD.
It should be noted that the circuit structure shown in fig. 7 is only an exemplary illustration, and the shift register unit shown in fig. 4 can be implemented as other circuit structures, for example, the GOA architecture of 15T1C, the GOA architecture of 17T1C, the GOA architecture of 18T1C, the GOA architecture of 19T1C, and the like, as long as the cut-off sub-circuit 20 is disposed between the Input sub-circuit 10 and the output sub-circuit 30, and the cut-off sub-circuit 20 is controlled by the Input terminal Input and the pull-down node PD, which is not listed herein.
Fig. 8 shows a timing chart of the shift register unit shown in fig. 7, and the operation principle of the shift register unit shown in fig. 7 will be described in detail below with reference to fig. 7 and 8 by taking the case where each thin film transistor is an N-type transistor. The driving process of the shift register unit shown in FIG. 7 mainly includes a first stage I, a second stage II and a third stage III.
As shown in fig. 7 and 8, in the first stage I, the Input terminal Input inputs a high level, the first thin film transistor T1 and the dual gate thin film transistor T dgWhen turned on, the Input terminal Input charges the storage capacitor C, and precharges the first pull-up node PU1 and the second pull-up node PU2, so that the voltages of the first pull-up node PU1 and the second pull-up node PU2 are at a high level. And the voltage of the second pull-up node PU2 is at a high level so that the third and eighth thin film transistors T3 and T8 are turned on, thereby outputting a low level input from the first clock signal terminal CLK1 from the first and second output terminals OUT1 and OUT 2.
In this process, the second clock signal terminal CLK2 is inputted with a high level, the tenth tft T10 is turned on, the pull-down control node PD _ CN is charged, and the first pull-up node PU1 is also at a high level, and at this time, the potential of the first pull-up node PU1 and the potential of the pull-down control node PD _ CN are in a competitive relationship.
In the present embodiment, by designing the width-to-length ratio of each thin film transistor, it can be ensured that the potential of the pull-down control node PD _ CN is pulled down and the first pull-up node PU1 can be pulled up to a desired potential in the above-mentioned competition relationship. For example, setting the width-to-length ratio of the channels of the seventh and eleventh thin film transistors T7 and T11 to be greater than the width-to-length ratio of the channel of the tenth thin film transistor T10 enables the seventh and eleventh thin film transistors T7 and T11 to be preferentially turned on in the above contention, thereby connecting the pull-down control node PD _ CN to the first power supply low voltage terminal VGL1 to pull down the potential of the pull-down control node PD _ CN. Since the potential of the pull-down control node PD _ CN is pulled down so that the sixth thin film transistor T6 is in an off state, the pull-down node PD is at a low level, and the fourth thin film transistor T4, the fifth thin film transistor T5, and the ninth thin film transistor T9 controlled by the pull-down node PD are in an off state in this process.
In this process, both the first Reset terminal Reset and the second Reset terminal TRST input a low level, so that the second thin film transistor T2 and the twelfth thin film transistor T12 are turned off.
As shown in fig. 7 and 8, in the second stage II, the Input terminal Input inputs a low level, the first thin film transistor T1 and the dual gate thin film transistor T dgAre all closed. The first pull-up node PU1 is still maintained at the same high level as the first stage I, and the second pull-up node PU2 is at the high level so that the third thin film transistor T3 and the eighth thin film transistor T8 are still turned on, thereby outputting the high level inputted from the first clock signal terminal CLK1 from the first output terminal OUT1 and the second output terminal OUT 2. In the process, the potential of the second pull-up node PU2 is further raised by the bootstrap action of the storage capacitor C.
In this process, the second clock signal terminal CLK2 inputs a low level, the tenth thin film transistor T10 is turned off, and at the same time, the first pull-up node PU1 is at a high level to turn on the seventh thin film transistor T7 and the eleventh thin film transistor T11, thereby respectively turning on the pull-down node PD and the pull-down control node PD _ CN with the power low voltage terminal VGL, so that the potentials of the pull-down node PD and the pull-down control node PD _ CN are maintained at a low level. Here, the pull-down control node PD _ CN is at a low level so that the sixth thin film transistor T6 is turned off, and the pull-down node PD is at a low level so that the fourth, fifth, and ninth thin film transistors T4, T5, and T9 are all in a turned-off state.
As shown in fig. 7 and 8, in the third stage III, the Input terminal Input inputs a low level, and the first thin film transistor T1 is turned off. In this process, the first Reset terminal Reset inputs a high level to turn on the second thin film transistor T2, thereby pulling the potential of the first pull-up node PU1 low, and further turning off the seventh thin film transistor T7 and the eleventh thin film transistor T11.
In this process, the tenth thin film transistor T10 is turned on by the high input of the second clock signal terminal CLK2, and the pull-down control node PD _ CN is at a high level to turn on the sixth thin film transistor T6, so that the voltage of the pull-down node PD rises to the high input of the second clock signal terminal CLK 2.
The pull-down node PD is at high level, so that the double-gate thin film transistor T dgAnd turning on, so that the first pull-up node PU1 and the second pull-up node PU2 are connected, and the fourth thin film transistor T4, the fifth thin film transistor T5, and the ninth thin film transistor T9 controlled by the pull-down node PD are all turned on, wherein the fifth thin film transistor T5 is mainly used for pulling down the potentials of the first pull-up node PU1 and the second pull-up node PU2, the fourth thin film transistor T4 is mainly used for pulling down the potential of the second output terminal OUT2, and the ninth thin film transistor T9 is mainly used for pulling down the potential of the first output terminal OUT 1.
In this process, the second pull-down node PU2 is at a low level, such that the third tft T3 and the eighth tft T8 are turned off, and at this time, the first output terminal OUT1 outputs a low level of the power low voltage terminal VGL2, and the second output terminal OUT2 outputs a low level of the power low voltage terminal VGL 1.
In this process, the second reset terminal TRST inputs a low level, so that the twelfth thin film transistor T12 is turned off.
It should be noted that, when the frame display screen is scanned, the second reset terminal TRST inputs a high level, and resets the shift register units of each stage again, so as to further reduce noise.
Based on the same inventive concept, the present embodiment provides a gate driving circuit, as shown in fig. 9, which includes a plurality of cascaded shift register units, where the shift register units are shift register units in the above embodiments.
It should be noted that the number and the cascade relationship of the shift register units in the gate driving circuit shown in fig. 9 are merely exemplary, and in practical applications, the number and the cascade relationship of the shift register units may be selected according to specific situations. For example, the plurality of cascaded shift register units include an (n-k) th stage shift register unit, an nth stage shift register unit, and an (n + k) th stage shift register unit, an input terminal of the nth stage shift register unit is connected to an output terminal of the (n-k) th stage, and an output terminal of the nth stage shift register unit is connected to an input terminal of the (n + k) th stage, where k is an integer greater than or equal to 1, and n is an integer greater than or equal to 2.
As shown in fig. 9, the start signal line STV is connected to the first polar shift register Unit1, and inputs a start signal to the first polar shift register Unit 1; a power supply low-voltage signal line VSS inputs a power supply low-voltage signal VGL to each pole shift register Unit; the first clock line CLK1 asserts a first clock signal for each of the plurality of shift register units, and the second clock line CLK2 asserts a second clock signal for each of the plurality of shift register units.
Note that the symbol "CLK 1" may indicate both the first clock input terminal and the first clock signal line, and similarly, the symbol "CLK 2" may indicate both the second clock input terminal and the second clock signal line.
In the gate driver circuit shown in fig. 9, the number of clock signal lines is merely an example, and when the cascade relationship is different, the number of necessary clock signal lines is different.
The gate driver circuit shown in fig. 9 may be applied to a DC (direct current) driver circuit or an AC (alternating current) driver circuit.
Based on the same inventive concept, the present embodiment provides an array substrate, as shown in fig. 10, the array substrate includes the gate driving circuit V in the above embodiment, and the beneficial effects of the gate driving circuit V can be achieved, which is not described herein again.
Specifically, the array substrate further includes a plurality of gate signal lines GL, a plurality of data lines DL crossing the gate signal lines, and a thin film transistor TD for controlling each of the sub-pixels P, a gate of the thin film transistor TD for controlling each of the sub-pixels P is connected to the gate signal line GL, a source of the thin film transistor TD for controlling each of the sub-pixels P is connected to the data line DL, and a drain of the thin film transistor TD for controlling each of the sub-pixels P is connected to the pixel electrode of the sub-pixel P.
When the gate signal line GL receives a driving signal (e.g. a high level output by the output terminal of the shift register unit in the above embodiment) output by the output terminal of the corresponding shift register unit, the thin film transistor connected to the gate signal line GL for controlling each subpixel P to turn on the TD is connected, so as to implement gate driving on the array substrate.
Based on the same inventive concept, this embodiment provides a display device, as shown in fig. 11, where the display device includes the array substrate in the above embodiment, and further includes a power supply and a driving chip, so that the beneficial effects of the array substrate can be achieved, and details are not repeated herein.
By applying the embodiment of the application, at least the following beneficial effects can be realized:
in the shift register unit, the gate driving circuit, the array substrate and the display device provided by this embodiment, the cut-off sub-circuit is added between the input sub-circuit and the output sub-circuit, and the cut-off sub-circuit can be selectively turned on or off, so that the first pull-up node and the second pull-up node can be connected to make the first pull-up node and the second pull-up node at the same potential, and the first pull-up node and the second pull-up node can be in a cut-off state, so that the potential of the second pull-up node is not affected by the pull-down sub-circuit connected to the first pull-up node.
Those of skill in the art will appreciate that the various operations, methods, steps in the processes, acts, or solutions discussed in this application can be interchanged, modified, combined, or eliminated. Further, other steps, measures, or schemes in various operations, methods, or flows that have been discussed in this application can be alternated, altered, rearranged, broken down, combined, or deleted. Further, steps, measures, schemes in the prior art having various operations, methods, procedures disclosed in the present application may also be alternated, modified, rearranged, decomposed, combined, or deleted.
In the description herein, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

Claims (14)

1. A shift register unit, comprising:
an input sub-circuit, respectively connected to an input terminal and a first pull-up node, configured to be turned on or off based on a signal received by the input terminal, so as to determine whether to pass a signal received by the receiving terminal to the first pull-up node;
a turn-off sub-circuit respectively connected to the input terminal, the first pull-up node, the second pull-up node, and the pull-down node, and configured to be turned on or off based on a received signal of the input terminal or based on a potential of the pull-down node, thereby controlling connection or disconnection of the first pull-up node and the second pull-up node;
an output sub-circuit connected to the second pull-up node, the first clock signal terminal, and the output terminal, respectively, and configured to control whether a signal received by the first clock signal terminal is output by the output terminal based on a potential of the second pull-up node;
the pull-down control sub-circuit comprises a first pull-down control sub-circuit and a second pull-down control sub-circuit, wherein the first pull-down control sub-circuit is respectively connected with a second clock signal terminal and the pull-down node and is configured to be switched on or switched off based on a signal received by the second clock signal terminal so as to transmit the signal received by the second clock signal terminal to the pull-down node or not; the second pull-down control sub-circuit is respectively connected with the first pull-up node, the pull-down node and a power supply low-voltage end, and is configured to control whether the pull-down node and the power supply low-voltage end are conducted or not based on the potential of the first pull-up node, so as to control whether the potential of the pull-down node is pulled down or not;
a pull-down sub-circuit, respectively connected to the first pull-up node, the pull-down node, the output terminal, and the power low-voltage terminal, and configured to control whether to conduct between the first pull-up node and the power low-voltage terminal and between the output terminal and the power low-voltage terminal based on a potential of the pull-down node, so as to control whether potentials of the first pull-up node and the output terminal are pulled down;
the first reset sub-circuit is respectively connected with the first reset terminal, the first pull-up node and the power low-voltage terminal, and is configured to control whether the first pull-up node and the power low-voltage terminal are conducted or not based on a signal received by the first reset terminal, so as to control whether the potential of the first pull-up node is pulled down or not, wherein the signal received by the first reset terminal is the same as a gate drive signal output by the next-stage shift register unit.
2. The shift register unit according to claim 1, further comprising:
the second reset sub-circuit is respectively connected with a second reset terminal, the first pull-up node and the power supply low-voltage terminal, and is configured to control whether the first pull-up node and the power supply low-voltage terminal are conducted or not based on a signal received by the second reset terminal;
the signal received by the second reset terminal is a total reset signal when the scanning of one frame of display picture is finished.
3. The shift register unit according to claim 1 or 2, wherein the off sub-circuit comprises a dual-gate thin film transistor, the dual-gate thin film transistor comprising a first gate, a second gate, a first electrode and a second electrode, the first gate being connected to the input terminal, the second gate being connected to the pull-down node, the first electrode being connected to the first pull-up node, the second electrode being connected to the second pull-up node.
4. The shift register cell of claim 3,
the input sub-circuit comprises a first thin film transistor, a grid electrode and a first electrode of the first thin film transistor are both connected with the input end, and a second electrode of the first thin film transistor is connected with the first pull-up node.
5. The shift register unit according to claim 3, wherein the first reset sub-circuit comprises a second thin film transistor, a gate of the second thin film transistor is connected to the first reset terminal, a first electrode of the second thin film transistor is connected to the first pull-up node, and a second electrode of the second thin film transistor is connected to the power supply low voltage terminal.
6. The shift register cell of claim 3, wherein the output sub-circuit comprises a third thin film transistor and a storage capacitor;
a gate of the third thin film transistor is connected with the second pull-up node, a first electrode of the third thin film transistor is connected with the first clock signal end, and a second electrode of the third thin film transistor is connected with the output end;
and the first pole of the storage capacitor is connected with the second pull-up node, and the second pole of the storage capacitor is connected with the second electrode of the third thin film transistor.
7. The shift register cell of claim 6, wherein the pull-down sub-circuit comprises a fourth thin film transistor and a fifth thin film transistor;
a grid electrode of the fourth thin film transistor is connected with the pull-down node, a first electrode of the fourth thin film transistor is connected with the output end, and a second electrode of the fourth thin film transistor is connected with the low-voltage end of the power supply;
the grid electrode of the fifth thin film transistor is connected with the pull-down node, the first electrode of the fifth thin film transistor is connected with the first pull-up node, and the second electrode of the fifth thin film transistor is connected with the low-voltage end of the power supply.
8. The shift register cell of claim 7,
the first pull-down control sub-circuit comprises a sixth thin film transistor, a grid electrode and a first electrode of the sixth thin film transistor are both connected with the second clock signal end, and a second electrode of the sixth thin film transistor is connected with the pull-down node;
the second pull-down control sub-circuit comprises a seventh thin film transistor, the grid electrode of the seventh thin film transistor is connected with the first pull-up node, the first electrode of the seventh thin film transistor is connected with the pull-down node, and the second electrode of the seventh thin film transistor is connected with the low-voltage end of the power supply. .
9. The shift register unit according to claim 8, wherein the output terminal comprises a first output terminal and a second output terminal, the first output terminal is connected to the gate signal line, the second output terminal is connected to the input terminal of the next shift register unit, and the second electrode of the third thin film transistor is connected to the first output terminal;
the output sub-circuit further comprises an eighth thin film transistor, a grid electrode of the eighth thin film transistor is connected with the second pull-up node, a first electrode of the eighth thin film transistor is connected with the first clock signal end, and a second electrode of the eighth thin film transistor is connected with the second output end;
the pull-down sub-circuit further comprises a ninth thin film transistor, a grid electrode of the ninth thin film transistor is connected with the pull-down node, a first electrode of the ninth thin film transistor is connected with the second pull-up node, and a second electrode of the ninth thin film transistor is connected with the low-voltage end of the power supply.
10. The shift register cell of claim 9,
the first pull-down control sub-circuit further comprises a tenth thin film transistor, a gate and a first electrode of the tenth thin film transistor are both connected with the second clock signal end, and a second electrode of the tenth thin film transistor is connected with a gate of the sixth thin film transistor;
the second pull-down control sub-circuit further comprises an eleventh thin film transistor, a gate of the eleventh thin film transistor is connected with the first pull-up node, a first electrode of the eleventh thin film transistor is connected with a second electrode of the tenth thin film transistor, and a second electrode of the eleventh thin film transistor is connected with the low-voltage end of the power supply.
11. The shift register unit according to claim 2, wherein the second reset sub-circuit comprises a twelfth thin film transistor, a gate of the twelfth thin film transistor is connected to the second reset terminal, a first electrode of the twelfth thin film transistor is connected to the first pull-up node, and a second electrode of the twelfth thin film transistor is connected to the power supply low voltage terminal.
12. A gate driving circuit, comprising a plurality of cascaded shift register units, wherein the shift register units are the shift register units according to any one of claims 1 to 11;
the plurality of cascaded shift register units comprise an (n-k) th stage shift register unit, an nth stage shift register unit and an (n + k) th stage shift register unit, wherein the input end of the nth stage shift register unit is connected with the output end of the (n-k) th stage, the output end of the nth stage shift register unit is connected with the input end of the (n + k) th stage, k is an integer greater than or equal to 1, and n is an integer greater than or equal to 2.
13. An array substrate comprising the gate driver circuit of claim 12.
14. A display device comprising a power supply and a driver chip, further comprising the array substrate according to claim 13.
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CN111933084A (en) * 2020-09-02 2020-11-13 京东方科技集团股份有限公司 Gate drive circuit, array substrate, display device and drive method
CN112382249A (en) * 2020-11-13 2021-02-19 昆山龙腾光电股份有限公司 Gate drive unit, gate drive circuit and display device
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