CN107564450B - Gate drive circuit and display device - Google Patents
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Abstract
The invention discloses a gate driving circuit, which comprises a plurality of stages of gate driving units controlled by a first mode signal and a second mode signal, wherein each stage of gate driving unit comprises: the input module is used for controlling the voltage of the first node according to the front-stage grid transmission signal and the rear-stage grid transmission signal; the control module is used for generating a first control signal when the first mode signal is effective and generating a second control signal when the second mode signal is effective, and the first mode signal and the second mode signal are alternately effective; the pull-down module is used for pulling down the voltage of the first node when the first control signal or the second control signal is effective; the reset module is used for resetting the second control signal to a low level when the first control signal is effective and resetting the first control signal to the low level when the second control signal is effective; and the output module is used for generating the current-stage grid driving signal according to the first control signal, the second control signal and the voltage of the first node.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a gate driving circuit and a display device.
Background
A display device generally includes a display panel, a gate driving circuit, and a source driving circuit. The display panel includes a pixel array formed of a plurality of pixel units, each of which includes a thin film transistor. In the pixel array, the grid electrodes of the thin film transistors in the pixel units in the same row are connected with a grid electrode driving circuit through the same scanning line, and the grid electrode driving circuit selects the pixel units in each row in the pixel array line by line through a plurality of scanning lines; the source electrodes or the drain electrodes of the thin film transistors in the pixel units in the same row are connected with a source electrode driving circuit through the same data line, and the source electrode driving circuit applies gray scale voltage to the pixel units in each row through a plurality of data lines, so that the display panel presents images.
With the development of display devices, the application of integrated Gate Driver In Array (GIA) is becoming more and more extensive, and it integrates a Gate Driver circuit and a display panel on the same substrate, and this technique not only can reduce thousands of wires, make the display device more symmetrical and compact, but also can reduce cost and improve the resolution and the bending degree of the display panel. However, in the GIA technology, when threshold voltage shift (Vth shift) occurs in a Thin Film Transistor (TFT) in a stabilization unit, power consumption of the gate driving circuit is greatly increased, which results in waste of energy.
In the prior art, the lifetime of the thin film transistor in the stabilization unit is prolonged by adjusting the process to improve the degree of threshold voltage drift, controlling the stabilization unit by an alternating current signal, and performing time-sharing control on two groups of stabilization units. However, these methods are difficult to implement and have not been ideal, for example, the threshold voltage drift cannot be completely solved by the manufacturing process; although the threshold voltage drift can be reduced by the alternating current signal, the threshold voltage drift is still serious; the threshold voltage drift can only be reduced but not suppressed.
Disclosure of Invention
The present invention provides a gate driving circuit and a display device to solve the above problems in the prior art, and aims to reduce power consumption of the gate driving circuit by improving the threshold voltage drift of the thin film transistor in the gate driving circuit stabilizing unit.
According to an aspect of the present invention, there is provided a gate driving circuit including a plurality of stages of gate driving units controlled by a first mode signal and a second mode signal, each of the stages of gate driving units including: the input module is used for controlling the voltage of the first node according to the front-stage grid transmission signal and the rear-stage grid transmission signal; the control module is used for generating a first control signal when the first mode signal is effective and generating a second control signal when the second mode signal is effective, and the first mode signal and the second mode signal are alternately effective; a pull-down module for pulling down a voltage of the first node when the first control signal or the second control signal is active; the reset module is used for resetting the second control signal to a low level when the first control signal is effective and resetting the first control signal to a low level when the second control signal is effective; and the output module is used for generating the current-stage gate driving signal according to the first control signal, the second control signal and the voltage of the first node.
Preferably, the control module comprises: the first control module is used for generating the first control signal according to the first node voltage; and the second control module is used for generating the second control signal according to the first node voltage.
Preferably, the pull-down module includes: the first pull-down module is used for pulling down the first node voltage according to the first control signal; and the second pull-down module is used for pulling down the first node voltage according to the second control signal.
Preferably, the reset module includes: the first reset module is used for resetting the second control signal to a low level according to the first control signal; and the second reset module is used for resetting the first control signal to a low level according to the second control signal.
Preferably, the input module includes a first transistor and a third transistor, a first path end and a control end of the first transistor receive the preceding stage transmission signal, a control end of the third transistor receives the subsequent stage transmission signal, a first path end of the third transistor receives a supply voltage, and second path ends of the first transistor and the third transistor are connected to the first node to generate the first node voltage.
Preferably, the first control module includes fifth, sixth, tenth and eleventh transistors, a control terminal and a first path terminal of the fifth transistor and a first path terminal of the sixth transistor receive the first mode signal, control terminals of the tenth and eleventh transistors receive the first node voltage, a first path terminal of the tenth and eleventh transistors receives the supply voltage, a second path terminal of the fifth and eleventh transistors is connected to a control terminal of the sixth transistor, and a second path terminal of the sixth and tenth transistors is connected to the second node and generates the first control signal; the second control module comprises a twelfth transistor, a thirteenth transistor, a seventeenth transistor and an eighteenth transistor, wherein a control end and a first path end of the twelfth transistor and the thirteenth transistor receive the second mode signal, control ends of the seventeenth transistor and the eighteenth transistor receive the first node voltage, the first path ends of the seventeenth transistor and the eighteenth transistor receive the power supply voltage, a second path end of the twelfth transistor and the eighteenth transistor are connected with a control end of the thirteenth transistor, and a second path end of the thirteenth transistor and the seventeenth transistor is connected with the third node and generates the second control signal.
Preferably, the first pull-down module includes an eighth transistor, a control terminal of the eighth transistor receives the first control signal, a first path terminal of the eighth transistor receives the supply voltage, and a second path terminal of the eighth transistor is connected to the first node to control the first node voltage; the second pull-down module comprises a fifteenth transistor, a control end of the fifteenth transistor receives a second control signal, a first path end of the fifteenth transistor receives the power supply voltage, and a second path end of the fifteenth transistor is connected with the first node to control the voltage of the first node.
Preferably, the first reset module includes a ninth transistor, a control terminal of the ninth transistor receives the first control signal, a first path terminal of the ninth transistor receives the supply voltage, and a second path terminal of the ninth transistor is connected to the third node to control the second control signal; the second reset module comprises a sixteenth transistor, a control end of the sixteenth transistor receives a second control signal, a first path end of the sixteenth transistor receives the power supply voltage, and a second path end of the sixteenth transistor is connected with the second node to control the first control signal.
Preferably, the output module includes a second transistor, a fourth transistor, a fourteenth transistor, a seventh transistor, and a first capacitor, the second transistor is connected to a control terminal of the fourth transistor and a first terminal of the first capacitor is connected to the first node, the second transistor receives a clock signal from a first path of the fourth transistor, the control terminal of the seventh transistor receives the first control signal, the control terminal of the fourteenth transistor receives the second control signal, first paths of the seventh transistor and the fourteenth transistor receive the supply voltage, a second path of the fourth transistor outputs the gate transfer signal, and second paths of the seventh transistor, the fourteenth transistor, and the second transistor are connected to a second terminal of the first capacitor to output the gate drive signal.
According to another aspect of the present invention, there is provided a display device comprising at least one gate driving circuit as described in any one of the above.
The gate driving circuit has the advantages that the gate driving circuit which enables the thin film transistors of the stabilizing unit to alternately recover the switching characteristics through the mode signal is designed, the threshold voltage of the corresponding thin film transistors is stabilized, and therefore the power consumption of the gate driving circuit is reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a gate driving circuit in a display device according to an embodiment of the invention.
Fig. 3 shows a schematic block diagram of an ith-stage gate driving unit in the display device of the embodiment of the present invention.
Fig. 4 is a schematic structural diagram of an ith-stage gate driving unit in the display device according to the embodiment of the invention.
Fig. 5 is a timing diagram illustrating an ith gate driving unit in the display device according to the embodiment of the invention in the first operation mode.
Fig. 6 is a timing diagram illustrating an ith gate driving unit in the display device according to the embodiment of the invention in the second operation mode.
Detailed Description
In order to make the objects and aspects of the present invention clearer and more convenient to implement, the present invention will be described in further detail with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.
Numerous specific details of the invention are set forth in the following description in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Fig. 1 shows a schematic structural diagram of a display device according to an embodiment of the present invention, which includes a timing control circuit 1100, a source driving circuit 1200, a gate driving circuit 1300, and a display panel 1400, wherein the gate driving circuit 1300 and the display panel 1400 may be integrated on the same substrate to form an integrated gate driving structure.
The timing control circuit 1100 is used for providing control signals such as a plurality of clock signals and a Start Vertical (STV) signal to the source driver circuit 1200 and the gate driver circuit 1300, wherein the Start signal may be an on signal for one frame.
In the following description of the embodiments of the present invention, i is a natural number of 1 or more and n or less unless otherwise specified.
Fig. 2 is a schematic structural diagram of a gate driving circuit in a display device according to an embodiment of the present invention, the gate driving circuit including a plurality of stages of gate driving units GIA [1] to GIA [ n ]. Wherein, each stage of gate drive unit respectively outputs gate drive signals G [1] to G [ n ] and transfer signals Z [1] to Z [ n ]. For each stage of gate driving unit GIA [ i ], the transfer signal Z [ i ] of the stage is used for replacing the gate driving signal G [ i ] of the stage to realize signal transfer among the gate driving units of each stage, and the gate driving signal G [ i ] of the stage is mainly used for driving transistors in pixel units, so that the attenuation of the gate driving signal G [ i ] of the stage is avoided, and the pixel units of the row can be normally driven. Therefore, in a normal case, the transfer signal Z [ i ] of each stage is equal to the gate driving signal G [ i ] output by the gate driving unit GIA [ i ] of the stage.
Each stage of gate driving unit GIA [ i ] has, for example, a preceding stage input terminal, a succeeding stage input terminal, a clock terminal, a driving terminal, a transfer terminal, a first mode terminal, a second mode terminal, and a power supply terminal.
The front stage input end of each stage of gate driving unit receives a front stage gate transmission signal Z [ i-2], the rear stage input end receives a rear stage gate transmission signal Z [ i +2], the clock end receives a clock signal clk corresponding to the present stage of gate driving unit, the first mode end receives a first mode signal D1, the second mode end receives a second mode signal D2, the power supply end receives a power supply voltage VGL, the driving end outputs a present stage gate driving signal G [ i ], and the transmission end outputs a present stage gate transmission signal Z [ i ].
The gate driving circuit includes four clock signals, i.e., a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, and a fourth clock signal CLK 4.
In the gate driving circuit of the present invention, a clock terminal CLK of a first stage gate driving unit GIA [1] receives a first clock signal CLK1, a preceding stage input terminal receives a preceding stage gate transfer signal Z [ i-2] which is a first preceding stage start signal STV1 provided by a timing control circuit directly or via a source driving circuit, a driving terminal outputs a first stage gate driving signal G [1], a transfer terminal outputs a first stage gate transfer signal Z [1], a subsequent stage input terminal receives a subsequent stage gate transfer signal Z [ i +2] as a third stage gate transfer signal Z [3] of a third stage gate driving unit circuit GIA [3 ];
the clock terminal CLK of the second stage gate driving unit GIA [2] receives the second clock signal CLK2, the front stage input terminal receives the front stage gate transfer signal Z [ i-2] which is the second front stage start signal STV2 provided by the timing control circuit directly or via the source driving circuit, the driving terminal outputs the second stage gate driving signal G [2], the transfer terminal outputs the second stage gate transfer signal Z [2], the rear stage input terminal receives the rear stage gate transfer signal Z [ i +2] as the fourth stage gate transfer signal Z [4] of the fourth stage gate driving unit circuit GIA [4 ];
the clock terminal CLK of the third stage gate driving unit GIA [3] receives the third clock signal CLK3, the front stage input terminal receives the front stage gate transfer signal Z [ i-2] and outputs the first stage gate transfer signal Z [1] to the transfer terminal of the first stage gate driving unit GIA [1], the rear stage input terminal receives the rear stage gate transfer signal Z [ i +2] and outputs the fifth stage gate transfer signal Z [5] of the fifth stage gate driving unit circuit GIA [5], the driving terminal outputs the third stage gate driving signal G [3], and the transfer terminal outputs the third stage gate transfer signal Z [3 ].
The clock terminal CLK of the fourth stage gate driving unit GIA [4] receives the fourth clock signal CLK4, the front stage input terminal receives the front stage gate transfer signal Z [ i-2] and outputs the second stage gate transfer signal Z [2] to the transfer terminal of the second stage gate driving unit GIA [2], the rear stage input terminal receives the rear stage gate transfer signal Z [ i +2] and outputs the sixth stage gate transfer signal Z [6] of the sixth stage gate driving unit circuit GIA [6], the driving terminal outputs the fourth stage gate driving signal G [4], and the transfer terminal outputs the fourth stage gate transfer signal Z [4 ].
In the gate driving circuit, the first to fourth gate driving units form a period, and the subsequent gate driving unit cyclically repeats the connection relationship of the first to fourth stage unit circuits, which is not described herein again. Wherein the post transfer signal Z [ i +2] received at the post input terminal of the (n-1) th gate driving unit GIA [ n-1] is the first post start signal STV3 provided directly by the timing control circuit or provided through the source driving circuit, and wherein the post transfer signal Z [ i +2] received at the post input terminal of the (n) th gate driving unit GIA [ n ] is the second post start signal STV4 provided directly by the timing control circuit or provided through the source driving circuit.
The power supply voltage VGL received by the power supply terminal of each stage of gate driving unit is always a low level signal, the first mode terminal receives the first mode signal D1, and the second mode terminal receives the second mode signal D2;
the clock end of each stage of gate driving unit respectively receives at least one of a plurality of clock signals provided by the timing control circuit directly or through the source driving circuit.
Fig. 3 is a schematic block diagram illustrating an ith stage gate driving unit in a display device according to an embodiment of the present invention, where the gate driving unit GIA [ i ] includes an input module 1310, a control module 1320, a pull-down module 1330, a reset module 1340, and an output module 1350, where the control module 1320 includes a first control module 1321 and a second control module 1322, the pull-down module 1330 includes a first pull-down module 1331 and a second pull-down module 1332, and the reset module 1340 includes a first reset module 1341 and a second reset module 1342. The connection relationship and signal relationship of each block in the ith-stage gate driving unit GIA [ i ] will be described in detail below.
The input module 1310 is configured to provide a voltage of a first node Q according to a previous gate transfer signal Z [ i-2] received by a previous input terminal of the gate driving unit, a next gate transfer signal Z [ i +2] received by a next input terminal of the gate driving unit, and a supply voltage VGL, where an output terminal of the input module 1310 is connected to the first node Q.
An input terminal of the first control module 1321 receives the first mode signal D1, and an output terminal of the first control module 1321 is respectively connected to input terminals of the first pull-down module 1331, the first reset module 1341, and the output module 1350, wherein the first control module 1321 generates the first control signal ctrl1 at the output terminal according to the first mode signal D1 and the supply voltage VGL.
An input terminal of the second control module 1322 receives the second mode signal D2, and an output terminal of the second control module 1322 is connected to input terminals of the second pull-down module 1332, the second reset module 1342 and the output module 1350, respectively, wherein the second control module 1322 generates the second control signal ctrl2 at the output terminal according to the second mode signal D2 and the supply voltage VGL.
An input and an output of the first pull-down module 1331 are connected to the first node Q, and the first pull-down module 1331 controls a voltage of the first node Q according to the first control signal ctrl1 and the supply voltage VGL.
An input and an output of the second pull-down module 1332 are connected to the first node Q, and the second pull-down module 1332 controls a voltage of the first node Q according to the second control signal ctrl2 and the supply voltage VGL.
The output terminal of the first reset module 1341 is connected to the third node QB1, and resets the second control signal ctrl2 according to the first control signal ctrl1 and the supply voltage VGL, so that the second control signal ctrl2 becomes a low level.
The output terminal of the second reset module 1342 is coupled to the second node QB, and resets the first control signal ctrl1 according to the second control signal ctrl2 and the power supply voltage VGL, so that the first control signal ctrl1 becomes a low level.
The output module 1350 generates the gate transfer signal Z [ i ] and the gate driving signal G [ i ] according to the first control signal ctrl1, the second control signal ctrl2, the clock signal clk, the voltage of the first node Q, and the power supply voltage VGL, wherein the generated gate driving signal G [ i ] is the first gate driving signal gout1 when the first mode signal D1 is at a high level and the second mode signal D2 is at a low level; when the first mode signal D1 is low and the second mode signal D2 is high, the generated gate driving signal G [ i ] is the second gate driving signal gout 2.
Fig. 4 is a schematic structural diagram of an ith-stage gate driving unit in the display device according to the embodiment of the invention. It should be noted that the transistors mentioned in this embodiment are all N-type thin film transistors, and the first via terminal and the second via terminal of each transistor may be interchanged (i.e., the drain and the source may be interchanged). But implementations of the invention are not limited thereto.
The input module 1310 includes a transistor T1 and a transistor T3. The source and the gate (i.e., the control terminal) of the transistor T1 receive the previous stage gate transfer signal Z [ i-2], the gate of the transistor T3 receives the next stage gate transfer signal Z [ i +2], the source of the transistor T3 receives the supply voltage VGL, and the drains of the transistors T1 and T3 are connected to provide the voltage of the first node Q.
The first control module 1321 includes transistors T5, T6, T10, and T11. The gate and source of the transistor T5 and the source of the transistor T6 receive the first mode signal D1, the gates of the transistors T10 and T11 are connected to the first node Q, receive the voltage of the first node Q, the sources of the transistors T10 and T11 receive the supply voltage VGL, the drains of the transistors T5 and T11 are connected to the gate of the transistor T6, and the drains of the transistors T6 and T10 are connected to the second node QB and generate the first control signal ctrl 1.
The first pull-down module 1331 includes a transistor T8. The source of the transistor T8 receives the supply voltage VGL, the gate of the transistor T8 receives the first control signal ctrl1, and the drain of the transistor T8 is connected to the first node Q, and controls the voltage of the first node Q according to the first control signal ctrl1 and the supply voltage VGL.
The first reset module 1341 includes a transistor T9. A gate of the transistor T9 receives the first control signal ctrl1, a source of the transistor T9 receives the supply voltage VGL, a drain of the transistor T9 is connected to the third node QB1, and controls the second control signal ctrl 2;
the second control module 1322 includes transistors T12, T13, T17, and T18. The gate and source of the transistor T12 and the source of the transistor T13 receive the second mode signal D2, the gates of the transistors T17 and T18 are connected to the first node Q, receive the voltage of the first node Q, the sources of the transistors T17 and T18 receive the supply voltage VGL, the drains of the transistors T12 and T18 are connected to the gate of the transistor T13, and the drains of the transistors T13 and T17 are connected to the third node QB1 and generate the second control signal ctrl 2.
The second pull-down module 1332 includes a transistor T15. The source of the transistor T15 receives the supply voltage VGL, the gate of the transistor T15 receives the second control signal ctrl2, and the drain of the transistor T15 is connected to the first node Q, and controls the voltage of the first node Q according to the second control signal ctrl2 and the supply voltage VGL.
The second reset module 1342 includes a transistor T16. A gate of the transistor T16 receives the second control signal ctrl2, a source of the transistor T16 receives the supply voltage VGL, and a drain of the transistor T16 is connected to the second node QB, controlling the first control signal ctrl 1;
the output module 1350 includes transistors T2, T4, T14, T7, and a capacitor C1. Gates of the transistors T2 and T4 and a first terminal of the capacitor C1 are connected to the first node Q to receive the first node voltage, sources of the transistors T2 and T4 receive the clock signal clk, a gate of the transistor T7 receives the first control signal ctrl1, a gate of the transistor T14 receives the second control signal ctrl2, sources of the transistors T7 and T14 receive the supply voltage VGL, a drain of the transistor T4 outputs the gate transfer signal Z [ i ] of the stage, and a second terminal of the capacitor C1 is connected to drains of the transistors T2, T7 and T14 to output the gate drive signal G [ i ] of the stage.
In the gate driving circuit 1300 of the present invention, each stage of the gate driving unit GIA [ i ] has two modes:
when the display device is operated in the odd cycle, the first mode signal D1 is asserted, i.e. the first mode signal D1 is high, the first control signal ctrl1 generated by the first control module 1321 at the second node QB is high, at which time the transistor T9 is turned on, the second control signal ctrl2 generated at the third node QB1 is reset to low, the transistors T14, T15, 16 are turned off, and since the supply voltage VGL is low, the transistors T14, T15, 16 are biased negatively, so that the threshold voltage shift that has occurred is shifted in the opposite direction.
When the display device is operated in an even cycle, the second mode signal D2 is asserted, i.e. the second mode signal D2 is high, the second control module 1322 generates the second control signal ctrl2 at the third node QB1, which is high, at which time the transistor T16 is turned on, which resets the first control signal ctrl1 generated at the second node QB to low, turns off the transistors T7, T8, and T9, and since the supply voltage VGL is low, the transistors T7, T8, and T9 are negatively biased, so that the threshold voltage shift that has occurred is shifted in the opposite direction.
Therefore, the first mode signal D1 and the second mode signal D2 are alternately asserted during the odd cycle and the even cycle, so that the switching characteristics of the tfts T7, T8, T14 and T15, which play a role in stabilizing the gate driving circuit of the present invention, are restored, thereby reducing the power consumption of the gate driving circuit.
The operation of each gate driving unit in the second mode will be described with reference to the drawings.
Fig. 5 is a timing diagram illustrating an ith gate driving unit in the display device according to the embodiment of the invention in the first mode.
When the first mode signal D1 is at a high level and the second mode signal D2 is at a low level, each stage of the gate driving units in the gate driving circuit 1300 is in the first mode as shown in fig. 5. When the first stage gate driving unit GIA [ i ] is in the first phase P1, the previous stage gate transfer signal Z [ i-2] is connected to the first previous stage start signal STV1, and STV1 is high, and the clock signal CLK corresponding to the present stage gate driving unit (i.e. the clock signal CLK1 in FIG. 5) is low. Therefore, as shown in fig. 4 and 5, the transistor T1 is turned on at this time so that the voltage of the first node Q is the high level VGH. Accordingly, the transistors T2, T4, T10, T11, T17 and T18 are turned on, so that the second node QB and the third node QB1 are at a low level, resulting in that the transistors T7, T8, T9, T14, T15 and T16 are turned off, and thus the output voltages of the gate driving signal G [ i ] and the transfer signal Z [ i ] are at a low level.
In the second phase P2, the CLK1 is at a high level, the gate driving signal G [ i ] and the transfer signal Z [ i ] are at a high level, the capacitor C1 generates a bootstrap effect, and the potential of the first node Q becomes VGH 2 times, so that the transistors T2 and T4 are turned on more fully.
In the third stage P3, the CLK1 changes from high to low, and the potential of the first node Q changes to VGH, so that the gate driving signal G [ i ] and the transfer signal Z [ i ] are output at low level.
In the fourth phase P4, the post-stage gate transfer signal Z [ i +2] is at a high level VGH, turning on the transistor T3, and the voltage at the first node Q becomes a low level. The transistors T2, T4, T10, T11, T17, T18 are turned off. Meanwhile, since the first control signal D1 is at a high level, the transistors T5 and T6 are turned on, so that the voltage of the second node QB is at a high level, and the transistors T7, T8 and T9 are turned on, so that the voltages of the first node Q and the third node QB1 are at a low level; the grid driving signal G [ i ] and the transmission signal Z [ i ] are output to low level; since the second control signal D2 is low, the transistors T12, T13 are off. Since the voltage of the third node QB1 is low, the transistors T14, T15 and T16 are turned off and negatively biased, so that the switching characteristics of the transistors T14, T15 and T16 are restored.
Fig. 6 is a timing diagram illustrating the first stage of gate driving unit in the display device according to the embodiment of the invention in the second operation mode.
When the first mode signal D1 is at a low level and the second mode signal D2 is at a high level, as shown in fig. 6, each stage of the gate driving unit in the gate driving circuit 1300 is in the second mode. When the first stage gate driving unit GIA [ i ] is in the first phase P1, the previous stage gate transfer signal Z [ i-2] receives the first previous stage start signal STV1 and STV1 is high, and the clock signal CLK corresponding to the present stage gate driving unit (i.e., the clock signal CLK1 in FIG. 6) is low. Therefore, as shown in fig. 4 and 6, the transistor T1 is turned on at this time so that the voltage of the first node Q is the high level VGH. Accordingly, the transistors T2, T4, T10, T11, T17 and T18 are turned on, so that the second node QB and the third node QB1 are at a low level, resulting in that the transistors T7, T8, T9, T14, T15 and T16 are turned off, and thus the output voltages of the gate driving signal G [ i ] and the transfer signal Z [ i ] are at a low level.
In the second phase P2, the CLK1 is at a high level, the gate driving signal G [ i ] and the transfer signal Z [ i ] are at a high level, the capacitor C1 generates a bootstrap effect, and the potential of the first node Q becomes VGH 2 times, so that the transistors T2 and T4 are turned on more fully.
In the third stage P3, the CLK1 changes from high to low, and the potential of the first node Q changes to VGH, so that the gate driving signal G [ i ] and the transfer signal Z [ i ] are output at low level.
In the fourth phase P4, the post-stage gate transfer signal Z [ i +2] is at a high level VGH, turning on the transistor T3, and the voltage at the first node Q becomes a low level. The transistors T2, T4, T10, T11, T17, T18 are turned off. Meanwhile, since the first control signal D2 is at a high level, the transistors T12 and T13 are turned on, so that the voltage of the third node QB1 is at a high level, and the transistors T14, T15 and T16 are turned on, so that the voltages of the first node Q and the second node QB are at a low level; the grid driving signal G [ i ] and the transmission signal Z [ i ] are output to low level; since the second control signal D1 is low, the transistors T5, T6 are off. Since the voltage at the second node QB is low, the transistors T7, T8, and T9 are turned off and negatively biased, so that the switching characteristics of the transistors are restored.
Therefore, the first mode signal D1 and the second mode signal D2 are alternately asserted during the odd cycle and the even cycle, so that the switching characteristics of the tfts T7, T8, T14 and T15, which play a role in stabilizing the gate driving circuit of the present invention, are restored, thereby reducing the power consumption of the gate driving circuit.
The gate driving circuit of the invention recovers the switching characteristics of the TFTs T7, T8, T14 and T15 which play a stabilizing role under the alternate operation of two modes, thereby reducing the power consumption of the gate driving circuit.
According to another aspect of the present invention, there is also provided a display device including at least one gate driving circuit of any one of the above described gate driving circuits, instead of the gate driving circuit of the related art in which the thin film transistor of the stabilization unit undergoes threshold voltage drift to cause an increase in power consumption.
The gate driving circuit has the advantages that the gate driving circuit which enables the thin film transistors of the stabilizing unit to alternately recover the switching characteristics through the mode signal is designed, the threshold voltage of the corresponding thin film transistors is stabilized, and therefore the power consumption of the gate driving circuit is reduced.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.
Claims (8)
1. A gate driving circuit comprising a plurality of stages of gate driving units controlled by a first mode signal and a second mode signal, each stage of the gate driving units comprising:
the input module is used for controlling the voltage of the first node according to the front-stage grid transmission signal and the rear-stage grid transmission signal;
a control module for generating a first control signal at a second node when the first mode signal is active and a second control signal at a third node when the second mode signal is active, the first mode signal and the second mode signal being alternately active;
a pull-down module, configured to pull down a voltage of the first node when the first control signal or the second control signal is valid, where the pull-down module includes an eighth transistor and a fifteenth transistor, a control end of the eighth transistor is connected to the second node to receive the first control signal, a first path end of the eighth transistor receives a supply voltage, and a second path end of the eighth transistor is connected to the first node to pull down the voltage of the first node; a control terminal of the fifteenth transistor is connected to the third node to receive the second control signal, a first path terminal of the fifteenth transistor receives the supply voltage, and a second path terminal of the fifteenth transistor is connected to the first node to pull down a voltage of the first node;
the reset module is used for resetting the second control signal to a low level when the first control signal is effective and resetting the first control signal to a low level when the second control signal is effective; and
an output module for generating a present-stage gate driving signal and a present-stage gate transfer signal according to the first control signal, the second control signal and the voltage of the first node,
wherein the eighth transistor is turned off and negatively biased in a case where the first control signal is reset to a low level, and the fifteenth transistor is turned off and negatively biased in a case where the second control signal is reset to a low level.
2. A gate drive circuit as claimed in claim 1, wherein the control module comprises:
the first control module is used for generating the first control signal according to the first mode signal, the voltage of a first node and a power supply voltage;
and the second control module is used for generating the second control signal according to the second mode signal, the voltage of the first node and the power supply voltage.
3. The gate driving circuit of claim 1, wherein the reset module comprises:
the first reset module is used for resetting the second control signal to a low level according to the first control signal and the power supply voltage;
and the second reset module is used for resetting the first control signal to a low level according to the second control signal and the power supply voltage.
4. The gate driving circuit according to claim 1, wherein the input module includes a first transistor and a third transistor, a first path terminal and a control terminal of the first transistor receive the previous stage gate transfer signal, a control terminal of the third transistor receives the next stage gate transfer signal, a first path terminal of the third transistor receives the supply voltage, and a second path terminal of the first and third transistors is connected to the first node to generate the voltage of the first node.
5. A gate driving circuit according to claim 2, wherein the first control module comprises fifth, sixth, tenth and eleventh transistors, a control terminal and a first pass terminal of the fifth transistor and a first pass terminal of the sixth transistor receive the first mode signal, control terminals of the tenth and eleventh transistors receive the voltage of the first node, a first pass terminal of the tenth and eleventh transistors receive the supply voltage, a second pass terminal of the fifth and eleventh transistors is connected to the control terminal of the sixth transistor, and a second pass terminal of the sixth and tenth transistors is connected to the second node and generates the first control signal;
the second control module comprises a twelfth transistor, a thirteenth transistor, a seventeenth transistor and an eighteenth transistor, wherein the control end and the first pass end of the twelfth transistor and the first pass end of the thirteenth transistor receive the second mode signal, the control ends of the seventeenth transistor and the eighteenth transistor receive the voltage of the first node, the first pass ends of the seventeenth transistor and the eighteenth transistor receive the power supply voltage, the second pass ends of the twelfth transistor and the eighteenth transistor are connected with the control end of the thirteenth transistor, and the second pass ends of the thirteenth transistor and the seventeenth transistor are connected with the third node and generate the second control signal.
6. A gate driving circuit according to claim 3, wherein the first reset module comprises a ninth transistor, a control terminal of the ninth transistor receives the first control signal, a first path terminal of the ninth transistor receives the supply voltage, and a second path terminal of the ninth transistor is connected to the third node to control the second control signal;
the second reset module comprises a sixteenth transistor, a control end of the sixteenth transistor receives a second control signal, a first path end of the sixteenth transistor receives the power supply voltage, and a second path end of the sixteenth transistor is connected with the second node to control the first control signal.
7. The gate driving circuit according to claim 1, wherein the output module includes second, fourth, seventh, and fourteenth transistors and a first capacitor, control terminals of the second and fourth transistors and a first terminal of the first capacitor are connected to the first node, first paths of the second and fourth transistors receive a clock signal, a control terminal of the seventh transistor receives the first control signal, a control terminal of the fourteenth transistor receives the second control signal, first paths of the seventh and fourteenth transistors receive the supply voltage, a second path of the fourth transistor outputs the present-stage gate transfer signal, and second paths of the second, seventh, and fourteenth transistors are connected to a second terminal of the first capacitor to output the present-stage gate driving signal.
8. A display device comprising at least one gate driver circuit as claimed in any one of claims 1 to 7.
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| CN109883562B (en) * | 2019-03-07 | 2021-03-09 | 昆山龙腾光电股份有限公司 | Display device, temperature sensor and temperature sensing method |
| CN111564132A (en) * | 2020-05-29 | 2020-08-21 | 厦门天马微电子有限公司 | Shift register, display panel and display device |
| CN112908235B (en) * | 2021-01-26 | 2022-09-23 | 昆山龙腾光电股份有限公司 | Gate drive unit, gate drive circuit and display device |
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