CN108154836B

CN108154836B - Shifting register unit, driving method thereof and grid driving circuit

Info

Publication number: CN108154836B
Application number: CN201810003605.4A
Authority: CN
Inventors: 古宏刚; 邵贤杰; 宋洁
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Priority date: 2018-01-03
Filing date: 2018-01-03
Publication date: 2020-07-07
Anticipated expiration: 2038-01-03
Also published as: CN108154836A

Abstract

The invention discloses a shift register unit, a driving method thereof and a gate driving circuit, relates to the technical field of display, and aims to solve the problem that the conventional gate driving circuit cannot meet the requirement of a display device on narrow frame. The shift register unit comprises N output modules, wherein the nth output module is used for controlling whether an nth grid driving signal output end is connected with an nth clock signal input end and controlling whether an nth grid driving signal output end is connected with a second end of the capacitor module under the control of an nth clock signal input end and a pull-up node; the first level input end is used for receiving a first level signal and outputting a first level signal to the first gate drive signal output end; n is a positive integer less than or equal to N. The shift register unit provided by the invention is used for providing a grid driving signal.

Description

Shifting register unit, driving method thereof and grid driving circuit

Technical Field

The invention relates to the technical field of display, in particular to a shift register unit, a driving method thereof and a grid driving circuit.

Background

With the continuous development of display technologies, more and more display devices adopt a Gate On Array (GOA) technology, in which a Gate driver circuit is directly integrated in a non-display area of an array substrate, thereby reducing the frame width of the array substrate to a great extent. The grid driving circuit integrated on the array substrate comprises a plurality of shift register units, each shift register unit corresponds to one grid line on the array substrate, and the grid lines are driven by outputting grid driving signals.

The conventional shift register unit generally comprises an input module, an energy storage module, an output module and a reset module, and the working process of the shift register unit is as follows: in the input period, the input module pulls up the voltage of the pull-up node; in the output period, the output module outputs a grid driving signal under the action of the energy storage module; in a reset period, the reset module resets the voltage of the pull-up node and the gate driving signal to a gate-off voltage; during the holding period, the output end of the output module is always in a floating state, and the grid turn-off voltage is kept. Because each grid line on the array substrate needs to correspond to one shift register unit, and each shift register unit needs to comprise an input module, an energy storage module, an output module and a reset module, a grid driving circuit arranged on the array substrate comprises too many devices, and the narrow frame requirement of the display device cannot be met

Disclosure of Invention

The invention aims to provide a shift register unit, a driving method thereof and a gate driving circuit, which are used for solving the problem that the gate driving circuit in the prior art cannot meet the requirement of a display device on narrow frame.

In order to achieve the above purpose, the invention provides the following technical scheme:

a first aspect of the present invention provides a shift register unit comprising:

the pull-up node control module is respectively connected with the input control end, the power signal input end, the pull-up node, the Nth reset end and the first level input end;

the pull-down node control module is respectively connected with the pull-up node, the second level input end, the first level input end and the pull-down node;

a first end of the capacitor module is connected with the pull-up node;

n output modules, N being an integer greater than 1, wherein,

the nth output module is respectively connected with the nth clock signal input end, the pull-up node, the second end of the capacitor module, the nth gate drive signal output end, the first level input end and the nth reset end; the nth output module is used for: under the control of the nth clock signal input end and the pull-up node, controlling whether the nth gate driving signal output end is connected with the nth clock signal input end and controlling whether the nth gate driving signal output end is connected with the second end of the capacitor module; the nth output module is further configured to: under the control of the nth reset end, controlling whether the nth gate driving signal output end is connected with the second end of the capacitor module or not and controlling whether the nth gate driving signal output end is connected with the first level input end or not; n is a positive integer less than or equal to N.

Further, the shift register unit further includes: n output control modules, wherein,

the nth output control module is respectively connected with the (n + 1) th clock signal input end, the nth output module and the first level input end, and is used for controlling whether the nth output module is connected with the first level input end or not under the control of the (n + 1) th clock signal input end, so that the nth output module controls whether the nth gate driving signal output end is connected with the nth clock signal input end or not.

Further, the shift register unit further includes: a node discharge module and N output discharge modules, wherein,

the node discharging module is respectively connected with the pull-down node, the pull-up node and the first level input end and is used for controlling whether the pull-up node is connected with the first level input end or not under the control of the pull-down node;

the nth output end discharging module is respectively connected with the pull-down node, the nth grid driving signal output end and the first level input end and is used for controlling whether the nth grid driving signal output end is connected with the first level input end or not under the control of the pull-down node.

Further, the pull-up node control module is configured to control whether the power signal input terminal is connected to the pull-up node under the control of the input control terminal, and is further configured to control whether the pull-up node is connected to the first level input terminal under the control of the nth reset terminal;

the pull-down node control module is used for controlling whether the pull-down node is connected with the second level input end or not under the control of the second level input end and the pull-up node, and is also used for controlling whether the pull-down node is connected with the first level input end or not under the control of the pull-up node.

Further, the nth output module comprises:

a gate of the first switching tube is connected with the nth clock signal input end, and a first pole of the first switching tube is connected with the pull-up node;

a gate of the second switch tube is connected with a second pole of the first switch tube, a first pole of the second switch tube is connected with the nth clock signal input end, and a second pole of the second switch tube is connected with the nth gate drive signal output end;

a gate of the third switching tube is connected with a second pole of the second switching tube, a first pole of the third switching tube is connected with a second end of the capacitor module, and a second pole of the third switching tube is connected with the nth gate driving signal output end;

and the grid electrode of the fourth switching tube is connected with the nth reset end, the first pole of the fourth switching tube is connected with the nth grid electrode driving signal output end, and the second pole of the fourth switching tube is connected with the first level input end.

Further, the nth output control module includes:

a gate of the fifth switching tube is connected to the (n + 1) th clock signal input end, a first pole of the fifth switching tube is connected to the gate of the second switching tube, and a second pole of the fifth switching tube is connected to the first level input end.

Further, the node discharging module includes:

a gate of the sixth switching tube is connected to the pull-down node, a first pole of the sixth switching tube is connected to the pull-up node, and a second pole of the sixth switching tube is connected to the first level input terminal;

the nth output terminal discharging module includes:

a gate of the seventh switching tube is connected to the pull-down node, a first pole of the seventh switching tube is connected to the nth gate driving signal output terminal, and a second pole of the seventh switching tube is connected to the first level input terminal.

Further, the pull-up node control module comprises:

a gate of the eighth switch tube is connected to the input control terminal, a first pole of the eighth switch tube is connected to the power signal input terminal, and a second pole of the eighth switch tube is connected to the pull-up node;

a gate of the ninth switching tube is connected to the nth reset terminal, a first pole of the ninth switching tube is connected to the pull-up node, and a second pole of the ninth switching tube is connected to the first level input terminal;

the pull-down node control module includes:

a tenth switching tube, a gate of the tenth switching tube and a first pole of the tenth switching tube are both connected with the second level input end;

a gate of the eleventh switch tube is connected to the second pole of the tenth switch tube, a first pole of the eleventh switch tube is connected to the second level input end, and a second pole of the eleventh switch tube is connected to the pull-down node;

a twelfth switching tube, a gate of which is connected to the pull-up node, a first pole of which is connected to the pull-down node, and a second pole of which is connected to the first level input terminal;

a gate of the thirteenth switching tube is connected to the pull-up node, a first pole of the thirteenth switching tube is connected to the gate of the eleventh switching tube, and a second pole of the thirteenth switching tube is connected to the first level input end.

Based on the technical solution of the shift register unit, a second aspect of the present invention provides a gate driving circuit, including the shift register unit.

Based on the technical solution of the shift register unit, a third aspect of the present invention provides a driving method for a shift register unit, which is applied to the shift register unit, and the driving method includes:

in the input period, under the control of the input control end, the pull-up node control module controls the power signal input end to be connected with the pull-up node;

n output periods, wherein,

in an nth output period, under the control of the nth clock signal input end and the pull-up node, the nth output module controls the nth gate driving signal output end to be connected with the nth clock signal input end and controls the nth gate driving signal output end to be connected with the second end of the capacitor module; under the control of an n-1 reset terminal, the n-1 output module controls the n-1 gate driving signal output terminal to be connected with the first level input terminal and controls the n-1 gate driving signal output terminal to be disconnected with the second terminal of the capacitor module;

in a reset period, under the control of the nth reset terminal, the nth output module controls the connection between the nth gate driving signal output terminal and the first level input terminal and controls the disconnection between the nth gate driving signal output terminal and the second terminal of the capacitor module; under the control of the Nth reset terminal, the pull-up node control module controls the pull-up node to be connected with the first level input terminal;

in a holding period, under the control of the second level input end and the pull-up node, the pull-down node control module controls the pull-down node to be connected with the second level input end and controls the pull-down node to be disconnected with the first level input end.

Further, when the shift register unit further includes N output control modules, the driving method further includes:

in the nth output period, under the control of the nth clock signal input end, the nth-1 output control module controls the nth-1 gate driving signal output end to be disconnected from the nth-1 clock signal input end by controlling the nth-1 output module to be connected with the first level input end;

in the reset period, under the control of the N +1 th clock signal input end, the nth output control module controls the nth output module to be connected with the first level input end so as to control the nth gate driving signal output end to be disconnected with the nth clock signal input end.

Further, when the shift register unit further includes a node discharge module and N output terminal discharge modules, the driving method further includes:

in the reset period and the holding period, under the control of the pull-down node, the node discharge module controls the pull-up node to be connected with the first level input end; under the control of the pull-down node, the nth output end discharging module controls the nth gate driving signal output end to be connected with the first level input end.

In the technical scheme provided by the invention, a plurality of output modules share the same pull-up node control module, pull-down node control module, capacitance module, pull-up node and pull-down node, and are combined with time sequence control to control the corresponding output modules to output gate drive signals at different output time periods, so that one shift register unit can output a plurality of gate drive signals at different time intervals. In addition, the number of the thin film transistors required by the gate driving circuit is small, so that the design requirement of narrowing the frame of the display device is well met when the gate driving circuit is applied to the display device.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

FIG. 1 is a block diagram of a shift register unit according to an embodiment of the present invention;

FIG. 2 is a timing diagram illustrating operation of a shift register unit according to an embodiment of the present invention;

FIG. 3 is a first schematic diagram of a shift register unit according to an embodiment of the present invention;

FIG. 4 is a first schematic diagram of a shift register unit according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention.

Reference numerals:

1-pull-up node control module, 2-pull-down node control module,

31-a first output module, 32-a second output module,

33-a third output module, 34-a fourth output module,

41 a first output control module, 42-a second output control module,

51-node discharge module, 52-first output terminal discharge module,

53-second output terminal discharging module, 6-capacitance module,

71-a first shift register unit, 72-a second shift register unit,

INPUT-INPUT control terminal, PD-pull-down node,

PU-pull-up node, RESET 1-first RESET terminal,

RESET 2-second RESET terminal, RESET 3-third RESET terminal,

RESET 4-fourth RESET terminal, VGL-first level input terminal,

VGH-a second level input terminal, VDD-a power supply signal input terminal,

CLK 1-first clock signal input, CLK 2-second clock signal input,

CLK3, third clock signal input, P1, input period,

p21-first output period, P22-second output period,

p3-reset period, P4-hold period,

OUTPUT 1-the first gate drive signal OUTPUT, OUTPUT 2-the second gate drive signal OUTPUT,

OUTPUT 3-the third gate drive signal OUTPUT, OUTPUT 4-the fourth gate drive signal OUTPUT,

c1-first capacitor, T1-first switch tube,

t2-second switch tube, T3-third switch tube,

t4-a fourth switching tube, T5-a fifth switching tube,

t6-sixth switch tube, T7-seventh switch tube,

t8-eighth switch tube, T9-ninth switch tube,

t10-tenth switch tube, T11-eleventh switch tube,

t12-twelfth switch tube, T13-thirteenth switch tube,

STV-start frame signal output.

Detailed Description

In order to further explain the shift register unit, the driving method thereof and the gate driving circuit provided by the embodiment of the invention, the following detailed description is made with reference to the accompanying drawings.

Referring to fig. 1, a shift register unit according to an embodiment of the present invention includes: the device comprises a pull-up node control module 1, a pull-down node control module 2, a capacitance module 6 and N output modules.

Specifically, the pull-up node control module 1 is respectively connected to the INPUT control terminal INPUT, the power signal INPUT terminal VDD, the pull-up node PU, the nth reset terminal, and the first level INPUT terminal VGL; the pull-down node control module 2 is respectively connected with the pull-up node PU, the second level input end VGH, the first level input end VGL and the pull-down node PD; the first end of the capacitor module 6 is connected with the pull-up node PU; for the N output modules, N is an integer greater than 1, and the nth output module is respectively connected to the nth clock signal input terminal, the pull-up node PU, the second terminal of the capacitor module 6, the nth gate driving signal output terminal, the first level input terminal VGL, and the nth reset terminal; the nth output module is used for: under the control of the nth clock signal input end and the pull-up node PU, controlling whether the nth gate driving signal output end is connected with the nth clock signal input end and controlling whether the nth gate driving signal output end is connected with the second end of the capacitor module 6; the nth output module is further used for: under the control of the nth reset end, controlling whether the nth grid driving signal output end is connected with the first level input end VGL or not; n is a positive integer less than or equal to N.

Referring to fig. 2, when the shift register unit actually works, the shift register unit includes a plurality of duty cycles, and each duty cycle includes: an input period P1, N output periods, a reset period P3, and a hold period P4.

In an INPUT period P1, under the control of the INPUT control terminal INPUT, the pull-up node control module 1 controls the power signal INPUT terminal VDD to be connected to the pull-up node PU, and pulls up the potential of the pull-up node PU; under the control of the pull-up node PU, the pull-down node control module 2 controls the connection between the pull-down node PD and the first level input terminal VGL.

In N output periods, wherein,

in the first OUTPUT period P21, under the control of the first clock signal input terminal CLK1 and the pull-up node PU, the first OUTPUT module 31 controls the first gate driving signal OUTPUT terminal OUTPUT1 to be connected to the first clock signal input terminal CLK1 and controls the first gate driving signal OUTPUT terminal OUTPUT1 to be connected to the second terminal of the capacitor module 6, so that the first gate driving signal OUTPUT terminal OUTPUT1 OUTPUTs the first gate driving signal and further pulls up the potential of the pull-up node PU;

when n is greater than 1, in the nth output period, under the control of the nth clock signal input end and the pull-up node PU, the nth output module controls the nth gate driving signal output end to be connected with the nth clock signal input end and controls the nth gate driving signal output end to be connected with the second end of the capacitor module 6, so that the nth gate driving signal output end outputs the nth gate driving signal and keeps the potential of the pull-up node PU; under the control of the n-1 reset terminal, the n-1 output module controls the n-1 gate drive signal output terminal to be disconnected with the second terminal of the capacitor module 6, controls the n-1 gate drive signal output terminal to be connected with the first level input terminal VGL, and pulls down the potential of the n-1 gate drive signal output terminal; under the control of the pull-up node PU, the pull-down node control module 2 continues to control the connection between the pull-down node PD and the first level input terminal VGL.

In the reset period P3, under the control of the nth reset terminal, the nth output module controls the nth gate driving signal output terminal to be connected to the first level input terminal VGL and controls the nth gate driving signal output terminal to be disconnected from the second terminal of the capacitor module 6, so as to pull down the potential of the nth gate driving signal output terminal; under the control of the Nth reset terminal, the pull-up node control module 1 controls the pull-up node PU to be connected with the first level input terminal VGL, and pulls down the potential of the pull-up node PU; under the control of a high-level signal input end and a low-level pull-up node PU, the pull-down node control module 2 controls the pull-down node PD to be connected with a second level input end VGH, and controls the pull-down node PD not to be connected with a first level input end VGL, so that the potential of the pull-down node PD is pulled up;

in the holding period P4, under the control of the second level input terminal VGH and the pull-up node PU with a low potential, the pull-down node control module 2 continues to control the pull-down node PD to be connected to the second level input terminal VGH, and control the pull-down node PD to be disconnected from the first level input terminal VGL, so as to hold the potential of the pull-down node PD at a high potential.

It is noted that the first level input terminal VGL can be selected as a low level input terminal, and the second level input terminal VGH can be selected as a high level input terminal, but is not limited thereto.

As can be seen from the structure and the specific working process of the shift register unit provided in the above embodiment, the shift register unit provided in the embodiment of the present invention includes a pull-up node control module 1, a pull-down node control module 2, a capacitance module 6, and N output modules, and each working cycle of the shift register unit sequentially includes an input period P1, N output periods, a reset period P3, and a holding period P4.

Specifically, in the first OUTPUT period P21, the first OUTPUT module 31 can control the first gate driving signal OUTPUT terminal OUTPUT1 to be connected to the first clock signal input terminal CLK1 and control the first gate driving signal OUTPUT terminal OUTPUT1 to be connected to the second terminal of the capacitor module 6, so that the first gate driving signal OUTPUT terminal OUTPUT1 OUTPUTs the first gate driving signal; when n is larger than 1, in the nth output period, the nth output module can control the nth gate drive signal output end to be connected with the nth clock signal input end and control the nth gate drive signal output end to be connected with the second end of the capacitor module 6, so that the nth gate drive signal output end outputs the nth gate drive signal, and meanwhile, under the control of the nth-1 reset end, the nth-1 output module controls the nth-1 gate drive signal output end to be disconnected with the second end of the capacitor module 6 and controls the nth-1 gate drive signal output end to be connected with the first level input end VGL, so that only the nth gate drive signal output end can output the nth gate drive signal in the nth output period.

It can be seen that, in the shift register unit, N output periods correspond to N output modules one to one, and in each output period, only one output module outputs a gate driving signal.

Therefore, compared with the prior art in which each shift register unit only includes one output module and can only output a gate driving signal for driving one gate line, in the shift register unit provided in the embodiment of the present invention, by setting a plurality of output modules to share the same pull-up node control module 1, pull-down node control module 2, capacitance module 6, pull-up node PU, and pull-down node PD, and combining with timing control, and controlling the corresponding output modules to output gate driving signals at different output periods, it is achieved that one shift register unit can output a plurality of gate driving signals at different times, and therefore, when the shift register unit provided in the embodiment of the present invention is used to form a gate driving circuit, the number of thin film transistors required by the gate driving circuit is reduced, thereby reducing power consumption and production cost of the gate driving circuit, the production yield is improved. In addition, the number of the thin film transistors required by the gate driving circuit is small, so that the design requirement of narrowing the frame of the display device is well met when the gate driving circuit is applied to the display device.

With continued reference to fig. 1 and fig. 2, the shift register unit according to the above embodiment further includes: and the N output control modules are respectively connected with the N +1 clock signal input end, the N output module and the first level input end VGL, and are used for controlling whether the N output module is connected with the first level input end VGL or not under the control of the N +1 clock signal input end so as to control whether the N gate drive signal output end is connected with the N clock signal input end or not.

Specifically, in the nth output period, under the control of the nth clock signal input end, the nth-1 output control module controls the nth-1 output module to be connected with the first level input end VGL so as to control the nth-1 gate driving signal output end to be disconnected with the nth-1 clock signal input end; in the reset period P3, the nth output control module controls the nth gate driving signal output terminal to be disconnected from the nth clock signal input terminal by controlling the nth output module to be connected to the first level input terminal VGL under the control of the N +1 th clock signal input terminal.

In the N output control modules included in the shift register unit, the N-1 output control module can control the N-1 gate driving signal output end to be disconnected with the N-1 clock signal input end by controlling the N-1 output module to be connected with the first level input end VGL when the N gate driving signal output end outputs the N gate driving signal, so that the N-1 gate driving signal output end can be connected with the low potential input end only under the control of the N-1 reset end in the N output period, the N-1 gate driving signal output end is stable low potential in the N output period, and the influence of the N-1 gate driving signal output end on the output of the N gate driving signal output end is avoided.

The nth output control module can control the nth gate driving signal output terminal to be disconnected from the nth clock signal input terminal by controlling the nth output module to be connected with the first level input terminal VGL during the reset period P3; therefore, in the reset period P3, the Nth gate driving signal output end can be connected with the low potential input end only under the control of the Nth reset end, so that the Nth gate driving signal output end is stable low potential in the reset period P3, and the stability of the work of the shift register unit is ensured.

With reference to fig. 1 and fig. 2, the shift register unit according to the above embodiment further includes a node discharging module 51 and N output discharging modules, wherein the node discharging module 51 is respectively connected to the pull-down node PD, the pull-up node PU and the first level input terminal VGL, and is configured to control whether the pull-up node PU is connected to the first level input terminal VGL or not under the control of the pull-down node PD; the nth output end discharging module is respectively connected with the pull-down node PD, the nth gate driving signal output end and the first level input end VGL and is used for controlling whether the nth gate driving signal output end is connected with the first level input end VGL or not under the control of the pull-down node PD.

In the reset period P3, under the control of the pull-down node PD with a high potential, the node discharge module 51 controls the pull-up node PU to be connected to the first level input terminal VGL, so as to pull down the potential of the pull-up node PU; under the control of the pull-down node PD with high potential, the nth output end discharge module controls the nth gate driving signal output end to be connected with the first level input end VGL, so that the nth gate driving signal output end does not output the gate driving signal.

In the holding period P4, the potential of the pull-up node PU continues to be pulled low under the control of the pull-down node PD at the high potential, and the nth gate driving signal output terminal continues not to output the gate driving signal.

In the shift register unit provided in the above embodiment, in the reset period P3 and the holding period P4, under the control of the high-level signal input terminal and the pull-up node PU with a low potential, the pull-down node control module 2 controls the pull-down node PD to be connected to the second level input terminal VGH, and controls the pull-down node PD to be disconnected from the first level input terminal VGL, so as to hold the potential of the pull-down node PD at a high potential; the pull-down node PD kept at a high potential can realize continuous discharge of the pull-up node PU and the N gate driving signal output ends in the reset period P3 and the holding period P4 by controlling the node discharge module 51 and the N output end discharge modules, so that the problem of coupling noise voltage caused by a clock signal input end is avoided, and the stability and yield of the shift register unit are improved. Therefore, the gate driving circuit formed by the shift register unit provided by the above embodiment has the characteristics of low noise, low power consumption and the like.

With reference to fig. 1 and fig. 2, the pull-up node control module 1 included in the shift register unit is configured to control whether the power signal INPUT terminal VDD is connected to the pull-up node PU under the control of the INPUT control terminal INPUT, and further configured to control whether the pull-up node PU is connected to the first level INPUT terminal VGL under the control of the nth reset terminal; the pull-down node control module 2 is used for controlling whether the pull-down node PD is connected with the second level input end VGH or not under the control of the second level input end VGH and the pull-up node PU, and is also used for controlling whether the pull-down node PD is connected with the first level input end VGL or not under the control of the pull-up node PU.

Specifically, in the INPUT period P1, the pull-up node control module 1 is configured to control the pull-up node PU to be connected to the INPUT control terminal INPUT, and in other periods except the INPUT period P1, the pull-up node control module 1 is configured to control the pull-up node PU to be disconnected from the INPUT control terminal INPUT; in the input period P1 and N output periods, the pull-up node control module 1 is configured to control the pull-up node PU to be disconnected from the first level input terminal VGL; in the reset period P3, the pull-up node control module 1 is configured to control the pull-up node PU to be connected to the first level input terminal VGL under the control of the nth reset terminal.

In the input period P1 and N output periods, the pull-down node control module 2 is configured to control the pull-down node PD to be disconnected from the second level input terminal VGH and control the pull-down node PD to be connected to the first level input terminal VGL under the control of the second level input terminal VGH and the pull-up node PU with a high potential; in the reset period P3 and the hold period P4, the pull-down node control module 2 is configured to control the pull-down node PD to be connected to the second level input terminal VGH and control the pull-down node PD to be disconnected from the first level input terminal VGL under the control of the second level input terminal VGH and the pull-up node PU with a low potential.

The pull-up node control module 1, the pull-down node control module 2, the capacitance module 6 and the N output modules provided in the above embodiments have various specific structures, and a specific structure of each module is given below, but not limited thereto.

As shown in fig. 3, the nth output module includes: a first switch tube T1, a second switch tube T2, a third switch tube T3 and a fourth switch tube T4, wherein a gate of the first switch tube T1 is connected to an nth clock signal input terminal, and a first pole of the first switch tube T1 is connected to a pull-up node PU; the grid electrode of the second switch tube T2 is connected with the second pole of the first switch tube T1, the first pole of the second switch tube T2 is connected with the nth clock signal input end, and the second pole of the second switch tube T2 is connected with the nth grid driving signal output end; the gate of the third switching tube T3 is connected to the second pole of the second switching tube T2, the first pole of the third switching tube T3 is connected to the second end of the capacitor module 6, and the second pole of the third switching tube T3 is connected to the nth gate driving signal output terminal; the gate of the fourth switch transistor T4 is connected to the nth reset terminal, the first pole of the fourth switch transistor T4 is connected to the nth gate driving signal output terminal, and the second pole of the fourth switch transistor T4 is connected to the first level input terminal VGL.

The nth output control module includes a fifth switch T5, a gate of the fifth switch T5 is connected to the (n + 1) th clock signal input terminal, a first pole of the fifth switch T5 is connected to the gate of the second switch, and a second pole of the fifth switch T5 is connected to the first level input terminal VGL.

The node discharge module 51 includes a sixth switch T6, a gate of the sixth switch T6 is connected to the pull-down node PD, a first pole of the sixth switch T6 is connected to the pull-up node PU, and a second pole of the sixth switch T6 is connected to the first level input terminal VGL.

The nth output terminal discharging module includes a seventh switch T7, a gate of the seventh switch T7 is connected to the pull-down node PD, a first pole of the seventh switch T7 is connected to the nth gate driving signal output terminal, and a second pole of the seventh switch T7 is connected to the first level input terminal VGL.

The pull-up node control module 1 includes: an eighth switch T8 and a ninth switch T9, wherein a gate of the eighth switch T8 is connected to the INPUT control terminal INPUT, a first pole of the eighth switch T8 is connected to the power signal INPUT terminal VDD, and a second pole of the eighth switch T8 is connected to the pull-up node PU; the gate of the ninth switch T9 is connected to the nth reset terminal, the first pole of the ninth switch T9 is connected to the pull-up node PU, and the second pole of the ninth switch T9 is connected to the first level input terminal VGL.

The pull-down node control module 2 includes: a tenth switching tube T10, an eleventh switching tube T11, a twelfth switching tube T12 and a thirteenth switching tube T13, wherein the gate of the tenth switching tube T10 and the first pole of the tenth switching tube T10 are both connected to the second level input terminal VGH; a gate of the eleventh switch T11 is connected to the second pole of the tenth switch T10, a first pole of the eleventh switch T11 is connected to the second level input terminal VGH, and a second pole of the eleventh switch T11 is connected to the pull-down node PD; a gate of the twelfth switch tube T12 is connected to the pull-up node PU, a first pole of the twelfth switch tube T12 is connected to the pull-down node PD, and a second pole of the twelfth switch tube T12 is connected to the first level input terminal VGL; the gate of the thirteenth switch T13 is connected to the pull-up node PU, the first pole of the thirteenth switch T13 is connected to the gate of the eleventh switch, and the second pole of the thirteenth switch T13 is connected to the first level input terminal VGL.

The capacitor module 6 comprises a first capacitor C1, a first terminal of the first capacitor C1 is used as a first terminal of the capacitor module 6, and a second terminal of the first capacitor C1 is used as a second terminal of the capacitor module 6.

When the shift register unit with the above structure works, in the INPUT period P1, the INPUT control terminal INPUT controls the eighth switch tube T8 to be turned on, so that the pull-up node PU is connected with the power signal INPUT terminal VDD, and the potential of the pull-up node PU is pulled up; the pull-up node PU at a high potential controls the twelfth switching tube T12 to be switched on, so that the pull-down node PD is connected with the low level signal input end, the potential of the pull-down node PD is pulled down, meanwhile, the pull-up node PU at the high potential controls the thirteenth switching tube T13 to be switched on, the gate of the eleventh switching tube T11 is connected with the low level signal input end, the potential of the gate of the eleventh switching tube T11 is pulled down, so that the eleventh switching tube T11 is switched off, and the pull-down node PD is not connected with the second level input end VGH.

Taking N equal to 2 as an example, referring to fig. 1-4, the shift register unit includes two output modules, namely a first output module 31 and a second output module 32, and the two output modules have the same structure and each include a first switch transistor T1, a second switch transistor T2, a third switch transistor T3 and a fourth switch transistor T4. The shift register unit includes two output control modules, namely a first output control module 41 and a second output control module 42, and the two output control modules have the same structure and each include a fifth switch transistor T5. The shift register unit includes two output terminal discharging modules, namely a first output terminal discharging module 52 and a second output terminal discharging module 53, and the two output terminal discharging modules have the same structure and each include a seventh switch transistor T7.

In the first OUTPUT period P21, the first clock signal input terminal CLK1 controls the first switch tube T1 in the first OUTPUT module 31 to be turned on, so that the pull-up node PU of the high potential is connected to the gate of the second switch tube T2 in the first OUTPUT module 31, the pull-up node PU of the high potential controls the second switch tube T2 in the first OUTPUT module 31 to be turned on, so that the gate of the third switch tube T3 in the first OUTPUT module 31 and the first gate driving signal OUTPUT terminal OUTPUT1 are both connected to the first clock signal input terminal CLK1, the first clock signal input terminal CLK1 controls the third switch tube T3 in the first OUTPUT module 31 to be turned on, so that the first gate driving signal OUTPUT terminal OUTPUT1 is connected to the second terminal of the capacitance module 6, so that the first gate driving signal OUTPUT terminal OUTPUT1 OUTPUTs the first gate driving signal, and further pulls up the potential of the pull-up node PU.

In the second OUTPUT period P22, the second clock signal input terminal CLK2 controls the first switch tube T1 in the second OUTPUT module 32 to be turned on, so that the pull-up node PU with a high potential is connected to the gate of the second switch tube T2 in the second OUTPUT module 32, the pull-up node PU with a high potential controls the second switch tube T2 in the second OUTPUT module 32 to be turned on, so that the gate of the third switch tube T3 in the second OUTPUT module 32 and the second gate driving signal OUTPUT terminal OUTPUT2 are both connected to the second clock signal input terminal CLK2, the second clock signal input terminal CLK2 controls the third switch tube T3 in the second OUTPUT module 32 to be turned on, so that the second gate driving signal OUTPUT terminal OUTPUT2 is connected to the second terminal of the capacitance module 6, so that the second gate driving signal OUTPUT terminal OUTPUT2 OUTPUTs the second gate driving signal, and maintains the high potential of the pull-up node PU is further pulled up.

Meanwhile, in the second OUTPUT period P22, the first RESET terminal RESET1 controls the fourth switching tube T4 in the first OUTPUT block 31 to be turned on, so that the gates of the first gate driving signal OUTPUT terminal OUTPUT1 and the third switching tube T3 in the first OUTPUT block 31 are both connected to the low level signal input terminal, so that the third switching tube T3 in the first OUTPUT block 31 is turned off, the first gate driving signal OUTPUT terminal OUTPUT1 is not connected to the second terminal of the capacitance block 6, and the first gate driving signal OUTPUT terminal OUTPUT1 does not OUTPUT the gate driving signal. In addition, in the second OUTPUT period P22, the second clock signal input terminal CLK2 controls the fifth switching tube T5 in the first OUTPUT control block 41 to be turned on, so that the gate of the second switching tube T2 in the first OUTPUT block 31 is connected to the low level signal input terminal, and under the control of the low level signal input terminal, the second switching tube T2 in the first OUTPUT block 31 is turned off, so that the first gate driving signal OUTPUT terminal OUTPUT1 is not connected to the first clock signal input terminal CLK 1.

In the RESET period P3, under the control of the second RESET terminal RESET2, the fourth switching tube in the second OUTPUT module 32 is turned on, so that the second gate driving signal OUTPUT terminal OUTPUT2 and the gate of the third switching tube T3 in the second OUTPUT module 32 are both connected to the low level signal input terminal, so that the third switching tube T3 in the second OUTPUT module 32 is turned off, the second gate driving signal OUTPUT terminal OUTPUT2 is not connected to the second terminal of the capacitor module 6, and the second gate driving signal OUTPUT terminal OUTPUT2 does not OUTPUT the gate driving signal. Meanwhile, in the reset period P3, the third clock signal input terminal CLK3 controls the fifth switching tube T5 in the second OUTPUT control block 42 to be turned on, so that the gate of the second switching tube T2 in the second OUTPUT block 32 is connected to the low level signal input terminal, and under the control of the low level signal input terminal, the second switching tube T2 in the second OUTPUT block 32 is turned off, so that the second gate driving signal OUTPUT terminal OUTPUT2 is not connected to the second clock signal input terminal CLK 2. In addition, in the RESET period P3, the second RESET terminal RESET2 controls the ninth switching tube to be turned on, so that the pull-up node PU is connected to the low-level signal input terminal, and the potential of the pull-up node PU is pulled down; the pull-up node PU with a low potential controls the twelfth switch tube T12 and the thirteenth switch tube T13 to be turned off, and the second level input end VGH controls the tenth switch tube T10 and the eleventh switch tube T11 to be turned on, so that the pull-down node PD is connected with the high level signal input end to pull up the level of the pull-down node PD; the pull-down node PD at a high level controls the sixth switching tube T6 to be turned on, so that the pull-up node PU is connected with the first level input end VGL through the sixth switching tube T6, the pull-down node PD at a high level controls the seventh switching tube T7 in the first OUTPUT end discharging module 52 to be turned on, so that the first gate driving signal OUTPUT end OUTPUT1 is connected with the first level input end VGL, and the pull-down node PD at a high level controls the seventh switching tube T7 in the second OUTPUT end discharging module 53 to be turned on, so that the second gate driving signal OUTPUT end OUTPUT2 is connected with the first level input end VGL.

In the holding period P4, under the control of the second level input terminal VGH and the pull-up node PU with a low potential, the tenth switching tube T10 and the eleventh switching tube T11 are continuously turned on, and the twelfth switching tube T12 and the thirteenth switching tube T13 are continuously turned off, so that the pull-down node PD is continuously connected with the second level input terminal VGH, and the pull-down node PD is further kept at a high potential; the pull-down node PD with a high potential continues to control the sixth switching tube T6, the seventh switching tube T7 in the first OUTPUT terminal discharging module 52, and the seventh switching tube T7 in the second OUTPUT terminal discharging module 53 to be turned on, so that the pull-up node PU is kept at a low potential, and neither the first gate driving signal OUTPUT terminal OUTPUT1 nor the second gate driving signal OUTPUT terminal OUTPUT2 OUTPUTs a gate driving signal.

In the shift register unit with the above structure, in the input period P1 and each output stage, the potential of the pull-down node PD is pulled down, so that the sixth switching tube T6 and the seventh switching tube T7 included in each output module are both turned off, thereby ensuring the stability of the signals of the pull-up node and each gate driving signal output terminal.

In addition, in the shift register unit with the above structure, the fifth switch tube T5 is arranged in the output control module to control the on and off of the second switch tube T2 in the corresponding output module, so that noise is better released to the second switch tube T2 in each output module and each gate drive signal output end in each output period, the reset period P3 and the hold period P4, and the stability of the operation of the shift register unit is better improved.

It is to be noted that, in the shift register unit provided in the above embodiment, the N output modules output N gate driving signals in a one-to-one correspondence, where an nth gate driving signal output by the nth output module is used as a reset signal of the N-1 th reset terminal. In addition, when three or more output blocks are included in the shift register unit, the output blocks and the output control blocks included in the shift register unit can recycle the clock signals correspondingly output by the first, second, and third clock signal input terminals CLK1, CLK2, and CLK3 as necessary without introducing new clock signals.

In the present embodiment, each switch is an N-type transistor, and the first electrode is a source electrode and the second electrode is a drain electrode. The above-mentioned switch transistors may also be P-type transistors, and the circuit design in which each switch transistor is a P-type transistor is also within the protection scope of the present application. In addition, the clock signals correspondingly input by the clock signal input ends are pulse signals; under normal operation, the low level signal inputted from the first level input terminal VGL (which may be connected to the negative electrode of the power supply, but is not limited thereto) is a dc signal.

The embodiment of the invention also provides a gate driving circuit which comprises a plurality of shift register units provided by the embodiment.

The gate driving circuit may include a plurality of cascaded shift register units, and the structure and connection manner of the gate driving circuit will be described below by taking two shift register units as an example.

As shown in fig. 5, the gate driving circuit includes a first shift register unit 71 and a second shift register unit 72, wherein the first shift register unit 71 includes a pull-up node control module, a pull-down node control module, a capacitor module, a node discharge module, a first output terminal discharge module, a second output terminal discharge module, a first output control module, a second output control module (not shown), a first output module 31, and a second output module 32; the second shift register unit 72 includes a pull-up node control module, a pull-down node control module, a capacitor module, a node discharge module, a first output terminal discharge module, a second output terminal discharge module, a first output control module, a second output control module (not shown), a third output module 33, and a fourth output module 34.

The first OUTPUT module 31 OUTPUTs a first gate driving signal through a first gate driving signal OUTPUT terminal OUTPUT1, the second OUTPUT module 32 OUTPUTs a second gate driving signal through a second gate driving signal OUTPUT terminal OUTPUT2, the third OUTPUT module 33 OUTPUTs a third gate driving signal through a third gate driving signal OUTPUT terminal OUTPUT3, and the fourth OUTPUT module 34 OUTPUTs a fourth gate driving signal through a fourth gate driving signal OUTPUT terminal OUTPUT 4.

When the gate driving circuit operates, an INPUT control signal is provided from the start frame signal output terminal STV to the INPUT control terminal INPUT of the first shift register unit 71; the INPUT control signal is provided by the second gate drive signal OUTPUT terminal OUTPUT2 to the INPUT control terminal INPUT of the second shift register unit 72. A first RESET signal is provided from the second gate driving signal OUTPUT terminal OUTPUT2 to the first RESET terminal RESET 1; a second RESET signal is provided from the third gate driving signal OUTPUT terminal OUTPUT3 to the second RESET terminal RESET 2; the third RESET terminal RESET3 is supplied with a third RESET signal from the fourth gate driving signal OUTPUT terminal OUTPUT 4.

Because the shift register unit is provided with a plurality of output modules which share the same pull-up node control module 1, pull-down node control module 2, capacitance module 6, pull-up node PU and pull-down node PD, and the corresponding output modules are controlled to output gate drive signals at different output time periods by combining time sequence control, the shift register unit can output a plurality of gate drive signals at different time intervals, therefore, when the gate drive circuit provided by the embodiment of the invention is composed of the shift register units, the number of thin film transistors required by the gate drive circuit is reduced, the power consumption is reduced, the production cost of the gate drive circuit is reduced, and the production yield is improved. In addition, the number of the thin film transistors required by the gate driving circuit is small, so that the design requirement of narrowing the frame of the display device is well met when the gate driving circuit is applied to the display device.

The embodiment of the present invention further provides a driving method of a shift register unit, which is applied to the shift register unit provided in the above embodiment, and the driving method of the shift register unit includes: an input period P1, N output periods, a reset period P3, and a hold period P4.

Specifically, in the INPUT period P1, under the control of the INPUT control terminal INPUT, the pull-up node control module 1 controls the power signal INPUT terminal VDD to be connected to the pull-up node PU.

In the nth output period, under the control of the nth clock signal input end and the pull-up node PU, the nth output module controls the nth gate driving signal output end to be connected with the nth clock signal input end and controls the nth gate driving signal output end to be connected with the second end of the capacitor module 6; under the control of the n-1 reset terminal, the n-1 output module controls the n-1 gate driving signal output terminal to be connected with the first level input terminal VGL and controls the n-1 gate driving signal output terminal to be disconnected with the second terminal of the capacitor module 6.

In the reset period P3, under the control of the nth reset terminal, the nth output module controls the nth gate driving signal output terminal to be connected with the first level input terminal VGL and controls the nth gate driving signal output terminal to be disconnected with the second terminal of the capacitor module 6; under the control of the nth reset terminal, the pull-up node control module 1 controls the pull-up node PU to be connected with the first level input terminal VGL.

In the holding period P4, under the control of the second level input terminal VGH and the pull-up node PU, the pull-down node control module 2 controls the pull-down node PD to be connected to the second level input terminal VGH and controls the pull-down node PD to be disconnected from the first level input terminal VGL.

As can be known from the structure and the specific driving process of the shift register unit, when the shift register unit is driven by the driving method according to the embodiment of the present invention, in the first OUTPUT period P21, the first OUTPUT module 31 can control the first gate driving signal OUTPUT terminal OUTPUT1 to be connected to the first clock signal input terminal CLK1, and control the first gate driving signal OUTPUT terminal OUTPUT1 to be connected to the second terminal of the capacitor module 6, so that the first gate driving signal OUTPUT terminal OUTPUT1 OUTPUTs the first gate driving signal; when n is larger than 1, in the nth output period, the nth output module can control the nth gate drive signal output end to be connected with the nth clock signal input end and control the nth gate drive signal output end to be connected with the second end of the capacitor module 6, so that the nth gate drive signal output end outputs the nth gate drive signal, and meanwhile, under the control of the nth-1 reset end, the nth-1 output module controls the nth-1 gate drive signal output end to be disconnected with the second end of the capacitor module 6 and controls the nth-1 gate drive signal output end to be connected with the first level input end VGL, so that only one gate drive signal output end can output the gate drive signal in each output period.

Therefore, when the shift register unit is driven by the driving method provided by the embodiment of the present invention, the shift register unit can control the corresponding output module to output the gate driving signal at different output periods by setting the plurality of output modules to share the same pull-up node control module 1, pull-down node control module 2, capacitance module 6, pull-up node PU and pull-down node PD, so that one shift register unit can output a plurality of gate driving signals at different time intervals. In addition, the number of the thin film transistors required by the gate driving circuit is small, so that the design requirement of narrowing the frame of the display device is well met when the gate driving circuit is applied to the display device.

When the shift register unit further includes N output control modules, the driving method provided in the above embodiment further includes:

in the nth output period, under the control of the nth clock signal input end, the nth-1 output control module controls the nth-1 gate driving signal output end to be disconnected from the nth-1 clock signal input end by controlling the nth-1 output module to be connected with the first level input end VGL.

In the reset period P3, the nth output control module controls the nth gate driving signal output terminal to be disconnected from the nth clock signal input terminal by controlling the nth output module to be connected to the first level input terminal VGL under the control of the N +1 th clock signal input terminal.

In the N output control modules included in the shift register unit driven by the driving method provided in the above embodiment, the (N-1) th output control module can control the (N-1) th gate driving signal output terminal to be disconnected from the (N-1) th clock signal input terminal by controlling the (N-1) th output module to be connected to the first level input terminal VGL when the N-th gate driving signal output terminal outputs the N-th gate driving signal; in the nth output period, the nth-1 gate driving signal output end can be connected with the low potential input end only under the control of the nth-1 reset end, so that the nth-1 gate driving signal output end is stable low potential in the nth output period, and the influence of the nth gate driving signal output end on the output of the nth gate driving signal output end is avoided. In addition, the nth output control block can control the nth gate driving signal output terminal to be disconnected from the nth clock signal input terminal by controlling the nth output block to be connected to the first level input terminal VGL during the reset period P3; therefore, in the reset period P3, the Nth gate driving signal output end can be connected with the low potential input end only under the control of the Nth reset end, so that the Nth gate driving signal output end is stable low potential in the reset period P3, and the stability of the work of the shift register unit is ensured.

When the shift register unit further includes the node discharging module 51 and N output terminal discharging modules, the driving method provided by the above embodiment further includes:

in the reset period P3 and the hold period P4, the node discharge module 51 controls the pull-up node PU to be connected to the first level input terminal VGL under the control of the pull-down node PD; under the control of the pull-down node PD, the nth output end discharging module controls the nth gate driving signal output end to be connected with the first level input end VGL.

In the shift register unit driven by the driving method provided by the above embodiment, in the reset period P3 and the holding period P4, under the control of the high-level signal input terminal and the pull-up node PU with a low potential, the pull-down node control module 2 controls the pull-down node PD to be connected with the second level input terminal VGH, and controls the pull-down node PD to be disconnected with the first level input terminal VGL, so as to hold the potential of the pull-down node PD at a high potential; the pull-down node PD kept at a high potential can realize continuous discharge of the pull-up node PU and the N gate driving signal output ends in the reset period P3 and the holding period P4 by controlling the node discharge module 51 and the N output end discharge modules, so that the problem of coupling noise voltage caused by a clock signal input end is avoided, and the yield of the shift register unit is improved. Therefore, the gate driving circuit formed by the shift register unit provided by the above embodiment has the characteristics of low noise, low power consumption and the like.

It should be noted that, in the present specification, all the embodiments are described in a progressive manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the method embodiments, since they are substantially similar to the product embodiments, they are described simply, and reference may be made to the partial description of the product embodiments for relevant points.

In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A shift register cell, comprising:

a first end of the capacitor module is connected with the pull-up node;

n output modules, N being an integer greater than 1, wherein,

2. The shift register cell of claim 1, further comprising:

n output control modules, wherein,

the nth output control module is respectively connected with the (n + 1) th clock signal input end, the nth output module and the first level input end, and is used for controlling whether the nth output module is connected with the first level input end or not under the control of the (n + 1) th clock signal input end so as to enable the nth output module to control whether the nth gate driving signal output end is connected with the nth clock signal input end or not;

the nth output module includes:

a gate of the fourth switching tube is connected with the nth reset end, a first pole of the fourth switching tube is connected with the nth gate driving signal output end, and a second pole of the fourth switching tube is connected with the first level input end;

the nth output control module includes:

3. The shift register cell of claim 1, further comprising:

a node discharge module and N output discharge modules, wherein,

4. The shift register cell of claim 1,

the pull-up node control module is used for controlling whether the power signal input end is connected with the pull-up node or not under the control of the input control end and controlling whether the pull-up node is connected with the first level input end or not under the control of the Nth reset end;

5. The shift register cell of claim 3,

the node discharge module includes:

the nth output terminal discharging module includes:

6. The shift register cell of claim 4,

the pull-up node control module comprises:

the pull-down node control module includes:

7. A gate drive circuit comprising a plurality of shift register cells according to any one of claims 1 to 6.

8. A driving method of a shift register unit, which is applied to the shift register unit according to any one of claims 1 to 6, the driving method comprising:

n output periods, wherein,

9. The method of driving a shift register unit according to claim 8, wherein when the shift register unit further includes N output control modules, the method further includes:

in the nth output period, under the control of the nth clock signal input end, the nth-1 output control module controls the connection between the nth-1 gate driving signal output end and the nth-1 clock signal input end by controlling the connection between the gate of a second switching tube in the nth-1 output module and the first level input end;

in the reset period, under the control of the N +1 th clock signal input end, the nth output control module controls the N-th gate driving signal output end to be disconnected from the nth clock signal input end by controlling the gate of the second switching tube in the nth output module to be connected with the first level input end.

10. The method for driving the shift register cell according to claim 8, wherein when the shift register cell further includes a node discharge module and N output terminal discharge modules, the method further includes: