CN113763866B - Shift register and driving method thereof, grid driving circuit and display device - Google Patents

Shift register and driving method thereof, grid driving circuit and display device Download PDF

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Publication number
CN113763866B
CN113763866B CN202111256179.3A CN202111256179A CN113763866B CN 113763866 B CN113763866 B CN 113763866B CN 202111256179 A CN202111256179 A CN 202111256179A CN 113763866 B CN113763866 B CN 113763866B
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pull
signal
control
shift register
module
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CN113763866A (en
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秦文文
闫伟
王珍
孙建
张寒
王德帅
山岳
张亚东
张健
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

The application provides a shift register, a driving method thereof, a grid driving circuit and a display device. The shift register includes: the device comprises a first input module, a first pull-down control module, a first output module and a first pull-down module; the first input module is electrically connected with the first input signal end, the first control signal end and the first pull-up node respectively; the first pull-down control module is respectively and electrically connected with the first pull-up node, the first input signal end, the first power signal end and the pull-down node; the first output module is respectively and electrically connected with the first pull-up node, the first clock signal end and the output end; the first pull-down module is electrically connected with the pull-down node, the first power signal end and the output end respectively. According to the technical scheme, normal output of the output end can be guaranteed when the transistor characteristic drifts, and then the stability of the shift register can be improved.

Description

Shift register and driving method thereof, grid driving circuit and display device
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, a gate driving circuit, and a display device.
Background
Along with the development trend of high integration of display panels, the GOA (Gate Driver On Array, array substrate gate driving) technology has emerged, and the GOA technology directly integrates a gate driving circuit of a display panel on an array substrate to replace an external driving chip, so that the GOA technology has the advantages of low cost, fewer procedures, high productivity and the like, and the gate driving circuit integrated on the array substrate by using the GOA technology is also called a GOA circuit or a shift register.
The existing shift register has poor stability, the characteristics of transistors at the input end in the shift register can shift after the reliability verification of the display panel or after long-time operation, and the threshold voltage and on-state current of the transistors at the input end are degraded, so that the shift register has abnormal output and cannot work normally.
Disclosure of Invention
The embodiment of the application provides a shift register, a driving method thereof, a grid driving circuit and a display device, so as to solve the problems in the related art, and the technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a shift register, including: the device comprises a first input module, a first pull-down control module, a first output module and a first pull-down module;
The first input module is electrically connected with the first input signal end, the first control signal end and the first pull-up node respectively; the first input module is used for providing a signal of a first control signal end for the first pull-up node under the control of a signal of a first input signal end;
the first pull-down control module is respectively and electrically connected with the first pull-up node, the first input signal end, the first power signal end and the pull-down node; the first pull-down control module is used for providing a signal of a first power supply signal end for the pull-down node under the control of the first input signal end and the first pull-up node;
the first output module is respectively and electrically connected with the first pull-up node, the first clock signal end and the output end; the first output module is used for providing a signal of a first clock signal end for the output end under the control of the potential of the first pull-up node so that the output end outputs a signal of a second clock signal end;
the first pull-down module is respectively and electrically connected with the pull-down node, the first power supply signal end and the output end; the first pull-down module is used for providing the potential of the first power supply signal end for the output end under the control of the potential of the pull-down node.
In a second aspect, an embodiment of the present application provides a gate driving circuit, including M cascaded shift registers provided in the first aspect of the embodiment of the present application, where M is an integer greater than 1;
The control end of the first input module in the 1 st-i th shift register is electrically connected with the frame trigger signal end;
the control end of the first input module in the N-th level shift register is electrically connected with the output end of the N-i-th level shift register;
the output end of the N-th shift register is electrically connected with the control end of the first input module in the (n+i) -th shift register;
i is a positive integer and N is an integer greater than i.
In a third aspect, embodiments of the present application provide a display device, including the gate driving circuit provided in the second aspect of embodiments of the present application.
In a fourth aspect, an embodiment of the present application provides a driving method of a shift register, which is applied to the shift register provided in the first aspect of the embodiment of the present application, where the driving method includes:
in the precharge stage, a first input module in the shift register provides a signal of a first control signal end for a first pull-up node under the control of a signal of a first input signal end, so that the potential of the first pull-up node is a first potential;
the first pull-down control module in the shift register provides a signal of a first power supply signal end for the pull-down node under the control of a first potential of a first pull-up node and a signal of a first input signal end, so that the potential of the pull-down node is a second potential; the second potential is lower than the first potential;
A first output module in the shift register outputs a signal of a second potential of the second clock signal end under the control of the potential of the first pull-up node;
in the output display stage, the first output module outputs a signal of a third potential of the second clock signal end; the third potential is higher than the first potential and the second potential.
The advantages or beneficial effects in the technical scheme at least comprise:
the first pull-down control module is directly and electrically connected with the first input signal end, and the potential of the pull-down node is pulled down under the control of the first input signal end, so that the first pull-down module is prevented from being abnormally opened, and further adverse influence of the first pull-down module on the output signal of the output end is prevented; the first input module is not needed for regulating the potential of the pull-down node, and even if the first input module has the characteristic drift of a transistor, the regulation of the potential of the pull-down node is not influenced, the normal output of an output end can be ensured, and the stability of the shift register can be further improved.
The foregoing summary is for the purpose of the specification only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present application will become apparent by reference to the drawings and the following detailed description.
Drawings
In the drawings, the same reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily drawn to scale. It is appreciated that these drawings depict only some embodiments according to the disclosure and are not therefore to be considered limiting of its scope.
FIG. 1 is a schematic diagram of a shift register according to the present application;
FIG. 2 is a schematic diagram of signal timing related to the shift register shown in FIG. 1;
FIG. 3 is a schematic diagram showing the simulation of the output of the shift register shown in FIG. 1 when the threshold voltage Vth of the transistors T1 and T6 is increased to 2.6V;
FIG. 4 is a schematic diagram showing the output simulation of the shift register shown in FIG. 1 when the threshold voltage Vth of the transistors T1 and T6 is increased to 2.7 volts;
FIG. 5 is a schematic diagram showing the output simulation of the shift register shown in FIG. 1 when the on-state current Ion of the transistors T1 and T6 is reduced to 1E-4A;
FIG. 6 is a schematic diagram showing the output simulation of the shift register shown in FIG. 1 when the on-state current Ion of the transistors T1 and T6 is reduced to 1E-5A;
FIG. 7 is a schematic diagram illustrating the internal current of the shift register of FIG. 1 during driving scan;
FIG. 8 is a schematic diagram of a shift register according to an embodiment of the present disclosure;
FIG. 9 is a schematic diagram of a shift register according to another embodiment of the present disclosure;
fig. 10 is a schematic circuit diagram of a shift register according to an embodiment of the present disclosure;
FIG. 11 is a schematic diagram of a cascade relationship of shift registers in a gate driving circuit according to an embodiment of the present disclosure;
fig. 12 is a schematic diagram of a driving method of a shift register according to an embodiment of the present application;
fig. 13 is a schematic signal timing diagram related to a driving method of a shift register according to an embodiment of the present application;
fig. 14 is an output simulation diagram of the shift register provided in the embodiment of the present application when the threshold voltage Vth of the first switch unit T1 and the second switch unit T2 is increased to 10 v;
fig. 15 is an output simulation schematic diagram of the shift register provided in the embodiment of the present application when the on-state currents Ion of the first switch unit T1 and the second switch unit T2 are reduced to 1E-6 amperes;
fig. 16 is a schematic diagram of simulation of internal current of the shift register during driving scanning according to the embodiment of the present application.
Detailed Description
Hereinafter, only certain exemplary embodiments are briefly described. As will be recognized by those of skill in the pertinent art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present application. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
Technical terms referred to in the present application are explained first as follows:
and (3) dependency verification: and (3) placing the produced product in environments with different temperatures and different humidity or under the limit voltage condition, and testing whether the performance of the product is changed.
The conventional shift register has a structure of 11T2C (11 transistors and 2 capacitors) as shown in fig. 1, and the shift register has a signal timing related to the operation as shown in fig. 2, and referring to fig. 1 and 2, the shift register is divided into the following stages:
in the stage T1, the OUT_N-1 signal and the VGH_G signal are high, the transistors T1 and T9 are conducted to charge the capacitor C1, and the PUCN point and the PU point are raised but not completely raised; the CKB signal is high, the transistor T7 is turned on, the PD point is raised, and the transistor T6 is turned on under the control of the PUCN point to pull the PD point low, but not completely low; the CK signal is low, the transistor T3 is turned on under the control of the PU point, and the output terminal out_n outputs a low level signal.
In the t2 stage, the OUT_N-1 signal, the CKB signal and the CK signal are all low level, the PUCN point, the PU point and the PD point all keep the level state regulated in the t1 stage, and the output end OUT_N is low level.
In the t3 stage, the PU point level gradually increases and the PD point gradually decreases due to the bootstrap action of the capacitor C1, the CK signal becomes high, and the output terminal out_n becomes high.
In the t4 stage, the OUT_N-1 signal, the CKB signal and the CK signal are all low level, the PUCN point, the PU point and the PD point all keep the level state regulated in the t3 stage, and the output end OUT_N becomes low level.
In the stage T5, the CKB signal is high, the transistor T7 is turned on, the PD point is high, the transistor T4 is turned on, the CK signal is low, the PU point is pulled down by the transistor T5, the transistor T3 is turned off, the output terminal out_n is still low, and the shift register ends the output of the stage.
In the stage after the t5 stage, the PD point keeps high level, pulls down the level of the PU point, and keeps the output end OUT_N low level until the shift register of the stage of the next frame is started.
In the above scheme of the existing shift register, the transistors T1 and T6 are easy to generate characteristic shift, when the transistors T1 and T6 generate characteristic shift, the threshold voltage Vth of the transistors T1 and T6 will increase, the on-state current Ion will greatly decrease, resulting in insufficient charging of the C1 in the T1 stage, the levels of the T1 to T3 stages and the PU point are not high enough, the PD point cannot be pulled down completely, and the transistor T4 cannot be turned off completely, the transistor T4 is turned on and the output terminal out_n will be pulled down, resulting in abnormal output of the output terminal out_n.
Fig. 3 shows a schematic diagram of a conventional shift register for outputting a signal when the threshold voltage Vth of the transistors T1 and T6 increases to 2.6 v, fig. 4 shows a schematic diagram of a conventional shift register for outputting a signal when the threshold voltage Vth of the transistors T1 and T6 increases to 2.7 v, fig. 5 shows a schematic diagram of a conventional shift register for outputting a signal when the on-state currents Ion of the transistors T1 and T6 decrease to 1E-4 a, and fig. 6 shows a schematic diagram of a conventional shift register for outputting a signal when the on-state currents Ion of the transistors T1 and T6 decrease to 1E-5 a.
As can be seen from fig. 3 to 6, when the threshold voltage Vth of the transistors T1 and T6 is increased to 2.7 volts or the on-state current Ion is reduced to 1E-5 amperes, the output of the output terminal out_n of the existing shift register is significantly abnormal.
In addition, in the period T1, since the transistor T6 is turned on when the PU point is raised to the high level, the CKB signal is at the high level, the transistor T7 is turned on, and a path from the high level of CKB to the low level of VGL is formed between T7 and T6, so that a large current is generated. Fig. 7 shows a schematic diagram of an internal path current of a conventional shift register, and as shown in fig. 7, simulation results show that a current value of a path formed by T7-T6 is higher than 100uA, a path on time is the same as a CKB signal on time, and compared with working states of other processes, power consumption caused by a large current at this time is main power consumption of the shift register.
The following describes the technical solution of the present application and how the technical solution of the present application solves the above technical problems in detail with specific embodiments.
The embodiment of the application provides a shift register, as shown in fig. 8, the shift register may include: a first input module 801, a first pull-down control module 802, a first output module 803, and a first pull-down module 804.
The first input module 801 is electrically connected to the first input signal terminal out_n-1, the first control signal terminal CN, and the first pull-up node PUCN, respectively; the first input module 801 is configured to provide a signal of the first control signal terminal CN to the first pull-up node PUCN under the control of a signal of the first input signal terminal out_n-1.
The first pull-down control module 802 is electrically connected to the first pull-up node PUCN, the first input signal terminal out_n-1, the first power signal terminal VGL, and the pull-down node PD, respectively; the first pull-down control module 802 is configured to provide a signal of the first power signal terminal VGL to the pull-down node PD under the control of the first input signal terminal out_n-1 or the first pull-up node PUCN.
The first output module 803 is electrically connected to the first pull-up node PUCN, the first clock signal terminal CK1, and the output terminal out_n, respectively; the first output module 803 is configured to provide the signal of the first clock signal terminal CK1 to the output terminal out_n under the control of the potential of the first pull-up node PUCN, so that the output terminal out_n outputs the signal of the first clock signal terminal CK 1.
The first pull-down module 804 is electrically connected to the pull-down node PD, the first power signal terminal VGL, and the output terminal out_n, respectively; the first pull-down module 804 is configured to provide the potential of the first power signal terminal VGL to the output terminal out_n under the control of the potential of the pull-down node PD.
In the shift register provided in this embodiment of the present application, the first pull-down control module 802 is directly electrically connected to the first input signal terminal out_n-1, and the potential of the pull-down node PD is pulled down under the control of the first input signal terminal out_n-1, so as to avoid abnormal opening of the first pull-down module 804 caused by failure to completely pull down the pull-down node PD, and further avoid adverse effects of the first pull-down module 804 on the output signal of the output terminal out_n; the first input module 801 is not needed for adjusting the potential of the pull-down node PD, and even if the first input module 801 has characteristic drift of a transistor, the adjustment of the potential of the pull-down node PD is not affected, so that the normal output of the output end OUT_N can be ensured, and the stability of the shift register can be improved.
In an alternative implementation manner, as shown in fig. 9, the shift register provided in the embodiment of the present application further includes: a second pull-down control module 805.
The second pull-down control module 805 is electrically connected to the first control signal terminal CN, the second clock signal terminal CK2, the second power signal terminal VG, and the pull-down node PD, respectively; the second pull-down control module 805 is configured to provide the signal of the second power signal terminal VG to the pull-down node PD based on the signal of the second clock signal terminal CK2 under the control of the first control signal terminal CN.
In an alternative implementation manner, as shown in fig. 9, the shift register provided in the embodiment of the present application further includes: a second input module 806. The second input module 806 is electrically connected to the second input signal terminal out_n+1, the second control signal terminal CNB, and the first pull-up node PUCN, respectively; the second input module 806 is configured to provide the signal of the second control signal terminal CNB to the first pull-up node PUCN under the control of the signal of the second input signal terminal out_n+1.
The second pull-down control module 805 is further electrically connected to the second control signal terminal CNB and the third clock signal terminal CK3, and is configured to provide, under control of the second control signal terminal CNB, a signal of the second power signal terminal VG to the pull-down node PD based on a signal of the third clock signal terminal CK 3.
The second pull-down control module 805 may raise the potential of the pull-down node PD during the reset phase to turn on the first pull-down module 804 to enable noise reduction and reset of the output.
In an alternative implementation manner, as shown in fig. 9, the shift register provided in the embodiment of the present application further includes: a second pull-down module 807.
The second pull-down module 807 is electrically connected to the pull-down node PD, the first pull-up node PUCN, and the first power signal terminal VGL, respectively; the second pull-down module 807 is configured to supply the signal of the first power supply signal terminal VGL to the first pull-up node PUCN under the control of the potential of the pull-down node PD.
The second pull-down module 807 may pull the potential of the first pull-up node PUCN low.
In an alternative implementation manner, as shown in fig. 9, the shift register provided in the embodiment of the present application further includes: a second output module 808.
The second output module 808 is electrically connected to the Touch signal end en_touch, the first power signal end VGL, and the output end, respectively; the second output module 808 is configured to provide the signal of the first power signal terminal VGL to the output terminal out_n under the control of the signal of the Touch signal terminal en_touch.
The second output module 808 can output signals in a Touch stage, and in the Touch stage, the signals of the Touch signal terminal en_touch are at a high level, and the internal circuit of the second output module 808 is turned on, so that the signals of the first power signal terminal VGL can be output to the output terminal out_n. The touch stage may be one of the output display stages of the shift register, or one of the non-display stages (e.g., the precharge stage or the reset stage) other than the output display stage, and when the touch stage is one of the output display stages and the signal of the first power signal terminal VGL is at a low level, the output terminal out_n outputs a low level, and the shift register pauses driving the pixel, and the pixel connected to the shift register can pause displaying.
In an alternative implementation manner, as shown in fig. 9, the shift register provided in the embodiment of the present application further includes: reset module 809.
The RESET module 809 is electrically connected with the RESET signal end RESET, the first power signal end VGL and the first pull-up node PUCN respectively; the RESET module 809 is configured to RESET the potential of the first pull-up node PDCN based on the signal of the first power signal terminal VGL under control of the signal of the RESET signal terminal RESET.
Fig. 10 is a schematic circuit diagram of an alternative implementation manner of the shift register provided in the embodiment of the present application, fig. 10 is only used as an example, and it will be understood by those skilled in the art that in other implementations other than fig. 10, the structure of each module may be the same as or different from that of the same module in fig. 10 according to actual needs, and the functions of each module may be implemented.
The following describes the modules in the embodiment of the present application with reference to fig. 10:
optionally, the first input module 801 includes a first switch unit T1, where a control terminal, a first terminal, and a second terminal of the first switch unit T1 are electrically connected to the first input signal terminal out_n-1, the first control signal terminal CN, and the first pull-up node PUCN, respectively, and configured to provide a signal of the first control signal terminal CN to the first pull-up node PUCN under control of a signal of the first input signal terminal out_n-1.
Optionally, the first pull-down control module 802 includes: a second switching unit T2 and a third switching unit T3.
The control end, the first end and the second end of the second switch unit T2 are respectively and electrically connected with the first pull-up node PUCN, the first power signal end VGL and the pull-down node PD; the second switching unit T2 is configured to supply the signal of the first power signal terminal VGL to the pull-down node PD under the control of the potential of the first pull-up node PUCN.
The control terminal, the first terminal, and the second terminal of the third switch unit T3 are electrically connected to the first input signal terminal out_n-1, the first power signal terminal, and the pull-down node PD, respectively, and the third switch unit T3 is configured to provide a signal of the first power signal terminal VGL to the pull-down node PD under control of a signal of the first input signal terminal out_n-1.
The third switch unit T3 in the first pull-down control module 802 can pull the potential of the pull-down node PD low enough under the control of the high level signal of the first input signal terminal out_n-1 to close the first pull-down module 804.
In an alternative embodiment, the first output module 803 includes: a fourth switching unit T4, a fifth switching unit T5, and a first storage unit C1.
The control end, the first end and the second end of the fourth switch unit T4 are respectively and electrically connected with the second power supply signal end VG, the second pull-up node PU and the control end of the output unit; the fourth switch unit T4 is configured to be turned on or off under the control of the second power signal terminal VG, so that the second pull-up node PU discharges when the fourth switch unit T4 is turned on, and stops discharging when the fourth switch unit T4 is turned off.
According to the different working stages of the shift register, the second power signal end VG may be at a high level or a low level, for example, in the touch stage, the second power signal end VG may be at a low level, at this time, the fourth switch unit T4 is turned off, the second pull-up node PU may keep the current potential without leakage through the fourth switch unit T4, and the occurrence probability of the problem that the output voltage of the shift register to be started after the touch stage is ended is insufficient, thereby causing insufficient charging of pixels and abnormal display can be reduced.
The control end, the first end and the second end of the fifth switch unit T5 are respectively and electrically connected with the second pull-up node PU, the first clock signal end CK1 and the output end; the fifth switching unit T5 is for supplying the signal of the first clock signal terminal CK1 to the output terminal out_n under the control of the potential of the second pull-up node PU.
The two ends of the first memory cell C1 are respectively electrically connected to the second pull-up node PU and the output terminal, and the first memory cell C1 is configured to raise the potential of the second pull-up node PU.
In an example, the first memory cell C1 may store charges during the precharge phase to control the fifth switch unit T5 to be turned on, and under the condition that the fifth switch unit T5 is turned on and the first clock signal terminal CK1 is at a high level, the first memory cell C1 may generate a bootstrap effect to further raise the potential of the second pull-up node PU, so as to ensure that the fifth switch unit T5 can sufficiently output the signal of the first clock signal terminal CK1 to the output terminal out_n.
In another alternative embodiment, the first output module 803 includes: a fifth switching unit T5 and a first storage unit C1.
The control end, the first end and the second end of the fifth switch unit T5 are respectively and electrically connected with the second pull-up node PU, the first clock signal end CK1 and the output end; the fifth switching unit T5 is for supplying the signal of the first clock signal terminal CK1 to the output terminal out_n under the control of the potential of the second pull-up node PU.
The two ends of the first memory cell C1 are respectively electrically connected to the second pull-up node PU and the output terminal, and the first memory cell C1 is configured to raise the potential of the second pull-up node PU.
The second pull-up node PU is directly electrically connected to the first pull-up node PUCN, i.e. the second pull-up node PU and the first pull-up node PUCN may be the same node at this time.
In an alternative embodiment, the first pull-down module 804 includes: a sixth switching unit T6 and a second storage unit C2.
The control end, the first end and the second end of the sixth switch unit T6 are respectively and electrically connected with the pull-down node PD, the output end OUT_N and the first power supply signal end VGL; the sixth switching unit T6 is configured to pull down the potential of the output terminal to the potential of the first power signal terminal VGL under the control of the potential of the pull-down node PD.
Both ends of the second memory cell C2 are electrically connected to the pull-down node PD and the first power signal terminal VGL, respectively, and the second memory cell C2 is configured to store charges and maintain the potential of the pull-down node PD stable.
In another alternative embodiment, the first pull-down module 804 includes: and a sixth switching unit T6. The control end, the first end and the second end of the sixth switch unit T6 are respectively and electrically connected with the pull-down node PD, the output end OUT_N and the first power supply signal end VGL; the sixth switching unit T6 is configured to pull down the potential of the output terminal to the potential of the first power signal terminal VGL under the control of the potential of the pull-down node PD.
In an alternative embodiment, the second pull-down control module 805 includes: a seventh switching unit T7 and an eighth switching unit T8.
The control end, the first end and the second end of the seventh switch unit T7 are respectively and electrically connected with the first control signal end CN, the second clock signal end CK2 and the control end of the eighth switch unit T8; the seventh switching unit T7 is configured to provide the signal of the second clock signal terminal CK2 to the control terminal of the eighth switching unit T8 under the control of the first control signal terminal CN.
The first end and the second end of the eighth switch unit T8 are respectively and electrically connected with the second power supply signal end VG and the pull-down node PD; the eighth switching unit T8 is configured to supply the signal of the second power signal terminal VG to the pull-down node PD under the control of the signal of the second clock signal terminal CK 2.
Optionally, the second input module 806 includes a tenth switch unit T10, where a control terminal, a first terminal, and a second terminal of the tenth switch unit are electrically connected to the second input signal terminal out_n+1, the second control signal terminal CNB, and the first pull-up node PUCN, respectively, and configured to provide a signal of the second control signal terminal CNB to the first pull-up node PUCN under control of a signal of the second input signal terminal out_n+1.
The second input module 806 may be connected to a reverse scan control signal to implement bidirectional scanning of the shift register.
In another alternative embodiment, the second pull-down control module 805 further comprises: and a ninth switching unit T9.
The control end, the first end and the second end of the ninth switch unit T9 are respectively and electrically connected with the control ends of the second control signal end CNB, the third clock signal end CK3 and the eighth switch unit T8; the ninth switching unit T9 is configured to provide the signal of the third clock signal terminal CK3 to the control terminal of the eighth switching unit T8 under the control of the second control signal terminal CNB.
The eighth switching unit T8 is further configured to supply the signal of the second power signal terminal VG to the pull-down node PD under the control of the signal of the third clock signal terminal CK 3.
The seventh switch unit T7 (or the ninth switch unit T9) in the second pull-down control module 805 may output the signal of the second clock signal terminal CK2 (or the third clock signal terminal CK 3) under the control of the first control signal terminal CN (or the second control signal terminal CNB) to control the on-off of the eighth switch unit T8, and the eighth switch unit T8 may not be turned on simultaneously with the second switch unit T2 in the first pull-down control module 802 under the common control of the signal of the first control signal terminal CN (or the second control signal terminal CNB) and the signal of the second clock signal terminal CK2 (or the third clock signal terminal CK 3), so that a large current path is not formed between the second pull-down control module 805 and the first pull-down control module 802, so that the large current of the internal path of the shift register can be reduced, and the power consumption of the shift register can be further reduced.
Optionally, the second pull-down module 807 includes: an eleventh switching unit T11.
The control end, the first end and the second end of the eleventh switch unit T11 are electrically connected with the pull-down node PD, the first pull-up node PUCN and the first power signal end VGL, respectively; the eleventh switching unit T11 is for outputting a signal of the first power signal terminal VGL to the first pull-up node PUCN under control of the potential of the pull-down node PD.
Optionally, the second output module 808 includes: a twelfth switching unit T12.
The control end, the first end and the second end of the twelfth switch unit T12 are respectively and electrically connected with the Touch signal end EN_touch, the first power signal end VGL and the output end; the twelfth switching unit T12 is configured to output the signal of the first power signal terminal VGL to the output terminal out_n when the signal of the Touch signal terminal en_touch is at a high level.
The twelfth switching unit T12 can realize output of a Touch stage, and in the Touch stage, the signal of the Touch signal terminal en_touch is at a high level, and the twelfth switching unit T12 is turned on to output the signal of the first power signal terminal VGL to the output terminal out_n. .
Optionally, the reset module 809 includes: thirteenth switching unit T13.
The control end, the first end and the second end of the thirteenth switch unit T13 are respectively and electrically connected with the RESET signal end RESET, the first power signal end VGL and the first pull-up node PDCN; the thirteenth switching unit T13 is configured to output the signal of the first power signal terminal VGL to the first pull-up node PDCN when the signal of the RESET signal terminal RESET is at a high level.
Each switching unit in the embodiments of the present application may include at least one transistor, and when a certain switching unit includes more than two transistors, the more than two transistors may be connected in series or in parallel according to actual needs, each transistor may be a single-gate transistor or a double-gate transistor, and fig. 3 illustrates a single-gate transistor as an example.
In the embodiments of the present application, each transistor may be a thin film transistor, a field effect transistor, or other devices with the same characteristics, and the source (also referred to as a source electrode) and the drain (also referred to as a drain electrode) of each transistor are symmetrical, so that the source and the drain of each transistor may be interchanged. In this embodiment of the present application, the source electrode is used as the first end of the switching unit, the drain electrode is used as the second end of the switching unit, or the drain electrode may be used as the first end of the switching unit, the source electrode is used as the second end of the switching unit, and the middle end of each transistor is used as the gate electrode (also referred to as the gate electrode) as the control end of the switching unit. The transistors in the embodiments of the present application may be P-type transistors or N-type transistors.
Each memory cell in the embodiments of the present application may include at least one capacitor, and when a certain memory cell includes more than two capacitors, the two capacitors may be connected in series or in parallel according to actual requirements.
The specific working principle of the shift register provided in the embodiments of the present application will be described in detail with reference to the following method embodiments, which are not described herein.
Based on the same inventive concept, the embodiment of the application also provides a gate driving circuit, which comprises M cascaded shift registers, wherein M is an integer greater than 1. Each stage of shift register may be any one of the shift registers provided in the embodiments of the present application. The cascade of M shift registers is as follows:
the control end of the first input module 801 in the 1 st to i st shift registers is electrically connected to the frame trigger signal end STV (as the first input signal end of the 1 st to i st shift registers); the control end of the first input module 801 in the nth shift register is electrically connected with the output end of the N-i pole shift register (used as the first input signal end of the nth shift register); the output terminal out_n (as the first input signal terminal of the n+i-th shift register) in the N-th shift register is electrically connected to the control terminal of the first input module 801 in the n+i-th shift register; wherein i is a positive integer, and N is an integer greater than i.
In an alternative embodiment, the control terminal of the second input module 806 in the M-th to M-i+1-th shift registers is electrically connected to the frame trigger signal terminal STV (as the second input signal terminal of the M-th to M-i+1-th shift registers); the output end of the M-th shift register (used as the second input signal end of the M-i-th shift register) is electrically connected with the control end of the second input module 806 in the M-i-th shift register; the control end of the second input module 806 in the K-th shift register is electrically connected to the output end (serving as the second input information end of the K-th shift register) in the k+i-th shift register; the output terminal of the K-th shift register (which is the second input information terminal of the K-i-th shift register) is electrically connected to the control terminal of the second input module 806 of the K-i-th shift register. K is a positive integer less than M-i+1.
In one example, i is 1, and the cascade relationship of the shift registers can refer to fig. 11, in the first stage shift register (shift register 1 in fig. 11), the first INPUT signal terminal INPUT1 is electrically connected to the frame trigger signal terminal STV, in the second to fifth stage shift registers (shift registers 2 to 5 in fig. 11), the first INPUT signal terminal INPUT1 is electrically connected to the output terminal OUT of the previous stage shift register, and the second INPUT signal terminal INPUT2 is electrically connected to the output terminal OUT of the next stage shift register. Fig. 11 shows only the cascade relationship of the first five shift registers, and in practical application, the cascade relationship of the subsequent shift registers involved can be analogized.
Based on the same inventive concept, the embodiment of the present application also provides a display device, including any one of the gate driving circuits provided in the embodiment of the present application.
The display device provided in the embodiments of the present application may be a liquid crystal display device or an organic light emitting diode display device, for example, the display device may be any product or component with a display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
Based on the same inventive concept, the embodiment of the present application further provides a driving method of a shift register, which is applied to any one of the shift registers provided in the embodiment of the present application, as shown in fig. 12, and the driving method includes:
S1201, during the precharge phase, the first input module 801 in the shift register supplies the signal of the first control signal terminal CN to the first pull-up node PUCN under the control of the signal of the first input signal terminal out_n-1, so that the potential of the first pull-up node PUCN is the first potential; the first pull-down control module 802 in the shift register provides the signal of the first power signal terminal VGL to the pull-down node PD under the control of the first potential of the first pull-up node PUCN and the signal of the first input signal terminal out_n-1, so that the potential of the pull-down node PD is the second potential; the first output module 803 in the shift register outputs a signal of the second potential of the second clock signal terminal CK1 under the control of the potential of the first pull-up node PUCN. Wherein the second potential is lower than the first potential.
In S1202, in the output display stage, the first output module 803 outputs a signal of the third potential of the second clock signal terminal CK 1. Wherein the third potential is higher than the first potential and the second potential.
Optionally, the driving method of the shift register provided in the embodiment of the present application further includes:
in the reset phase, the second pull-down control module 805 of the shift register adjusts the potential of the pull-down node PD to the third potential according to the signal of the second clock signal terminal CK2 or the third clock signal terminal CK3, and the first pull-down module 804 of the shift register provides the signal of the first power signal terminal VGL to the output terminal out_n under the control of the third potential of the pull-down node PD.
Fig. 13 is a schematic signal timing diagram of a driving method of a shift register according to an embodiment of the present application, and the following description is given to the principle of the driving method of a shift register according to an embodiment of the present application by taking the shift register shown in fig. 10 and the signal timing diagram shown in fig. 13 as examples:
in the T1 stage (i.e., the precharge stage), the signal of the second power signal terminal VG and the signal of the first input signal terminal out_n-1 are both at the third potential (first high level), the fourth switching unit T4 and the first switching unit T1 are turned on to charge the first memory cell C1, the potentials of the first pull-up node PUCN and the second pull-up node PU are raised to the first potential (second high level), the second switching unit T2 and the third switching unit T3 are both turned on to pull the potential of the pull-down node PD down to the second potential (low level), the sixth switching unit T6 is turned off, and the fifth switching unit T5 is turned on under the control of the potential of the second pull-up node PU to output the low level signal of the first clock signal CK1 through the output terminal out_n.
In the period T2 (i.e. output display period), the potential of the second pull-up node PU increases under the bootstrap action of the first memory cell C1, the potential of the first pull-up node PUCN is still the second potential, the pull-down node PD still maintains the second potential under the action of the second switching unit T2 and the third switching unit T3, the sixth switching unit T6 maintains the off state under the control of the second potential of the pull-down node PD, and the fifth switching unit T5 is turned on under the control of the increased potential of the second pull-up node PU, and provides the high level signal of the first clock signal terminal CK1 to the output terminal out_n.
In the stage T3 (i.e., reset stage), the signal of the first control signal terminal CN is at a high level, the seventh switching unit T7 is turned on under the control of the high level signal of the first control signal terminal CN, the high level signal of the second clock signal terminal CK2 is output to the control terminal of the eighth switching unit T8, the eighth switching unit T8 is turned on, the high level signal of the second power signal terminal VG is output to the pull-up node PD, the potential of the pull-up node PD is made to be at a third potential, the sixth switching unit T6 is turned on under the control of the third potential, the potential of the output terminal out_n is pulled down, and the output terminal out_n is made to output a low level.
At the stage after t3, the shift register of the present stage still keeps the state of the stage t3 until the shift register of the present stage of the next frame is started.
Referring to the driving principle, when the first switching unit T1 or the second switching unit T2 experiences a characteristic drift, and the potential of the first pull-up node PUCN is not high enough in the stages T1 and T2, and thus the pull-down node PD cannot be pulled low enough by the second switching unit T2, the high-level signal of the first input signal terminal out_n-1 can make the third switching unit T3 pull the pull-down node PD low enough, so that the sixth switching unit T6 is completely turned off, so as to avoid the influence of the sixth switching unit T6 on the output terminal, and thus ensure the normal output of the output terminal out_n.
Fig. 14 shows an output simulation diagram of the shift register provided in the embodiment of the present application when the threshold voltages Vth of the first switch unit T1 and the second switch unit T2 are increased to 10 volts, and fig. 15 shows an output simulation diagram of the shift register provided in the embodiment of the present application when the on-state currents Ion of the first switch unit T1 and the second switch unit T2 are reduced to 1E-6 amps. Referring to fig. 14 and 15, the driving process is not affected by the shift of the threshold voltage Vth and the decrease of the on-state current Ion of the first and second switching units T1 and T2, and the pull-down action of the stable pull-down node PD can be maintained, so that the output terminal out_n can be outputted normally and stably.
During the above operation of the shift register, the switch units between the second clock signal terminal CK2 and the first power signal terminal VGL and between the second power signal terminal VG and the first power signal terminal VGL are not turned on at the same time.
In one example, referring to the circuit principle shown in fig. 10 and the signal timing diagram shown in fig. 13, in the stages T1 and T2, the signal of the first control signal terminal CN is at a high level, the seventh switching unit T7 is turned on, and since the signal of the second clock signal terminal CK2 is at a low level, the eighth switching unit T8 is not turned on; in the stage T3, the signal of the first control signal terminal CN, the signal of the second clock signal terminal CK2 and the signal of the second power signal terminal VG are all at high level, the seventh switching unit T7 is turned on under the control of the signal of the first control signal terminal CN, and then the eighth switching unit T8 is turned on under the control of the signal of the second clock signal terminal CK2 output by the seventh switching unit T7, at this time, PUCN is at low level, and the second switching unit T2 is turned off; the seventh switching unit T7 and the eighth switching unit T8 are not directly electrically connected to the third switching unit T3, the eleventh switching unit T11, the thirteenth switching unit T13, and the like.
Therefore, in the stage t1-t3, no direct current path is formed between the second clock signal end CK2 and the first power signal end VGL and between the second power signal end VG and the first power signal end VGL, so that the generation of large current is effectively avoided, the power consumption of the shift register can be effectively reduced, and the service lives of the shift register, a grid driving circuit, a display device and the like which belong to the shift register are prolonged.
Fig. 16 shows a schematic diagram of an internal current of the shift register provided in the embodiment of the present application when driving scanning, specifically shows a dot current of the second switch unit T2 and the eleventh switch unit T11 in the shift register, where both dot currents are smaller, both are smaller than 5uA (microamperes), and no large current is generated.
Optionally, the driving method of the shift register provided in the embodiment of the present application further includes:
in the RESET phase, the RESET module 809 in the shift register RESETs the potential of the first pull-up node PDCN based on the signal of the first power supply signal terminal VGL under the control of the signal of the RESET signal terminal RESET.
Referring to the example shown in fig. 10, in the T3 stage, the thirteenth switching unit T13 is turned on when the signal of the RESET signal terminal RESET is at the high level, and outputs the signal of the first power signal terminal VGL to the first pull-up node PDCN.
In an optional implementation manner, the driving method of the shift register provided in the embodiment of the present application further includes:
in the case that the shift register includes the second output module 808, in a Touch stage (not shown in fig. 13), the second output module 808 provides the signal of the first power signal terminal VGL to the output terminal under the control of the signal of the Touch signal terminal en_touch.
Referring to the example of fig. 10, in the case where the shift register includes the second output module 808, in the Touch stage, the twelfth switching unit T12 is turned on when the signal of the Touch signal terminal en_touch is at the high level, and outputs the signal of the second potential of the first power signal terminal VGL to the output terminal out_n.
Fig. 13 of the embodiment of the present application is taken as an example, and does not directly represent a touch stage, and it can be understood by those skilled in the art that, according to the actual situation, the touch stage may be any one of the sub-stages in fig. 13, and when a certain sub-stage in fig. 13 is a touch stage, a signal of the second power signal terminal VG of the sub-stage may be a low level.
In another optional implementation manner, the driving method of the shift register provided in the embodiment of the present application further includes:
In the case that the shift register does not include the second output module 808, in the touch stage, the shift register outputs a signal of the second potential based on the signal of the second potential of each signal terminal.
Referring to the example of fig. 10, in the case where the shift register does not include the second output module 808, in the touch stage, the first control signal terminal CN, the first power signal terminal VGL, the second power signal terminal VG, the first clock signal terminal CK1, and the second clock signal terminal CK2 all provide low level signals, and accordingly, the output terminal out_n outputs low level signals.
Fig. 13 of the embodiment of the present application does not directly show, as an example, a case where each signal is at a low level, and those skilled in the art can understand that each signal involved in fig. 13 may be adjusted to be at a low level during the touch stage.
The description of the specific embodiments of the driving method of the shift register described above may be applied to the case of forward scanning, where the driving method is similar to the forward scanning in the case of reverse scanning, and the tenth switching unit T10 replaces the first switching unit T1 to implement the corresponding function in the case of reverse scanning, and the ninth switching unit T9 replaces the seventh switching unit T7 to implement the corresponding function, so that the principles of the other units are the same as those of the downward scanning, and will not be repeated herein.
In this embodiment, each signal refers to a first potential, a second potential, and a third potential, where the first potential, the second potential, and the third potential only represent the potentials of each signal with 3 state quantities, and do not represent specific values.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of various changes or substitutions within the technical scope of the present application, and these should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (14)

1. A shift register, comprising: the device comprises a first input module, a first pull-down control module, a first output module and a first pull-down module;
the first input module is electrically connected with the first input signal end, the first control signal end and the first pull-up node respectively; the first input module is used for providing the signal of the first control signal end for the first pull-up node under the control of the signal of the first input signal end;
the first pull-down control module is electrically connected with the first pull-up node, the first input signal end, the first power signal end and the pull-down node respectively; the first pull-down control module is used for providing the signal of the first power supply signal end for the pull-down node under the control of the first input signal end and the first pull-up node; the first pull-down control module includes: a second switching unit and a third switching unit; the control end, the first end and the second end of the second switch unit are respectively and electrically connected with the first pull-up node, the first power signal end and the pull-down node; the control end, the first end and the second end of the third switch unit are respectively and electrically connected with the first input signal end, the first power signal end and the pull-down node;
The first output module is respectively and electrically connected with the first pull-up node, the first clock signal end and the output end; the first output module is used for providing the signal of the first clock signal end for the output end under the control of the potential of the first pull-up node so that the output end outputs the signal of the first clock signal end;
the first pull-down module is respectively and electrically connected with the pull-down node, the first power signal end and the output end; the first pull-down module is used for providing the potential of the first power supply signal end for the output end under the control of the potential of the pull-down node.
2. The shift register of claim 1, further comprising: a second pull-down control module;
the second pull-down control module is respectively and electrically connected with the first control signal end, the second clock signal end, the second power signal end and the pull-down node;
the second pull-down control module is configured to provide the signal of the second power supply signal terminal to the pull-down node based on the signal of the second clock signal terminal under the control of the first control signal terminal.
3. The shift register of claim 2, wherein the second pull-down control module comprises: a seventh switching unit and an eighth switching unit;
The control end, the first end and the second end of the seventh switch unit are respectively and electrically connected with the first control signal end, the second clock signal end and the control end of the eighth switch unit;
the first end and the second end of the eighth switch unit are respectively and electrically connected with the second power supply signal end and the pull-down node.
4. A shift register as claimed in claim 3, further comprising: a second input module;
the second input module is electrically connected with the second input signal end, the second control signal end and the first pull-up node respectively; the second input module is configured to provide the signal of the second control signal end to the first pull-up node under the control of the signal of the second input signal end;
the second pull-down control module further includes: a ninth switching unit;
and the control end, the first end and the second end of the ninth switch unit are respectively and electrically connected with the second control signal end, the third clock signal end and the control end of the eighth switch unit.
5. The shift register of claim 1, further comprising: a second pull-down module;
the second pull-down module is electrically connected with the pull-down node, the first pull-up node and the first power signal end;
The second pull-down module is used for providing the signal of the first power supply signal end for the first pull-up node under the control of the potential of the pull-down node.
6. The shift register of claim 1, wherein the first output module comprises: a fourth switching unit, a fifth switching unit, and a first storage unit;
the control end, the first end and the second end of the fourth switch unit are respectively and electrically connected with the second power supply signal end, the second pull-up node and the control end of the fifth switch unit;
the control end, the first end and the second end of the fifth switch unit are respectively and electrically connected with the second pull-up node, the first clock signal end and the output end;
and two ends of the first storage unit are respectively and electrically connected with the second pull-up node and the output end.
7. The shift register of claim 1, wherein the first pull-down module comprises: a sixth switching unit and a second storage unit;
the control end, the first end and the second end of the sixth switch unit are respectively and electrically connected with the pull-down node, the output end and the first power supply signal end;
and two ends of the second storage unit are respectively and electrically connected with the pull-down node and the first power signal end.
8. The shift register of claim 1, further comprising: a second output module;
the second output module is respectively and electrically connected with the touch signal end, the first power signal end and the output end;
the second output module is used for providing the signal of the first power supply signal end for the output end under the control of the signal of the touch signal end.
9. A gate drive circuit comprising M cascaded shift registers according to any one of claims 1-8, M being an integer greater than 1;
the control end of the first input module in the 1 st-i st shift register is electrically connected with the frame trigger signal end STV;
the control end of the first input module in the N-th level shift register is electrically connected with the output end of the N-i-th level shift register;
the output end of the N-th shift register is electrically connected with the control end of the first input module in the (n+i) -th shift register;
i is a positive integer and N is an integer greater than i.
10. The gate driving circuit according to claim 9, wherein,
the control end of the second input module in the M-th to M-i+1-th shift registers is electrically connected with the frame trigger signal end;
The output end of the M-th shift register is electrically connected with the control end of the second input module in the M-i-th shift register;
the control end of the second input module in the K-stage shift register is electrically connected with the output end in the K+i-stage shift register;
the output end of the K-stage shift register is electrically connected with the control end of the second input module in the K-i-stage shift register;
k is a positive integer less than M-i+1.
11. A display device comprising the gate driving circuit according to claim 9 or 10.
12. A shift register driving method applied to the shift register according to any one of claims 1 to 8, comprising:
in a precharge stage, a first input module in the shift register provides a signal of a first control signal end for a first pull-up node under the control of a signal of a first input signal end, so that the potential of the first pull-up node is a first potential;
a first pull-down control module in the shift register provides a signal of a first power supply signal end for the pull-down node under the control of the first potential of the first pull-up node and the signal of the first input signal end, so that the potential of the pull-down node is a second potential; the second potential is lower than the first potential;
A first output module in the shift register outputs a signal of a second potential of a second clock signal end under the control of the potential of the first pull-up node;
in the output display stage, the first output module outputs a signal of a third potential of the second clock signal end; the third potential is higher than the first potential and the second potential.
13. The driving method of a shift register according to claim 12, further comprising:
in the reset stage, the second pull-down control module of the shift register adjusts the potential of the pull-down node to the third potential according to the signal of the second clock signal end, and the first pull-down module of the shift register provides the signal of the first power supply signal end to the output end under the control of the third potential of the pull-down node.
14. The driving method of a shift register according to claim 12 or 13, characterized by further comprising:
in the touch stage, the second output module of the shift register provides the signal of the second potential of the first power supply signal end to the output end under the control of the signal of the touch signal end.
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CN111429830A (en) * 2020-04-23 2020-07-17 合肥京东方卓印科技有限公司 Shifting register unit and driving method thereof, grid driving circuit and display panel

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