CN108154836A

CN108154836A - A kind of shift register cell and its driving method, gate driving circuit

Info

Publication number: CN108154836A
Application number: CN201810003605.4A
Authority: CN
Inventors: 古宏刚; 邵贤杰; 宋洁
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Priority date: 2018-01-03
Filing date: 2018-01-03
Publication date: 2018-06-12
Anticipated expiration: 2038-01-03
Also published as: CN108154836B

Abstract

The present invention discloses a kind of shift register cell and its driving method, gate driving circuit, is related to display technology field, to solve the problems, such as that existing gate driving circuit can not meet the narrow frame demand of display device.The shift register cell includes N number of output module, wherein the n-th output module is used under the control of the n-th clock signal input terminal and pull-up node, the second end whether the n-th gate drive signal output terminal connect and controlled the n-th gate drive signal output terminal and capacitance module with the n-th clock signal input terminal is controlled whether to connect；It is additionally operable under the control of the n-th reset terminal, controls whether the second end of the n-th gate drive signal output terminal and capacitance module connects and control whether the n-th gate drive signal output terminal connect with the first level input；N is the positive integer less than or equal to N.Shift register cell provided by the invention is used to provide gate drive signal.

Description

A kind of shift register cell and its driving method, gate driving circuit

Technical field

The present invention relates to display technology fields more particularly to a kind of shift register cell and its driving method, grid to drive Dynamic circuit.

Background technology

With the continuous development of display technology, more and more display devices drive (Gate On using array substrate row Array, hereinafter referred to as GOA) technology, this GOA technologies are that gate driving circuit directly is integrated in the non-display of array substrate On region, the border width of array substrate is largely reduced.The gate driving circuit packet being integrated in array substrate Include several shift register cells, a grid line on each shift register cell corresponding array substrate, and pass through output Gate drive signal realizes the driving to this grid line.

Traditional shift register cell generally comprises input module, energy-storage module, output module and reseting module, this The course of work of shift register cell is：In the input period, input module is by the voltage high of pull-up node；In output Section, under the action of energy-storage module, output module output gate drive signal；The period is being resetted, reseting module is by pull-up node Voltage and gate drive signal be reset to gate off voltage；Kept for the period, the output terminal of output module can have been at Suspended state, and keep gate off voltage.Since each grid line in array substrate is required to a corresponding shift LD Device unit, and each shift register cell is required to include input module, energy-storage module, output module and reseting module, makes It obtains the gate driving circuit set in array substrate and includes excessive device, and the narrow frame demand of display device can not be met

Invention content

The purpose of the present invention is to provide a kind of shift register cell and its driving method, gate driving circuits, are used for Solve the problems, such as that gate driving circuit of the prior art can not meet the narrow frame demand of display device.

To achieve these goals, the present invention provides following technical solution：

The first aspect of the present invention provides a kind of shift register cell, including：

Pull-up node control module, respectively with input control end, power supply signal input, pull-up node, N reset terminals and First level input connects；

Pull-down node control module, respectively with the pull-up node, second electrical level input terminal, first level input It is connected with the pull-down node；

Capacitance module, the first end of the capacitance module are connect with the pull-up node；

N number of output module, N are the integer more than 1, wherein,

N-th output module respectively with the n-th clock signal input terminal, the pull-up node, the second end of the capacitance module, N-th gate drive signal output terminal, first level input and the connection of the n-th reset terminal；N-th output module is used for： Under the control of n-th clock signal input terminal and the pull-up node, control the n-th gate drive signal output terminal with Whether n-th clock signal input terminal connects and controls the n-th gate drive signal output terminal and the capacitance module Second end whether connect；N-th output module is additionally operable to：Under the control of n-th reset terminal, n-th grid are controlled Whether pole driving signal output end connect and controls n-th gate drive signal defeated with the second end of the capacitance module Whether outlet connect with first level input；N is the positive integer less than or equal to N.

Further, the shift register cell further includes：N number of output control module, wherein,

N-th output control module respectively with the (n+1)th clock signal input terminal, n-th output module and it is described first electricity The connection of flat input terminal, under the control of (n+1)th clock signal input terminal, by control n-th output module with Whether first level input connects, n-th output module to be caused to control the n-th gate drive signal output terminal Whether it is connect with n-th clock signal input terminal.

Further, the shift register cell further includes：Node discharge module and N number of output terminal discharge module, In,

The node discharge module connects respectively with the pull-down node, the pull-up node and first level input It connects, under the control of the pull-down node, controlling whether the pull-up node connect with first level input；

N-th output terminal discharge module respectively with the pull-down node, the n-th gate drive signal output terminal and described One level input connects, under the control of the pull-down node, controlling the n-th gate drive signal output terminal and institute State whether the first level input connects.

Further, the pull-up node control module is used under the control at the input control end, controls the electricity Whether source signal input terminal connect with the pull-up node, is additionally operable under the control of the N reset terminals, controls the pull-up Whether node connect with first level input；

The pull-down node control module is used under the control of the second electrical level input terminal and the pull-up node, control It makes whether the pull-down node connect with the second electrical level input terminal, is additionally operable under the control of the pull-up node, control Whether the pull-down node connect with first level input.

Further, n-th output module includes：

First switch pipe, the grid of the first switch pipe are connect with n-th clock signal input terminal, and described first opens The first pole for closing pipe is connect with the pull-up node；

Second switch pipe, the grid of the second switch pipe are connect with the second pole of the first switch pipe, and described second First pole of switching tube is connect with n-th clock signal input terminal, the second pole of the second switch pipe and n-th grid Driving signal output end connects；

Third switching tube, the grid of the third switching tube are connect with the second pole of the second switch pipe, the third First pole of switching tube is connect with the second end of the capacitance module, the second pole of the third switching tube and n-th grid Driving signal output end connects；

4th switching tube, the grid of the 4th switching tube are connect with n-th reset terminal, and the of the 4th switching tube One pole is connect with the n-th gate drive signal output terminal, and the second pole and first level of the 4th switching tube input End connection.

Further, n-th output control module includes：

5th switching tube, the grid of the 5th switching tube are connect with (n+1)th clock signal input terminal, and the described 5th First pole of switching tube is connect with the grid of the second switch pipe, the second pole and first level of the 5th switching tube Input terminal connects.

Further, the node discharge module includes：

6th switching tube, the grid of the 6th switching tube are connect with the pull-down node, and the of the 6th switching tube One pole is connect with the pull-up node, and the second pole of the 6th switching tube is connect with first level input；

The n-th output terminal discharge module includes：

7th switching tube, the grid of the 7th switching tube are connect with the pull-down node, and the of the 7th switching tube One pole is connect with the n-th gate drive signal output terminal, and the second pole and first level of the 7th switching tube input End connection.

Further, the pull-up node control module includes：

8th switching tube, the grid of the 8th switching tube are connect with the input control end, the 8th switching tube First pole is connect with the power supply signal input, and the second pole of the 8th switching tube is connect with the pull-up node；

9th switching tube, the grid of the 9th switching tube are connect with the N reset terminals, and the of the 9th switching tube One pole is connect with the pull-up node, and the second pole of the 9th switching tube is connect with first level input；

The pull-down node control module includes：

Tenth switching tube, the grid of the tenth switching tube and the first of the tenth switching tube extremely with described second electricity Flat input terminal connection；

11st switching tube, the grid of the 11st switching tube is connect with the second pole of the tenth switching tube, described First pole of the 11st switching tube is connect with the second electrical level input terminal, the second pole of the 11st switching tube with it is described under Draw node connection；

12nd switching tube, the grid of the 12nd switching tube are connect with the pull-up node, the 12nd switch First pole of pipe is connect with the pull-down node, and the second pole and first level input of the 12nd switching tube connect It connects；

13rd switching tube, the grid of the 13rd switching tube are connect with the pull-up node, the 13rd switch First pole of pipe is connect with the grid of the 11st switching tube, the second pole and first level of the 13rd switching tube Input terminal connects.

Based on the technical solution of above-mentioned shift register cell, the second aspect of the present invention provides a kind of gate driving electricity Road, including above-mentioned shift register cell.

Based on the technical solution of above-mentioned shift register cell, the third aspect of the present invention provides a kind of shift register list The driving method of member, applied to above-mentioned shift register cell, the driving method includes：

The period is inputted, under the control at the input control end, the pull-up node control module controls the power supply letter Number input terminal is connect with the pull-up node；

N number of output period, wherein,

In the n-th output period, under the control of n-th clock signal input terminal and the pull-up node, described n-th Output module controls the n-th gate drive signal output terminal to be connect with n-th clock signal input terminal, control described n-th Gate drive signal output terminal is connect with the second end of the capacitance module；Under the control of the (n-1)th reset terminal, the (n-1)th output Module controls the (n-1)th gate drive signal output terminal to be connect with first level input, and control (n-1)th grid Pole driving signal output end and the second end of the capacitance module are not connected to；

The period is being resetted, under the control of the N reset terminals, the N output modules control the N gate drivings Signal output end is connect with first level input, and controls the N gate drive signals output terminal and the capacitance The second end of module is not connected to；Under the control of the N reset terminals, the pull-up node control module control pull-up section Point is connect with first level input；

Kept for period, under the control of the second electrical level input terminal and the pull-up node, the pull-down node control Molding block controls the pull-down node to be connect with the second electrical level input terminal, controls the pull-down node and first level Input terminal is not connected to.

Further, when the shift register cell further includes N number of output control module, the driving method also wraps It includes：

In the described n-th output period, under the control of n-th clock signal input terminal, the (n-1)th output control module By the way that (n-1)th output module is controlled to be connect with first level input, to cause the n-th output module control institute The (n-1)th gate drive signal output terminal is stated to be not connected to (n-1)th clock signal input terminal；

In the reset period, under the control of the N+1 clock signal input terminals, N output control modules lead to It crosses and the N output modules is controlled to be connect with first level input, to control the N gate drive signal output terminals It is not connected to the N clock signal input terminals.

Further, when the shift register cell further includes node discharge module and N number of output terminal discharge module, The driving method further includes：

In the reset period and the holding period, under the control of the pull-down node, the node discharge module The pull-up node is controlled to be connect with first level input；Under the control of the pull-down node, n-th output terminal Discharge module controls the n-th gate drive signal output terminal to be connect with first level input.

In technical solution provided by the invention, mould is controlled by the way that multiple output modules is set to share same pull-up node Block, pull-down node control module, capacitance module, pull-up node and pull-down node, and with reference to timing control, in different output Section controls corresponding output module output gate drive signal, realize a shift register cell can timesharing output it is more Therefore a gate drive signal, when forming gate driving circuit using shift register cell provided by the invention, reduces grid The quantity of the required thin film transistor (TFT) of pole driving circuit, so as to reduce the production cost of power consumption and gate driving circuit, Improve production yield.Moreover, because the negligible amounts of the required thin film transistor (TFT) of gate driving circuit so that by the grid When in the display device of pole driving circuit application, the design requirement of the narrow frame of display device is met well.

Description of the drawings

Attached drawing described herein is used to provide further understanding of the present invention, and forms the part of the present invention, this hair Bright illustrative embodiments and their description do not constitute improper limitations of the present invention for explaining the present invention.In the accompanying drawings：

Fig. 1 is the module diagram of shift register cell provided in an embodiment of the present invention；

Fig. 2 is the working timing figure of shift register cell provided in an embodiment of the present invention；

Fig. 3 is the first schematic diagram of shift register cell provided in an embodiment of the present invention；

Fig. 4 is the first schematic diagram of shift register cell provided in an embodiment of the present invention；

Fig. 5 is the structure diagram of gate driving circuit provided in an embodiment of the present invention.

Reference numeral：

1- pull-up node control modules, 2- pull-down node control modules,

The first output modules of 31-, the second output modules of 32-,

33- third output modules, the 4th output modules of 34-,

41 first output control modules, the second output control modules of 42-,

51- node discharge modules, 52- the first output terminal discharge modules,

53- second output terminal discharge modules, 6- capacitance modules,

The first shift register cells of 71-, the second shift register cells of 72-,

INPUT- input controls end, PD- pull-down nodes,

PU- pull-up nodes, the first reset terminals of RESET1-,

The second reset terminals of RESET2-, RESET3- third reset terminals,

The 4th reset terminals of RESET4-, the first level inputs of VGL-,

VGH- second electrical level input terminals, VDD- power supply signal inputs,

The first clock signal input terminals of CLK1-, CLK2- second clock signal input parts,

CLK3- third clock signal input terminals, the P1- input periods,

P21- first exports the period, and P22- second exports the period,

P3- resets the period, and P4- is kept for the period,

OUTPUT1- first gate driving signal output terminals, OUTPUT2- second grid driving signal output ends,

OUTPUT3- third gate drive signal output terminals, the 4th gate drive signal output terminals of OUTPUT4-,

The first capacitances of C1-, T1- first switch pipes,

T2- second switch pipes, T3- third switching tubes,

The 4th switching tubes of T4-, the 5th switching tubes of T5-,

The 6th switching tubes of T6-, the 7th switching tubes of T7-,

The 8th switching tubes of T8-, the 9th switching tubes of T9-,

The tenth switching tubes of T10-, the 11st switching tubes of T11-,

The 12nd switching tubes of T12-, the 13rd switching tubes of T13-,

STV- start frame signal output ends.

Specific embodiment

The shift register cell and its driving method, gate driving that embodiment provides in order to further illustrate the present invention are electric Road is described in detail with reference to the accompanying drawings of the specification.

Referring to Fig. 1, shift register cell provided in an embodiment of the present invention includes：Pull-up node control module 1, drop-down Node control module 2, capacitance module 6 and N number of output module.

Specifically, pull-up node control module 1 respectively with input control end INPUT, power supply signal input VDD, pull-up Node PU, N reset terminals and the first level input VGL connections；Pull-down node control module 2 respectively with pull-up node PU, Two level input VGH, the first level input VGL are connected with pull-down node PD；The first end and pull-up node of capacitance module 6 PU connections；For N number of output module, N is the integer more than 1, and wherein the n-th output module respectively with the n-th clock signal input End, pull-up node PU, the second end of capacitance module 6, the n-th gate drive signal output terminal, the first level input VGL and n-th Reset terminal connects；N-th output module is used for：Under the control of the n-th clock signal input terminal and pull-up node PU, the n-th grid are controlled Whether pole driving signal output end connect and controls the n-th gate drive signal output terminal and electricity with the n-th clock signal input terminal Whether the second end of molar block 6 connects；N-th output module is additionally operable to：Under the control of the n-th reset terminal, the n-th gate driving is controlled Whether signal output end connect with the first level input VGL；N is the positive integer less than or equal to N.

Referring to Fig. 2, above-mentioned shift register cell, in actual work, including multiple work periods, each works Period includes successively：Period P1, N number of output period are inputted, period P3 is resetted and keeps period P4.

In input period P1, under the control of input control end INPUT, pull-up node control module 1 controls power supply signal Input terminal VDD is connect with pull-up node PU, and the current potential of pull-up node PU is drawn high；Under the control of pull-up node PU, drop-down section Point control module 2 controls pull-down node PD and the first level input VGL connections.

In N number of output period, wherein,

In the first output period P21, under the control of the first clock signal input terminal CLK1 and pull-up node PU, first Output module 31 controls first gate driving signal output terminal OUTPUT1 to be connect, and control with the first clock signal input terminal CLK1 First gate driving signal output terminal OUTPUT1 processed is connect with the second end of capacitance module 6, exports first gate driving signal OUTPUT1 output first gate driving signals are held, and the current potential of pull-up node PU is further pulled up；

When n is more than 1, in the n-th output period, under the control of the n-th clock signal input terminal and pull-up node PU, the N output modules control the n-th gate drive signal output terminal to be connect with the n-th clock signal input terminal, control the n-th gate drive signal Output terminal is connect with the second end of capacitance module 6, the n-th gate drive signal output terminal is made to export the n-th gate drive signal, and protect Hold the current potential of pull-up node PU；Under the control of the (n-1)th reset terminal, the (n-1)th output module controls the (n-1)th gate drive signal defeated Outlet and the second end of capacitance module 6 are not connected to, and control the (n-1)th gate drive signal output terminal and the first level input VGL connections drag down the current potential of the (n-1)th gate drive signal output terminal；Under the control of pull-up node PU, pull-down node control Module 2 continues to control pull-down node PD and the first level input VGL connections.

Period P3 is being resetted, under the control of N reset terminals, N output modules control N gate drive signal output terminals It is connect with the first level input VGL, and controls the second end of N gate drive signals output terminal and the capacitance module 6 not Connection, so as to which the current potential of N gate drive signal output terminals be dragged down；Under the control of N reset terminals, pull-up node control mould Block 1 controls pull-up node PU to be connect with the first level input VGL, and the current potential of pull-up node PU is dragged down；In high level signal Under the control of the pull-up node PU of input terminal and low potential, pull-down node control module 2 controls pull-down node PD and second electrical level Input terminal VGH connections, control pull-down node PD and the first level input VGL are not connected to, thus by the current potential of pull-down node PD It draws high；

Keeping period P4, under the control of second electrical level input terminal VGH and the pull-up node PU of low potential, pull-down node Control module 2 continues that pull-down node PD is controlled to connect with second electrical level input terminal VGH, controls pull-down node PD and the first level defeated Enter VGL is held to be not connected to, the current potential of pull-down node PD is maintained at high potential.

It is worth noting that, above-mentioned first level input VGL is chosen as low-level input, above-mentioned second electrical level input End VGH is chosen as high level input terminal, but be not limited only to this.

With reference to above-described embodiment provide shift register cell structure and specific work process it is found that the present invention implement In the shift register cell that example provides, including pull-up node control module 1, pull-down node control module 2, capacitance module 6 and N A output module, and each work period of the shift register cell successively include input period P1, N number of output when Section resets period P3 and keeps period P4.

Specifically, period P21 is exported first, the first output module 31 can control first gate driving signal output terminal OUTPUT1 is connect with the first clock signal input terminal CLK1, and controls first gate driving signal output terminal OUTPUT1 and capacitance The second end connection of module 6, makes first gate driving signal output terminal OUTPUT1 export first gate driving signal；When n is more than When 1, the period is exported n-th, the n-th output module can control the n-th gate drive signal output terminal and the n-th clock signal input terminal Connection, and the n-th gate drive signal output terminal is controlled to be connect with the second end of capacitance module 6, export the n-th gate drive signal The n-th gate drive signal of end output, meanwhile, under the control of the (n-1)th reset terminal, the (n-1)th output module controls the (n-1)th grid to drive The second end of dynamic signal output end and capacitance module 6 is not connected to, and controls the (n-1)th gate drive signal output terminal and the first level Input terminal VGL connections ensure that, in the n-th output period, only the n-th gate drive signal output terminal can export the drive of the n-th grid Dynamic signal.

As it can be seen that in above-mentioned shift register cell, N number of output period corresponds with N number of output module, defeated at each Go out the period, one and only one output module corresponds to output gate drive signal.

Therefore, in compared with the prior art, each shift register cell only includes an output module, only can be defeated Go out for drive a grid line gate drive signal structure, in shift register cell provided in an embodiment of the present invention, lead to Cross set multiple output modules share same pull-up node control module 1, pull-down node control module 2, capacitance module 6, on Node PU and pull-down node PD is drawn, and with reference to timing control, in the different output periods, controls corresponding output module output grid Pole drive signal, realize a shift register cell can timesharing export multiple gate drive signals, therefore, utilize this hair When the shift register cell that bright embodiment provides forms gate driving circuit, reduce the required film of gate driving circuit The quantity of transistor so as to reduce the production cost of power consumption and gate driving circuit, improves production yield.Moreover, by In the negligible amounts of the required thin film transistor (TFT) of gate driving circuit so that in the display dress for applying the gate driving circuit When putting middle, the design requirement of the narrow frame of display device is met well.

Please continue to refer to Fig. 1 and Fig. 2, the shift register cell that above-described embodiment provides further includes：With N number of output module One-to-one N number of output control module, wherein, the n-th output control module respectively with the (n+1)th clock signal input terminal, n-th defeated Go out module to connect with the first level input VGL, it is defeated by control n-th under the control of the (n+1)th clock signal input terminal Go out whether module connect with the first level input VGL, n-th output module to be caused to control the n-th gate drive signal defeated Whether outlet connect with the n-th clock signal input terminal.

Specifically, in the n-th output period, under the control of the n-th clock signal input terminal, the (n-1)th output control module By control the (n-1)th output module connect with the first level input VGL, come control the (n-1)th gate drive signal output terminal and (n-1)th clock signal input terminal is not connected to；In period P3 is resetted, under the control of N+1 clock signal input terminals, N is defeated Go out control module by the way that N output modules is controlled to be connect with the first level input VGL, to control N gate drive signals defeated Outlet is not connected to N clock signal input terminals.

In N number of output control module included by above-mentioned shift register cell, the (n-1)th output control module can be When n gate drive signals output terminal exports the n-th gate drive signal, by the way that the (n-1)th output module and the first level is controlled to input VGL connections are held, the (n-1)th gate drive signal output terminal and the (n-1)th clock signal input terminal to be controlled to be not connected to so that n-th The period is exported, the (n-1)th gate drive signal output terminal can connect only under the control of the (n-1)th reset terminal with low potential input terminal It connects, so that the (n-1)th gate drive signal output terminal is stable low potential in the n-th output period, avoids it to the n-th grid The output of pole driving signal output end has an impact.

N output control modules can reset period P3, by controlling N output modules and the first level input VGL connections, N gate drive signals output terminal and N clock signal input terminals to be controlled to be not connected to；So that when resetting Section P3, N gate drive signals output terminal can be connect only under the control of N reset terminals with low potential input terminal, so as to make It is stable low potential that N gate drive signals output terminal, which is obtained, resetting period P3, ensure that shift register cell work Stability.

Please continue to refer to Fig. 1 and Fig. 2, the shift register cell that above-described embodiment provides further includes node discharge module 51 With N number of output terminal discharge module, wherein, node discharge module 51 respectively with pull-down node PD, pull-up node PU and the first level Input terminal VGL connections, under the control of pull-down node PD, whether control pull-up node PU and the first level input VGL Connection；N-th output terminal discharge module respectively with pull-down node PD, the n-th gate drive signal output terminal and the first level input VGL connections, under the control of pull-down node PD, controlling the n-th gate drive signal output terminal and the first level input VGL Whether connect.

Period P3 is being resetted, under the control of the pull-down node PD of high potential, node discharge module 51 controls pull-up node PU is connect with the first level input VGL, so as to which the current potential of pull-up node PU be dragged down；In the control of the pull-down node PD of high potential Under system, the n-th output terminal discharge module controls the n-th gate drive signal output terminal to be connect with the first level input VGL, so as to make N-th gate drive signal output terminal does not export gate drive signal.

Period P4 is being kept, under the control of the pull-down node PD of high potential, the current potential of pull-up node PU continues to be pulled low, The continuation of n-th gate drive signal output terminal does not export gate drive signal.

The shift register cell that above-described embodiment provides is resetting period P3 and is keeping period P4, defeated in high level signal Under the control for entering the pull-up node PU of end and low potential, pull-down node control module 2 controls pull-down node PD and second electrical level defeated Enter VGH is held to connect, control pull-down node PD and the first level input VGL is not connected to, so as to which the current potential of pull-down node PD be protected It holds in high potential；The pull-down node PD for being maintained at high potential can be put again by control node discharge module 51 and N number of output terminal Electric module is realized and pull-up node PU and N number of gate drive signal output terminal is being resetted period P3 and period P4 kept to continue Electric discharge, caused by avoiding the clock signal inputted as clock signal input terminal the problem of coupling noise voltage, improves displacement The stability and yield of register cell.Therefore, the gate driving that the shift register cell provided by above-described embodiment is formed Circuit has the features such as noise is small, low in energy consumption.

Please continue to refer to Fig. 1 and Fig. 2, the pull-up node control module 1 included by shift register cell is used to input Under the control of control terminal INPUT, whether control power supply signal input VDD connect with pull-up node PU, is additionally operable to reset in N Under the control at end, whether control pull-up node PU connect with the first level input VGL；Pull-down node control module 2 is used for Under the control of second electrical level input terminal VGH and pull-up node PU, whether control pull-down node PD and second electrical level input terminal VGH connects It connects, is additionally operable under the control of pull-up node PU, whether control pull-down node PD connect with the first level input VGL.

Specifically, in input period P1, pull-up node control module 1 is used to control pull-up node PU and input control end INPUT connections, except other periods of input period P1, pull-up node control module 1 is used to control pull-up node PU and input Control terminal INPUT is not connected to；In input period P1 and N number of output period, pull-up node control module 1 is used to control pull-up node PU is not connected to the first level input VGL；Period P3 is being resetted, pull-up node control module 1 is used for the control in N reset terminals Under system, control pull-up node PU is connect with the first level input VGL.

In input period P1 and N number of output period, pull-down node control module 2 be used in second electrical level input terminal VGH and Under the control of the pull-up node PU of high potential, control pull-down node PD and second electrical level input terminal VGH is not connected to, control drop-down section Point PD is connect with the first level input VGL；It is resetting period P3 and is keeping period P4, pull-down node control module 2 is used for Under the control of the pull-up node PU of second electrical level input terminal VGH and low potential, control pull-down node PD and second electrical level input terminal VGH connections, control pull-down node PD and the first level input VGL are not connected to.

Pull-up node control module 1 that above-described embodiment provides, pull-down node control module 2, capacitance module 6 and N number of defeated The concrete structure for going out module is varied, and a kind of concrete structure of each module is given below, but is not limited only to this.

As shown in figure 3, above-mentioned n-th output module includes：First switch pipe T1, second switch pipe T2, third switch transistor T 3 With the 4th switch transistor T 4, wherein, the grid of first switch pipe T1 is connect with the n-th clock signal input terminal, first switch pipe T1's First pole is connect with pull-up node PU；The grid of second switch pipe T2 is connect with the second pole of first switch pipe T1, second switch The first pole of pipe T2 is connect with the n-th clock signal input terminal, and the second pole and the n-th gate drive signal of second switch pipe T2 export End connection；The grid of third switch transistor T 3 is connect with the second pole of second switch pipe T2, the first pole and the electricity of third switch transistor T 3 The second end connection of molar block 6, the second pole of third switch transistor T 3 is connect with the n-th gate drive signal output terminal；4th switch The grid of pipe T4 is connect with the n-th reset terminal, and the first pole of the 4th switch transistor T 4 is connect with the n-th gate drive signal output terminal, the Second pole of four switch transistor Ts 4 is connect with the first level input VGL.

Above-mentioned n-th output control module includes the 5th switch transistor T 5, the grid and the (n+1)th clock signal of the 5th switch transistor T 5 Input terminal connects, and the first pole of the 5th switch transistor T 5 connect with the grid of second switch pipe, the second pole of the 5th switch transistor T 5 and First level input VGL connections.

Above-mentioned node discharge module 51 includes the 6th switch transistor T 6, and grid and the pull-down node PD of the 6th switch transistor T 6 connect It connects, the first pole of the 6th switch transistor T 6 is connect with pull-up node PU, the second pole and the first level input of the 6th switch transistor T 6 VGL connections.

Above-mentioned n-th output terminal discharge module includes the 7th switch transistor T 7, grid and the pull-down node PD of the 7th switch transistor T 7 Connection, the first pole of the 7th switch transistor T 7 connect with the n-th gate drive signal output terminal, the second pole of the 7th switch transistor T 7 and the One level input VGL connections.

Above-mentioned pull-up node control module 1 includes：8th switch transistor T 8 and the 9th switch transistor T 9, wherein the 8th switch transistor T 8 Grid connect with input control end INPUT, the first pole of the 8th switch transistor T 8 is connect with power supply signal input VDD, the 8th Second pole of switch transistor T 8 is connect with pull-up node PU；The grid of 9th switch transistor T 9 is connect with N reset terminals, the 9th switching tube The first pole of T9 is connect with pull-up node PU, and the second pole of the 9th switch transistor T 9 is connect with the first level input VGL.

Above-mentioned pull-down node control module 2 includes：Tenth switch transistor T 10, the 11st switch transistor T 11, the 12nd switching tube T12 and the 13rd switch transistor T 13, wherein the first of the grid of the tenth switch transistor T 10 and the tenth switch transistor T 10 extremely with the second electricity Flat input terminal VGH connections；The grid of 11st switch transistor T 11 is connect with the second pole of the tenth switch transistor T 10, the 11st switching tube The first pole of T11 is connect with second electrical level input terminal VGH, and the second pole of the 11st switch transistor T 11 is connect with pull-down node PD；The The grid of 12 switch transistor Ts 12 is connect with pull-up node PU, and the first pole of the 12nd switch transistor T 12 is connect with pull-down node PD, Second pole of the 12nd switch transistor T 12 is connect with the first level input VGL；The grid of 13rd switch transistor T 13 is saved with pull-up Point PU connections, the first pole of the 13rd switch transistor T 13 are connect with the grid of the 11st switching tube, and the of the 13rd switch transistor T 13 Two poles are connect with the first level input VGL.

First end of first end of the capacitance module 6 including the first capacitance C1, the first capacitance C1 as capacitance module 6, first Second end of the second end of capacitance C1 as capacitance module 6.

During the shift register cell work of above structure, opened in input period P1, input control end INPUT control the 8th Close pipe T8 conductings so that pull-up node PU is connect with power supply signal input VDD, and the current potential of pull-up node PU is drawn high；High electricity The pull-up node PU of position controls the 12nd switch transistor T 12 to be connected so that pull-down node PD is connect with low level signal input terminal, will The current potential of pull-down node PD drags down, while the pull-up node PU of high potential controls the 13rd switch transistor T 13 to be connected, and makes the 11st to open The grid for closing pipe T11 is connect with low level signal input terminal, and the current potential of the grid of the 11st switch transistor T 11 is dragged down, thus the 11 switch transistor Ts 11 are ended so that pull-down node PD is not connected to second electrical level input terminal VGH.

By taking N is equal to 2 as an example, refering to Fig. 1-Fig. 4, above-mentioned shift register cell includes two output modules, i.e., first is defeated Go out 31 and second output module 32 of module, and the structure of two output modules is identical, including first switch pipe T1, second switch Pipe T2,3 and the 4th switch transistor T 4 of third switch transistor T.Above-mentioned shift register cell include two output control modules, i.e., first 41 and second output control module 42 of output control module, and two output control module structures are identical, including the 5th switch Pipe T5.Above-mentioned shift register cell includes two output terminal discharge modules, i.e. the first output terminal discharge module 52 and second is defeated Outlet discharge module 53, and the structure of two output terminal discharge modules is identical, including the 7th switch transistor T 7.

Period P21 is exported first, the first clock signal input terminal CLK1 controls first in the first output module 31 to open Closing pipe T1 conductings so that the pull-up node PU of high potential is connect with the grid of the second switch pipe T2 in the first output module 31, The pull-up node PU of high potential controls the second switch pipe T2 conductings in the first output module 31 so that in the first output module 31 Third switch transistor T 3 grid and first gate driving signal output terminal OUTPUT1 with the first clock signal input terminal CLK1 Connection, the first clock signal input terminal CLK1 control the third switch transistor T 3 in the first output module 31 to be connected so that the first grid Pole driving signal output end OUTPUT1 is connect with the second end of capacitance module 6, and then makes first gate driving signal output terminal OUTPUT1 exports first gate driving signal, and the current potential of pull-up node PU is further pulled up.

Period P22 is exported second, second clock signal input part CLK2 controls first in the second output module 32 to open Closing pipe T1 conductings so that the pull-up node PU of high potential is connect with the grid of the second switch pipe T2 in the second output module 32, The pull-up node PU of high potential controls the second switch pipe T2 conductings in the second output module 32 so that in the second output module 32 Third switch transistor T 3 grid and second grid driving signal output end OUTPUT2 with second clock signal input part CLK2 Connection, second clock signal input part CLK2 control the third switch transistor T 3 in the second output module 32 to be connected so that second gate Pole driving signal output end OUTPUT2 is connect with the second end of capacitance module 6, and then makes second grid driving signal output end OUTPUT2 export second grid drive signal, and keep pull-up node PU be further pulled up after high potential.

Meanwhile period P22 is exported second, the first reset terminal RESET1 controls the 4th switch in the first output module 31 Pipe T4 is connected so that the third switch transistor T 3 in first gate driving signal output terminal OUTPUT1 and the first output module 31 Grid connect with low level signal input terminal, so as to which the third switch transistor T 3 in the first output module 31 is ended, the first grid Pole driving signal output end OUTPUT1 and the second end of capacitance module 6 are not connected to, first gate driving signal output terminal OUTPUT1 does not export gate drive signal.In addition, export period P22, second clock signal input part CLK2 controls the second The 5th switch transistor T 5 in one output control module 41 is connected so that the grid of the second switch pipe T2 in the first output module 31 It is connect with low level signal input terminal, under the control of low level signal input terminal, the second switch in the first output module 31 Pipe T2 ends so that first gate driving signal output terminal OUTPUT1 is not connected to the first clock signal input terminal CLK1.

Resetting period P3, under the control of the second reset terminal RESET2, the 4th switching tube in the second output module 32 Conducting so that second grid driving signal output end OUTPUT2 and the grid of the third switch transistor T 3 in the second output module 32 It is extremely connect with low level signal input terminal, so as to which the third switch transistor T 3 in the second output module 32 is ended, second grid drives Dynamic signal output end OUTPUT2 and the second end of capacitance module 6 are not connected to, and second grid driving signal output end OUTPUT2 is not Export gate drive signal.Meanwhile period P3 is being resetted, third clock signal input terminal CLK3 controls the second output control module The 5th switch transistor T 5 in 42 is connected so that the grid and low level signal of the second switch pipe T2 in the second output module 32 is defeated Enter end connection, under the control of low level signal input terminal, the second switch pipe T2 cut-offs in the second output module 32 so that the Two gate drive signal output terminal OUTPUT2 are not connected to second clock signal input part CLK2.In addition, resetting period P3, Second reset terminal RESET2 controls the conducting of the 9th switching tube so that pull-up node PU is connect with low level signal input terminal, will be upper The current potential of node PU is drawn to drag down；The pull-up node PU of low potential controls the 12nd switch transistor T 12 and the 13rd switch transistor T 13 to cut Only, second electrical level input terminal VGH controls the tenth switch transistor T 10 and the 11st switch transistor T 11 to be connected so that pull-down node PD and height Level signal input terminal connects, and the level of pull-down node PD is drawn high；The 6th switch transistor T 6 of pull-down node PD control of high level Conducting so that pull-up node PU is connect by the 6th switch transistor T 6 with the first level input VGL, the pull-down node PD of high level The 7th switch transistor T 7 in the first output terminal discharge module 52 is controlled to be connected so that first gate driving signal output terminal OUTPUT1 is connect with the first level input VGL, in the pull-down node PD control second output terminal discharge module 53 of high level 7th switch transistor T 7 is connected so that second grid driving signal output end OUTPUT2 is connect with the first level input VGL.

Period P4 is being kept, under the control of second electrical level input terminal VGH and the pull-up node PU of low potential, the tenth switch Pipe T10 and the 11st switch transistor T 11 continue to be connected, and the 12nd switch transistor T 12 and the 13rd switch transistor T 13 continue to end so that Pull-down node PD continuation is connect with second electrical level input terminal VGH, so that pull-down node PD is maintained at high potential；High potential Pull-down node PD continues to control the 7th switch transistor T 7 and second in the 6th switch transistor T 6, the first output terminal discharge module 52 defeated The 7th switch transistor T 7 in outlet discharge module 53 is connected so that pull-up node PU is maintained at low potential, first grid driving letter Number output terminal OUTPUT1 and second grid driving signal output end OUTPUT2 does not export gate drive signal.

In the shift register cell of above structure, in input period P1 and each output stage, by the electricity of pull-down node PD Position drags down so that the 7th switch transistor T 7 that the 6th switch transistor T 6 and each output module include is turned off, so as to ensure that pull-up The stability of the signal of node and each gate drive signal output terminal.

In addition, in the shift register cell of above structure, by setting the 5th switch transistor T 5 in output control module Control the conducting and cut-off of the second switch pipe T2 in corresponding output module, preferably realize in each output period and Reset period P3, keep period P4, to the second switch pipe T2 in each output module and each gate drive signal output terminal into Row, which is put, makes an uproar, and preferably improves the stability of shift register cell work.

It is worth noting that, in the shift register cell that above-described embodiment provides, N number of output module corresponds output N number of gate drive signal, wherein the n-th gate drive signal of n-th of output module output is believed as the reset of the (n-1)th reset terminal Number.In addition, when shift register cell includes the output module of three or more, shift register cell includes each defeated Going out module and each output control module can recycle as needed by the first clock signal input terminal CLK1, second clock Signal input part CLK2 and third clock signal input terminal CLK3 corresponds to the clock signal of output, without introducing new clock Signal.

It should be noted that in the present embodiment using each switching tube as N-type transistor, and the first extremely source electrode, second It is illustrated for extremely draining.Above-mentioned each switching tube may be P-type transistor, and each switching tube is P-type transistor Circuit design also within the protection domain of the application.In addition, the clock signal of input is corresponded to by each clock signal input terminal It is pulse signal；Under normal operation, (it can be connect by the first level input VGL, but be not limited only to power cathode This) input low level signal be direct current signal.

The embodiment of the present invention additionally provides a kind of gate driving circuit, the shift LD provided including several above-described embodiments Device unit.

Above-mentioned gate driving circuit may include multiple cascade shift register cells, below to include two shift LDs For device unit, the structure and connection mode of gate driving circuit are illustrated.

As shown in figure 5, gate driving circuit includes the first shift register cell 71 and the second shift register cell 72, Wherein the first shift register cell 71 includes pull-up node control module, pull-down node control module, capacitance module, node Discharge module, the first output terminal discharge module, second output terminal discharge module, the first output control module, the second output control Module (not shown), the first output module 31 and the second output module 32；Second shift register cell 72 includes Draw node control module, pull-down node control module, capacitance module, node discharge module, the first output terminal discharge module, second Output terminal discharge module, the first output control module, the second output control module (not shown), 33 and of third output module 4th output module 34.

First output module 31 exports first gate driving signal by first gate driving signal output terminal OUTPUT1, Second output module 32 exports second grid drive signal, third output by second grid driving signal output end OUTPUT2 Module 33 exports third gate drive signal by third gate drive signal output terminal OUTPUT3, and the 4th output module 34 is logical It crosses the 4th gate drive signal output terminal OUTPUT4 and exports the 4th gate drive signal.

When the gate driving circuit works, from start frame signal output end STV to the defeated of the first shift register cell 71 Enter control terminal INPUT and input control signal is provided；From second grid driving signal output end OUTPUT2 to the second shift register The input control end INPUT of unit 72 provides input control signal.From second grid driving signal output end OUTPUT2 to first Reset terminal RESET1 provides the first reset signal；From third gate drive signal output terminal OUTPUT3 to the second reset terminal RESET2 provides the second reset signal；It is provided from the 4th gate drive signal output terminal OUTPUT4 to third reset terminal RESET3 Third reset signal.

Due to above-mentioned shift register cell set multiple output modules share same pull-up node control module 1, under Node control module 2, capacitance module 6, pull-up node PU and pull-down node PD are drawn, and with reference to timing control, in different output Period controls corresponding output module output gate drive signal, and realizing a shift register cell being capable of timesharing output Multiple gate drive signals, therefore, gate driving circuit provided in an embodiment of the present invention is by above-mentioned shift register cell structure Cheng Shi reduces the quantity of the required thin film transistor (TFT) of gate driving circuit, so as to reduce power consumption and gate driving electricity The production cost on road, improves production yield.Moreover, because the quantity of the required thin film transistor (TFT) of gate driving circuit compared with It is few so that when in the display device for applying the gate driving circuit, to meet the narrow frame of display device well Design requirement.

The embodiment of the present invention additionally provides a kind of driving method of shift register cell, is provided applied to above-described embodiment Shift register cell, the driving method of the shift register cell includes：When inputting period P1, N number of output period, resetting Section P3 and holding period P4.

Specifically, in input period P1, under the control of input control end INPUT, pull-up node control module 1 controls electricity Source signal input terminal VDD is connect with pull-up node PU.

In the n-th output period, under the control of the n-th clock signal input terminal and pull-up node PU, the n-th output module control It makes the n-th gate drive signal output terminal to connect with the n-th clock signal input terminal, the n-th gate drive signal output terminal of control and electricity The second end connection of molar block 6；Under the control of the (n-1)th reset terminal, the (n-1)th output module controls the (n-1)th gate drive signal Output terminal is connect with the first level input VGL, and controls the second of the (n-1)th gate drive signal output terminal and capacitance module 6 End is not connected to.

Period P3 is being resetted, under the control of N reset terminals, N output modules control N gate drive signal output terminals It is connect with the first level input VGL, and N gate drive signals output terminal and the second end of capacitance module 6 is controlled to be not connected to； Under the control of N reset terminals, pull-up node control module 1 controls pull-up node PU to be connect with the first level input VGL.

Keeping period P4, under the control of second electrical level input terminal VGH and pull-up node PU, pull-down node control module 2 control pull-down node PD are connect with second electrical level input terminal VGH, and control pull-down node PD and the first level input VGL does not connect It connects.

With reference to the structure of above-mentioned shift register cell and specific driving process it is found that using provided in an embodiment of the present invention When driving method drives above-mentioned shift register cell, period P21 is exported first, the first output module 31 can control first Gate drive signal output terminal OUTPUT1 is connect, and control first gate driving signal with the first clock signal input terminal CLK1 Output terminal OUTPUT1 is connect with the second end of capacitance module 6, and first gate driving signal output terminal OUTPUT1 is made to export first Gate drive signal；When n is more than 1, the period is exported n-th, the n-th output module can control the n-th gate drive signal to export End is connect with the n-th clock signal input terminal, and the n-th gate drive signal output terminal is controlled to be connect with the second end of capacitance module 6, The n-th gate drive signal output terminal is made to export the n-th gate drive signal, meanwhile, under the control of the (n-1)th reset terminal, (n-1)th is defeated The second end for going out module control the (n-1)th gate drive signal output terminal and capacitance module 6 is not connected to, and the (n-1)th grid is controlled to drive Dynamic signal output end is connect with the first level input VGL, so as to ensure that, in each output period, only there are one grids to drive Dynamic signal output end can export gate drive signal.

Therefore, when driving method provided in an embodiment of the present invention drives above-mentioned shift register cell, above-mentioned shift LD Device unit can be by setting multiple output modules to share same pull-up node control module 1, pull-down node control module 2, electricity Molar block 6, pull-up node PU and pull-down node PD were realized in the different output periods, controlled corresponding output module output grid Pole drive signal, realize a shift register cell can timesharing export multiple gate drive signals, therefore, this will be utilized When the shift register cell of driving method driving that inventive embodiments provide forms gate driving circuit, reduce gate driving The quantity of the required thin film transistor (TFT) of circuit, so as to reduce the production cost of power consumption and gate driving circuit, improves Production yield.Moreover, because the negligible amounts of the required thin film transistor (TFT) of gate driving circuit so that by the gate driving When in the display device of circuit application, the design requirement of the narrow frame of display device is met well.

When above-mentioned shift register cell further includes N number of output control module, the driving method of above-described embodiment offer It further includes：

In the n-th output period, under the control of the n-th clock signal input terminal, the (n-1)th output control module passes through control (n-1)th output module is connect with the first level input VGL, n-th output module to be caused to control the (n-1)th gate driving letter Number output terminal is not connected to the (n-1)th clock signal input terminal.

In period P3 is resetted, under the control of N+1 clock signal input terminals, N output control modules pass through control N output modules are connect with the first level input VGL, to control N gate drive signals output terminal and N clock signals defeated Enter end to be not connected to.

The N number of output included by shift register cell driven using the driving method that above-described embodiment provides controls mould In block, the (n-1)th output control module can pass through control when the n-th gate drive signal output terminal exports the n-th gate drive signal It makes the (n-1)th output module to connect with the first level input VGL, come when controlling the (n-1)th gate drive signal output terminal and (n-1)th Clock signal input part is not connected to；So that exporting the period n-th, the (n-1)th gate drive signal output terminal can only be resetted (n-1)th It under the control at end, is connect with low potential input terminal, so that the (n-1)th gate drive signal output terminal is in the n-th output period Stable low potential avoids its output to the n-th gate drive signal output terminal and has an impact.In addition, N output control moulds Block can reset period P3, by the way that N output modules is controlled to be connect with the first level input VGL, N grids to be controlled to drive Dynamic signal output end is not connected to N clock signal input terminals；So that resetting period P3, N gate drive signals are defeated Outlet can be connect only under the control of N reset terminals with low potential input terminal, so that N gate drive signals export It is stable low potential to hold resetting period P3, ensure that the stability of shift register cell work.

When above-mentioned shift register cell further includes node discharge module 51 and N number of output terminal discharge module, above-mentioned reality The driving method for applying example offer further includes：

It is resetting period P3 and is keeping period P4, under the control of pull-down node PD, the control pull-up of node discharge module 51 Node PU is connect with the first level input VGL；Under the control of pull-down node PD, the n-th output terminal discharge module controls the n-th grid Pole driving signal output end is connect with the first level input VGL.

The shift register cell driven using the driving method that above-described embodiment provides, when resetting period P3 and keeping Section P4, under the control of high level signal input terminal and the pull-up node PU of low potential, the control drop-down of pull-down node control module 2 Node PD is connect with second electrical level input terminal VGH, and control pull-down node PD and the first level input VGL is not connected to, thus will The current potential of pull-down node PD is maintained at high potential；Being maintained at the pull-down node PD of high potential can be discharged mould by control node again Block 51 and N number of output terminal discharge module, realize to pull-up node PU and N number of gate drive signal output terminal reset period P3 and Keep the continuous discharge of period P4, coupling noise voltage caused by avoiding the clock signal inputted as clock signal input terminal Problem improves the yield of shift register cell.Therefore, the grid that the shift register cell provided by above-described embodiment is formed Pole driving circuit has the features such as noise is small, low in energy consumption.

It should be noted that each embodiment in this specification is described by the way of progressive, each embodiment it Between just to refer each other for identical similar part, the highlights of each of the examples are difference from other examples. For embodiment of the method, since it is substantially similar to product embodiments, so describe fairly simple, correlation Place illustrates referring to the part of product embodiments.

In the description of the above embodiment, particular features, structures, materials, or characteristics can be in any one or more It is combined in an appropriate manner in a embodiment or example.

The above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, any Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in change or replacement, should all contain Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.

Claims

1. a kind of shift register cell, which is characterized in that including：

Pull-down node control module, respectively with the pull-up node, second electrical level input terminal, first level input and institute State pull-down node connection；

N number of output module, N are the integer more than 1, wherein,

N-th output module respectively with the n-th clock signal input terminal, the pull-up node, the second end of the capacitance module, n-th Gate drive signal output terminal, first level input and the connection of the n-th reset terminal；N-th output module is used for：Institute Under the control for stating the n-th clock signal input terminal and the pull-up node, control the n-th gate drive signal output terminal with it is described Whether the n-th clock signal input terminal connects and controls the of the n-th gate drive signal output terminal and the capacitance module Whether two ends connect；N-th output module is additionally operable to：Under the control of n-th reset terminal, n-th grid is controlled to drive Whether dynamic signal output end connect and controls the n-th gate drive signal output terminal with the second end of the capacitance module Whether it is connect with first level input；N is the positive integer less than or equal to N.

2. shift register cell according to claim 1, which is characterized in that the shift register cell further includes：

N number of output control module, wherein,

N-th output control module is defeated with the (n+1)th clock signal input terminal, n-th output module and first level respectively Enter end connection, under the control of (n+1)th clock signal input terminal, by control n-th output module with it is described Whether the first level input connects, n-th output module to be caused to control the n-th gate drive signal output terminal and institute State whether the n-th clock signal input terminal connects.

3. shift register cell according to claim 1, which is characterized in that the shift register cell further includes：

Node discharge module and N number of output terminal discharge module, wherein,

The node discharge module is connect respectively with the pull-down node, the pull-up node and first level input, For under the control of the pull-down node, controlling whether the pull-up node connect with first level input；

N-th output terminal discharge module respectively with the pull-down node, the n-th gate drive signal output terminal and it is described first electricity Flat input terminal connection, under the control of the pull-down node, controlling the n-th gate drive signal output terminal and described the Whether one level input connects.

4. shift register cell according to claim 1, which is characterized in that

The pull-up node control module be used under the control at the input control end, control the power supply signal input with Whether the pull-up node connects, and is additionally operable under the control of the N reset terminals, controls the pull-up node and described first Whether level input connects；

The pull-down node control module is used under the control of the second electrical level input terminal and the pull-up node, controls institute It states whether pull-down node connect with the second electrical level input terminal, is additionally operable under the control of the pull-up node, described in control Whether pull-down node connect with first level input.

5. shift register cell according to claim 2, which is characterized in that n-th output module includes：

First switch pipe, the grid of the first switch pipe are connect with n-th clock signal input terminal, the first switch pipe The first pole connect with the pull-up node；

Second switch pipe, the grid of the second switch pipe are connect with the second pole of the first switch pipe, the second switch First pole of pipe is connect with n-th clock signal input terminal, the second pole of the second switch pipe and n-th gate driving Signal output end connects；

Third switching tube, the grid of the third switching tube are connect with the second pole of the second switch pipe, the third switch First pole of pipe is connect with the second end of the capacitance module, the second pole of the third switching tube and n-th gate driving Signal output end connects；

4th switching tube, the grid of the 4th switching tube are connect with n-th reset terminal, the first pole of the 4th switching tube It is connect with the n-th gate drive signal output terminal, the second pole and first level input of the 4th switching tube connect It connects.

6. shift register cell according to claim 5, which is characterized in that n-th output control module includes：

5th switching tube, the grid of the 5th switching tube are connect with (n+1)th clock signal input terminal, the 5th switch First pole of pipe is connect with the grid of the second switch pipe, and the second pole and first level of the 5th switching tube input End connection.

7. shift register cell according to claim 3, which is characterized in that

The node discharge module includes：

6th switching tube, the grid of the 6th switching tube are connect with the pull-down node, the first pole of the 6th switching tube It is connect with the pull-up node, the second pole of the 6th switching tube is connect with first level input；

The n-th output terminal discharge module includes：

7th switching tube, the grid of the 7th switching tube are connect with the pull-down node, the first pole of the 7th switching tube It is connect with the n-th gate drive signal output terminal, the second pole and first level input of the 7th switching tube connect It connects.

8. shift register cell according to claim 4, which is characterized in that

The pull-up node control module includes：

8th switching tube, the grid of the 8th switching tube are connect with the input control end, and the first of the 8th switching tube Pole is connect with the power supply signal input, and the second pole of the 8th switching tube is connect with the pull-up node；

9th switching tube, the grid of the 9th switching tube are connect with the N reset terminals, the first pole of the 9th switching tube It is connect with the pull-up node, the second pole of the 9th switching tube is connect with first level input；

The pull-down node control module includes：

Tenth switching tube, the grid of the tenth switching tube and the first of the tenth switching tube extremely defeated with the second electrical level Enter end connection；

11st switching tube, the grid of the 11st switching tube are connect with the second pole of the tenth switching tube, and the described tenth First pole of one switching tube is connect with the second electrical level input terminal, and the second pole of the 11st switching tube is saved with the drop-down Point connection；

12nd switching tube, the grid of the 12nd switching tube are connect with the pull-up node, the 12nd switching tube First pole is connect with the pull-down node, and the second pole of the 12nd switching tube is connect with first level input；

13rd switching tube, the grid of the 13rd switching tube are connect with the pull-up node, the 13rd switching tube First pole is connect with the grid of the 11st switching tube, and the second pole and first level of the 13rd switching tube input End connection.

9. a kind of gate driving circuit, which is characterized in that including several shift LDs as described in any one of claim 1-8 Device unit.

10. a kind of driving method of shift register cell, which is characterized in that applied to as described in any one of claim 1~8 Shift register cell, the driving method includes：

The period is inputted, under the control at the input control end, the pull-up node control module controls the power supply signal defeated Enter end to connect with the pull-up node；

N number of output period, wherein,

In the n-th output period, under the control of n-th clock signal input terminal and the pull-up node, n-th output Module controls the n-th gate drive signal output terminal to be connect with n-th clock signal input terminal, controls n-th grid Driving signal output end is connect with the second end of the capacitance module；Under the control of the (n-1)th reset terminal, the (n-1)th output module The (n-1)th gate drive signal output terminal is controlled to be connect with first level input, and (n-1)th grid is controlled to drive The second end of dynamic signal output end and the capacitance module is not connected to；

The period is being resetted, under the control of the N reset terminals, the N output modules control the N gate drive signals Output terminal is connect with first level input, and controls the N gate drive signals output terminal and the capacitance module Second end be not connected to；Under the control of the N reset terminals, the pull-up node control module control the pull-up node with The first level input connection；

Kept for the period, under the control of the second electrical level input terminal and the pull-up node, the pull-down node controls mould Block controls the pull-down node to be connect with the second electrical level input terminal, and the pull-down node is controlled to be inputted with first level End is not connected to.

11. the driving method of shift register cell according to claim 10, which is characterized in that when the shift LD When device unit further includes N number of output control module, the driving method further includes：

In the described n-th output period, under the control of n-th clock signal input terminal, the (n-1)th output control module passes through (n-1)th output module is controlled to be connect with first level input, to cause n-th output module control described the N-1 gate drive signals output terminal is not connected to (n-1)th clock signal input terminal；

In the reset period, under the control of the N+1 clock signal input terminals, N output control modules pass through control It makes the N output modules to connect with first level input, to control the N gate drive signals output terminal and institute N clock signal input terminals are stated to be not connected to.

12. the driving method of shift register cell according to claim 10, which is characterized in that when the shift LD When device unit further includes node discharge module and N number of output terminal discharge module, the driving method further includes：

In the reset period and the holding period, under the control of the pull-down node, the node discharge module control The pull-up node is connect with first level input；Under the control of the pull-down node, the n-th output terminal electric discharge Module controls the n-th gate drive signal output terminal to be connect with first level input.