CN107464521B - Shift register cell, gate driving circuit and driving method, display device - Google Patents
Shift register cell, gate driving circuit and driving method, display device Download PDFInfo
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- CN107464521B CN107464521B CN201710910077.6A CN201710910077A CN107464521B CN 107464521 B CN107464521 B CN 107464521B CN 201710910077 A CN201710910077 A CN 201710910077A CN 107464521 B CN107464521 B CN 107464521B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/061—Details of flat display driving waveforms for resetting or blanking
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Abstract
The present invention provides a kind of shift register cell, gate driving circuit and driving method, display device, is related to field of display technology, can improve because threshold voltage shift leads to occur the problem of concealed wire on display screen.The shift register cell, including the first input circuit, under the control of the first signal end, by the voltage output at first voltage end to pull-up node；Second input circuit, under the control at second signal end, by the voltage output at second voltage end to pull-up node；Output circuit, under the control of pull-up node, by the voltage output of clock signal terminal to signal output end；Pull-up node reset circuit, under the control of third signal end, by the voltage output at tertiary voltage end to pull-up node.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of shift register cells, gate driving circuit and its drive
Dynamic method, display device.
Background technique
The development of display in recent years presents high integration, inexpensive development trend.One of them are very heavy
The technology wanted is exactly the realization of GOA (Gate Driver on Array, integrated gate drive circuitry) technology mass production.It utilizes
Gate driving circuit is integrated in the array substrate of display panel by GOA technology, so as to save grid-driving integrated circuit
Part, to reduce product cost in terms of material cost and manufacture craft two.It is this to utilize GOA Integration ofTechnology in array substrate
Gate switch circuit be also referred to as GOA circuit or shift-register circuit, wherein each displacement in the gate switch circuit is posted
Storage is also referred to as GOA unit.Pull-up and drop-down control structure in existing shift register are generally used TFT (Thin Film
Transistor, thin film transistor).But since TFT itself is there are the characteristic of leakage current, GOA circuit usually can
Occur a variety of bad.
For example, a frame time is divided into display stage and loitering phase (loitering phase is short and shows the stage), every level-one GOA
The pull-up node of unit is pulled low under the control of the signal of next stage output, and the pull-up section of afterbody GOA unit
Point, which needs to open Shi Caineng until next frame, to be pulled low.The waveform diagram of pull-up node as shown in Figure 1, afterbody GOA
The pull-up node of unit is kept for the time of high potential be much larger than other row GOA units, so that the output electricity of afterbody GOA unit
Transistor operating time in road is much larger than other row GOA units, if things go on like this, in the output circuit of afterbody GOA unit
Transistor on threshold voltage shift far seriously in other rows.When reverse scan, afterbody GOA unit is as first
Grade, since threshold voltage shift is serious, cause the row GOA unit output voltage can subnormal gate drive signal electricity
Pressure, therefore can occur a line on a display screen due to the concealed wire of the darker formation of display brightness, end user can see on a display screen
To a plurality of concealed wire, display effect is influenced.
Summary of the invention
The embodiment of the present invention provides a kind of shift register cell, gate driving circuit and driving method, display device,
It can improve because threshold voltage shift leads to occur the problem of concealed wire on display screen.
In order to achieve the above objectives, the embodiment of the present invention adopts the following technical scheme that
In a first aspect, providing a kind of shift register cell, including the first input circuit, the second input circuit, output electricity
Road and pull-up node reset circuit；First input circuit connects the first signal end, first voltage end, pull-up node, is used for
Under the control of first signal end, by the voltage output at the first voltage end to the pull-up node；Described second is defeated
Enter circuit, connect second signal end, second voltage end, the pull-up node, for inciting somebody to action under the control at the second signal end
The voltage output at the second voltage end is to the pull-up node；The output circuit, connection clock signal terminal, pull-up section
Point, signal output end, under the control of the pull-up node, by the voltage output of the clock signal terminal to the signal
Output end；The pull-up node reset circuit connects third signal end, the tertiary voltage end, the pull-up node, is used for
Under the control of the third signal end, by the voltage output at the tertiary voltage end to the pull-up node.
Preferably, the shift register cell further includes signal output end reset circuit；The signal output end resets
Circuit connects the third signal end, the tertiary voltage end, the signal output end, in the third signal end
Under control, by the voltage output at the tertiary voltage end to the signal output end.
Preferably, the shift register cell further includes pull-down control circuit, pull-down circuit, Dolby circuit；Under described
Control circuit is drawn, tertiary voltage end, the 4th voltage end, the pull-up node, pull-down node are connected, for the pull-down node
Level controlled；The pull-down circuit connects the pull-down node, the tertiary voltage end, the signal output end, uses
Under the control in the pull-down node, by the voltage output at the tertiary voltage end to the signal output end；The noise reduction
Circuit connects the pull-down node, the tertiary voltage end, the pull-up node, will for the control in the pull-down node
The voltage output at the tertiary voltage end is to the pull-up node.
Preferably, the pull-up node reset circuit includes the first transistor；The grid of the first transistor connects institute
Third signal end is stated, the first pole connects the tertiary voltage end, and the second pole connects the pull-up node.
Preferably, the signal output end reset circuit includes second transistor；The grid of the second transistor connects
The third signal end, the first pole connect the tertiary voltage end, and the second pole connects the signal output end.
Preferably, first input circuit includes third transistor；The grid connection described the of the third transistor
One signal end, the first pole connect the first voltage end, and the second pole connects the pull-up node.
Preferably, second input circuit includes the 4th transistor；The grid connection described the of 4th transistor
Binary signal end, the first pole connect the second voltage end, and the second pole connects the pull-up node.
Preferably, the output circuit includes the 5th transistor and capacitor；Described in the grid connection of 5th transistor
Pull-up node, the first pole connect the clock signal terminal, and the second pole connects the second end of the signal output end and the capacitor；
The first end of the capacitor connects the pull-up node, and second end is also connected with the signal output end.
Preferably, the pull-down control circuit includes the 6th transistor, the 7th transistor；The grid of 6th transistor
The 4th voltage end is connected, the first pole connects the 4th voltage end, and the second pole connects the pull-down node；Described 7th is brilliant
The grid of body pipe connects the pull-up node, and the first pole connects the tertiary voltage end, and the second pole connects the pull-down node.
It is further preferred that the pull-down control circuit further includes the 8th transistor, the 9th transistor；8th crystal
The grid of pipe connects the 4th voltage end, and the first pole connects the 4th voltage end, and the second pole connects the 6th transistor
Grid；The grid of 9th transistor connects the pull-up node, and the first pole connects the tertiary voltage end, and the second pole connects
Connect the grid of the 6th transistor.
Preferably, the pull-down circuit includes the tenth transistor；The grid of tenth transistor connects the drop-down section
Point, the first pole connect the tertiary voltage end, and the second pole connects the signal output end.
Preferably, the Dolby circuit includes the 11st transistor；Under the grid connection of 11st transistor is described
Node is drawn, the first pole connects the tertiary voltage end, and the second pole connects the pull-up node.
Second aspect provides a kind of gate driving circuit, the displacement as described in relation to the first aspect including at least two-stage cascade
Register cell；First signal end of first order shift register cell is connected with initial signal end；In addition to the first order
Other than shift register cell, the of the signal output end of upper level shift register cell and next stage shift register cell
One signal end is connected；Other than afterbody shift register cell, the signal of next stage shift register cell is exported
End is connected with the second signal end of upper level shift register cell；Second letter of the afterbody shift register cell
Number end connects the initial signal end.
The third aspect provides a kind of display device, including gate driving circuit described in second aspect.
Fourth aspect, provide it is a kind of for driving the driving method of shift register cell described in first aspect, it is described
Method includes: input phase: under the control of the first signal end, the first input circuit is supreme by the voltage output at first voltage end
Draw node；Output circuit stores the current potential of the pull-up node, and under the control of the pull-up node, the output
Circuit exports the clock signal of clock signal terminal to signal output end；Output stage: under the control of the pull-up node, institute
It states output circuit to export the clock signal of the clock signal terminal to the signal output end, the signal output end exports grid
Pole scanning signal.
Preferably, the shift register cell further includes pull-down control circuit, pull-down circuit, Dolby circuit；The side
Method further include: drop-down stage: under the control at second signal end, the second input circuit is by the voltage output at second voltage end to institute
Pull-up node is stated, the output circuit is controlled and closes；Under the control of the pull-up node, the pull-down control circuit is by the 4th
The cut-in voltage of voltage end input is exported to pull-down node；Under the control of the pull-down node, the pull-down circuit is by third
The voltage output of voltage end is to signal output end；The Dolby circuit is by the voltage output at the tertiary voltage end to the drop-down
Node.
5th aspect, provides a kind of for driving the driving method of gate driving circuit described in second aspect, the side
Method includes: in a picture frame: the first order shift register cell of gate driving circuit receives the starting letter at initial signal end
Number, the shift register cell in gate driving circuit is opened step by step；Between two picture frames: all in gate driving circuit
Shift register cell receives the open signal of third signal end, while resetting the pull-up node of all shift register cells.
The present invention provides a kind of shift register cell, gate driving circuit and driving method, display device, passes through increase
Pull-up node reset circuit, after signal output end exports gated sweep signal, control pull-up node reset circuit is opened, pull-up
Node reset circuit pulls up node output low-potential signal, closes output circuit.For afterbody shift register list
For member, without starting until next frame, output circuit can be closed, the working time of output circuit is shortened.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the waveform diagram of the pull-up node in prior art gate driving circuit；
Fig. 2 (a) is a kind of structural schematic diagram of shift register cell provided in an embodiment of the present invention；
Fig. 2 (b) is the structural schematic diagram of another shift register cell provided in an embodiment of the present invention；
Fig. 3 is a kind of concrete structure schematic diagram of each circuit in Fig. 2 (b)；
Fig. 4 is another concrete structure schematic diagram of each circuit in Fig. 2 (b)；
Fig. 5 is a kind of signal timing diagram of shift register cell shown in control figure 3 or 4；
Fig. 6 is a kind of structural schematic diagram of gate driving circuit provided in an embodiment of the present invention；
Fig. 7 is the waveform diagram of the pull-up node in gate driving circuit provided in an embodiment of the present invention.
Appended drawing reference
The first input circuit of 10-；The second input circuit of 20-；30- output circuit；40- pull-up node reset circuit；50- letter
Number output end reset circuit；60- pull-down control circuit；70- pull-down circuit；80- Dolby circuit；The first signal end of IN1-；IN2-
Second signal end；IN3- third signal end；CLK- clock signal terminal；OUTPUT- signal output end；V1- first voltage end；V2-
Second voltage end；V3- tertiary voltage end；The 4th voltage end of V4-；PU- pull-up node；PD- pull-down node；C- capacitor.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of shift register cell, as shown in Fig. 2 (a), including the first input circuit 10,
Two input circuits 20, output circuit 30 and pull-up node reset circuit 40.
Wherein, the first input circuit 10 connects the first signal end IN1, first voltage end V1, pull-up node PU, is used for
Under the control of first signal end IN1, by the voltage output of first voltage end V1 to pull-up node PU.
Second input circuit 20 connects second signal end IN2, second voltage end V2, pull-up node PU, in the second letter
Number end IN2 control under, by the voltage output of second voltage end V2 to pull-up node PU.
Output circuit 30 connects clock signal terminal CLK, pull-up node PU, signal output end OUTPUT, for saving in pull-up
Under the control of point PU, by the voltage output of clock signal terminal CLK to signal output end OUTPUT.
Pull-up node reset circuit 40 connects third signal end IN3, tertiary voltage end V3, pull-up node PU, for the
Under the control of three signal end IN3, by the voltage output of tertiary voltage end V3 to pull-up node PU.
It should be noted that the current potential of signal output end OUTPUT can by low level that clock signal terminal CLK is inputted come
It resets.
Preferably, as shown in Fig. 2 (b), the shift register cell further includes signal output end reset circuit 50.
Signal output end reset circuit 50 connects third signal end IN3, tertiary voltage end V3, signal output end OUTPUT,
For under the control of third signal end IN3, by the voltage output of tertiary voltage end V3 to signal output end OUTPUT.
Preferably, as shown in Fig. 2 (b), the shift register cell further includes pull-down control circuit 60, pull-down circuit
70, Dolby circuit 80.
Pull-down control circuit 60 connects tertiary voltage end V3, the 4th voltage end V4, pull-up node PU, pull-down node PD, uses
It is controlled in the level to the pull-down node.
That is, under the control of pull-up node PU, by the voltage output of tertiary voltage end V3 to pull-down node PD, alternatively,
Under the control of pull-up node PU, by the voltage output of the 4th voltage end V4 to pull-down node PD.
Pull-down circuit 70 connects pull-down node PD, tertiary voltage end V3, signal output end OUTPUT, for saving in drop-down
Under the control of point PD, by the voltage output of tertiary voltage end V3 to signal output end OUTPUT.
Dolby circuit 80 connects pull-down node PD, tertiary voltage end V3, pull-up node PU, for pull-down node PD's
It controls the voltage output of tertiary voltage end V3 to pull-up node PU.
Pull-down control circuit 60 can control the current potential of pull-down node PD, so that pull-down node PD can control noise reduction
The current potential of pull-up node PU is pulled down to the current potential of tertiary voltage end V3 by circuit 80, to carry out noise reduction to pull-up node PU.
It should be noted that the signal that above-mentioned first signal end IN1 and second signal end IN2 is exported in the embodiment of the present invention
Low and high level each other.In addition, following embodiment is to input constant high level with first voltage end V1, second voltage end V2 and
Tertiary voltage end V3 inputs the explanation carried out for constant low level or ground connection.
So, on the one hand, the first input circuit 10 can be under the first signal end IN1 control, by first voltage end
The voltage output of V1 is to pull-up node PU, in addition, the second input circuit 20 can be under the control of second signal end IN2, by
The voltage output of two voltage end V2 is to pull-up node PU.In the case, when the shift register cell uses forward scan,
For charging to pull-up node PU, the voltage of second voltage end V2 is used for pull-up node PU the voltage of first voltage end V1
It is resetted, and when the shift register cell uses reverse scan, the voltage of second voltage end V2 is used for pull-up node
PU charges, and the voltage of first voltage end V1 is for resetting pull-up node PU.
Based on this, after pull-up node PU is electrically charged, output circuit 30 under the control of pull-up node PU, can by when
The clock signal of clock signal end CLK is exported to signal output end OUTPUT, so that signal output end OUTPUT is in output stage
Gated sweep signal can be exported to the grid line being connected with signal output end OUTPUT.Second input circuit 20 is in the second letter
Under the control of number end IN2, by the voltage output of second voltage end V2 to pull-up node PU, to be controlled by pull-down control circuit 60
The current potential of pull-down node PD, so that pull-down circuit 70 is under the control of pull-down node PD, by the current potential of signal output end OUTPUT
It is pulled down to the current potential of tertiary voltage end V3.
On the other hand, pull-up node reset circuit 40 can be under the control of third signal end IN3 by pull-up node PU's
Current potential is pulled down to the current potential of tertiary voltage end V3, to control the closing of output circuit 30；Signal output end reset circuit 50 can be
The current potential of signal output end OUTPUT is also pulled down to the current potential of tertiary voltage end V3 under the control of third signal end IN3.
So, by increasing pull-up node reset circuit 40, in signal output end OUTPUT output gated sweep letter
After number, control pull-up node reset circuit 40 is opened, and pull-up node reset circuit 40 pulls up node PU output low-potential signal,
Close output circuit 30.For afterbody shift register cell, without starting until next frame, it can close defeated
Circuit 30 out shorten the working time of output circuit 30.In addition, starting for shift register cell in next frame
Before, low potential is exported to signal output end OUTPUT by signal output end reset circuit 50, it can be to shift register cell
Play the role of noise reduction.
Hereinafter, the specific structure of each circuit in above-mentioned shift register cell is described in detail.
Optionally, as shown in Figure 3 and Figure 4, pull-up node reset circuit 40 includes the first transistor M1.
The grid of the first transistor M1 connects third signal end IN3, and the first pole connects tertiary voltage end V3, the connection of the second pole
Pull-up node PU.
Optionally, as shown in Figure 3 and Figure 4, signal output end reset circuit 50 includes second transistor M2.
The grid of second transistor M2 connects third signal end IN3, and the first pole connects tertiary voltage end V3, the connection of the second pole
Signal output end OUTPUT.
As shown in Figure 3 and Figure 4, the first input circuit 10 includes third transistor M3.
The grid of the third transistor M3 connects the first signal end IN1, and the first pole connects the first voltage end
V1, the second pole connect the pull-up node PU.
As shown in Figure 3 and Figure 4, the second input circuit 20 includes the 4th transistor M4.
The grid of the 4th transistor M4 connects the second signal end IN2, and the first pole connects the second voltage end
V2, the second pole connect the pull-up node PU.
As shown in Figure 3 and Figure 4, output circuit 30 includes the 5th transistor M5 and capacitor C.
The grid of the 5th transistor M5 connects the pull-up node PU, and the first pole connects the clock signal terminal CLK,
Second pole connects the second end of the signal output end OUTPUT and the capacitor C.
The first end of the capacitor C connects the pull-up node PU, and second end is also connected with the signal output end OUTPUT.
As shown in figure 3, pull-down control circuit 60 includes the 6th transistor M6, the 7th transistor M7.
The grid of the 6th transistor M6 connects the 4th voltage end V4, and the first pole connects the 4th voltage end
V4, the second pole connect the pull-down node PD.
The grid of the 7th transistor M7 connects the pull-up node PU, and the first pole connects the tertiary voltage end V3,
Second pole connects the pull-down node PD.
As shown in figure 4, pull-down control circuit 60 further includes the 8th transistor M8, the 9th transistor M9.
The grid of the 8th transistor M8 connects the 4th voltage end V4, and the first pole connects the 4th voltage end
V4, the second pole connect the grid of the 6th transistor M6.
The grid of the 9th transistor M9 connects the pull-up node PU, and the first pole connects the tertiary voltage end V3,
Second pole connects the grid of the 6th transistor M6.
As shown in Figure 3 and Figure 4, pull-down circuit 70 includes the tenth transistor M10.
The grid of tenth transistor M10 connects pull-down node PD, and the first pole connects tertiary voltage end V3, the second pole connection letter
Number output end OUTPUT.
As shown in Figure 3 and Figure 4, Dolby circuit 80 includes the 11st transistor M11.
The grid of 11st transistor M11 connects pull-down node PD, and the first pole connects tertiary voltage end V3, the connection of the second pole
Pull-up node PU.
It should be noted that above-mentioned transistor can be N-type transistor, or P-type transistor；It can be enhanced
Transistor, or depletion mode transistor；The first of above-mentioned transistor extremely can be source electrode, and second can be extremely drain electrode, or
The first of the above-mentioned transistor of person can be extremely drain electrode, and the second extremely source electrode, this is not limited by the present invention.
Hereinafter, signal timing diagram as shown in connection with fig. 5 is to Fig. 3 and Fig. 4 so that above-mentioned transistor is N-type transistor as an example
Shown in shift register cell the break-make situation in different stages carry out detailed illustration.Wherein, the present invention is real
Apply in example is with first voltage end V1 constant output high level, second voltage end V2 and tertiary voltage end V3 constant output low level
For the explanation that carries out.In addition, following explanation is to receive input signal INPUT, second signal end IN2 with the first signal end IN1
For reception reset signal RESET.
In input phase P1, INPUT=1, RESET=0, CLK=0, IN3=0, V4=1；Wherein " 0 " indicates low level,
" 1 " indicates high level.
At this point, since the first signal end IN1 exports high level, third transistor M3 conducting, thus by first voltage
Hold the high level output of V1 to pull-up node PU.Under the control of pull-up node PU high potential, the 5th transistor M5 conducting, by when
The low level output of clock signal end CLK is to signal output end OUTPUT.
As shown in figure 3, under the control of pull-up node PU high potential, the 7th transistor M7 conducting, in the 4th voltage end V4
Under the control of high level, the 6th transistor M6 conducting, but since the breadth length ratio of the 7th transistor M7 channel is greater than the 6th transistor
The breadth length ratio of M6 channel, so that the current potential of pull-down node PD still can be pulled down to the low of tertiary voltage end V3 by the 7th transistor M7
Level.In the case, the tenth transistor M10 and the 11st transistor M11 are in off state.
As shown in figure 4, under the control of pull-up node PU high potential, the 7th transistor M7 and the 9th transistor M9 conducting,
Under the control of the 4th voltage end V4 high level, the 8th transistor M8 conducting, but due to the breadth length ratio of the 9th transistor M9 channel
Greater than the breadth length ratio of the 8th transistor M8 channel, so that the 6th transistor M6 grid is low level, the 6th transistor M6 of control is cut
Only, the current potential of pull-down node PD can still be pulled down to the low level of tertiary voltage end V3 by the 7th transistor M7.In the case,
Tenth transistor M10 and the 11st transistor M11 are in off state.
In addition, third signal end IN3 input low level, so that the first transistor M1 and second transistor M2 are turned off；The
Binary signal end IN2 input low level, so that the 4th transistor M4 ends.
In conclusion signal output end OUTPUT exports low level in above-mentioned input phase P1.
Output stage P2, INPUT=0, RESET=0, CLK=1, IN3=0, V4=1.
At this point, third transistor M3 is in off state since the first signal end IN1 exports low level.Capacitor C will
The high level of input phase P1 storage charges to pull-up node PU, so that the 5th transistor M5 is kept it turned on.
In the case, the high level of clock signal terminal CLK is exported by the 5th transistor M5 to signal output end OUTPUT.In addition,
Under bootstrapping (Bootstrapping) effect of capacitor C, the current potential of pull-up node PU further increases (capacitor C and signal output
Holding the current potential of one end of OUTPUT connection to be jumped by 0 is 1, when capacitor C charges to pull-up node PU, pull-up node PU's
1) current potential is jumped to high potential again on the basis of 1, with the state for maintaining the 5th transistor M5 to be on, so that clock
The high level of signal end CLK can be exported to the grid line being connected with signal output end OUTPUT as gated sweep signal.
As shown in figure 3, under the control of pull-up node PU high potential, the 7th transistor M7 conducting, in the 4th voltage end V4
Under the control of high level, the 6th transistor M6 conducting, but since the breadth length ratio of the 7th transistor M7 channel is greater than the 6th transistor
The breadth length ratio of M6 channel, so that the current potential of pull-down node PD still can be pulled down to the low of tertiary voltage end V3 by the 7th transistor M7
Level.In the case, the tenth transistor M10 and the 11st transistor M11 are in off state.
As shown in figure 4, under the control of pull-up node PU high potential, the 7th transistor M7 and the 9th transistor M9 conducting,
Under the control of the 4th voltage end V4 high level, the 8th transistor M8 conducting, but due to the breadth length ratio of the 9th transistor M9 channel
Greater than the breadth length ratio of the 8th transistor M8 channel, so that the 6th transistor M6 grid is low level, the 6th transistor M6 of control is cut
Only, so that the current potential of pull-down node PD can still be pulled down to the low level of tertiary voltage end V3 by the 7th transistor M7.In this feelings
Under condition, the tenth transistor M10 and the 11st transistor M11 are in off state.
In addition, third signal end IN3 input low level, so that the first transistor M1 and second transistor M2 are turned off, the
Binary signal end IN2 input low level, so that the 4th transistor M4 ends.
In conclusion signal output end OUTPUT above-mentioned output stage P2 export high level, with to signal output end
The grid line that OUTPUT is connected exports gated sweep signal.
Drop-down stage P3, INPUT=0, RESET=1, CLK=0, IN3=0, V4=1.
At this point, since second signal end IN2 exports high level, the 4th transistor M4 conducting, thus by pull-up node PU's
Current potential is pulled down to the low level of second voltage end V2, and the 5th transistor M5 is in off state.
As shown in figure 3, the 7th transistor M7 cut-off, the 6th transistor M6 exists under the control of pull-up node PU low potential
It is connected under the control of 4th voltage end V4 high level, and by the high level output of the 4th voltage end V4 to pull-down node PD, under
Under the control for drawing node PD high potential, the tenth transistor M10 and the 11st transistor M11 are both turned on, and pass through the 11st transistor
The current potential of pull-up node PU is pulled down to the low level of tertiary voltage end V3 by M11, and is exported signal by the tenth transistor M10
The current potential of end OUTPUT is pulled down to the low level of tertiary voltage end V3.
As shown in figure 4, the 7th transistor M7 and the 9th transistor M9 are cut under the control of pull-up node PU low potential
Only, the 8th transistor M8 is connected under the control of the 4th voltage end V4 high level, and by the high level output of the 4th voltage end V4
To the grid of the 6th transistor M6, the 6th transistor M6 conducting is controlled, the 6th transistor M6 is by the high level of the 4th voltage end V4
Output is to pull-down node PD, and under the control of pull-down node PD high potential, the tenth transistor M10 and the 11st transistor M11 are equal
The current potential of pull-up node PU, is pulled down to the low level of tertiary voltage end V3 by the 11st transistor M11 by conducting, and passes through the
The current potential of signal output end OUTPUT is pulled down to the low level of tertiary voltage end V3 by ten transistor M10.
In addition, the first signal end IN1 input low level, so that third transistor M3 ends；Third signal end IN3 input is low
Level, so that the first transistor M1 and second transistor M2 are turned off.
Reseting stage P4, INPUT=0, RESET=0, IN3=1, V4=0.
At this point, third signal end IN3 enters and leaves high level, the first transistor M1 and second transistor M2 are both turned on, make the
The low level of tertiary voltage end V3 is input to pull-up node PU by one transistor M1, to be resetted to pull-up node PU, control
The low level of tertiary voltage end V3 is input to signal output end OUTPUT by the 5th transistor M5 cut-off, second transistor M2, with
Signal output end OUTPUT is resetted.
Wherein, third signal end IN3 can be also possible to resetting rank in entire reseting stage P4 input high level always
Section P4 start and/or at the end of respectively input a high level.
In this stage other than the first transistor M1 and second transistor M2 is connected, remaining transistor is in cut-off shape
State.
It should be noted that the switching process of transistor is to be using all transistors as N-type transistor in above-described embodiment
What example was illustrated, when all transistors are p-type, need to overturn control signal each in Fig. 5, and shift LD
The make and break process of the transistor of each circuit is same as above in device unit, and details are not described herein again.
In addition, the course of work of above-mentioned shift register cell, is constituted with above-mentioned multiple shift register cell cascades
Gate driving circuit by the way of forward scan for the explanation that carries out.When using reverse scan, in Fig. 3 and Fig. 4 institute
In the shift register cell shown, the first signal end IN1 can be received to reset signal RESET, second signal end IN2 receives defeated
Enter signal INPUT.In addition, above-mentioned first voltage end V1 input low level, second voltage end V2 input high level.
The embodiment of the present invention provides a kind of gate driving circuit, as shown in fig. 6, including multiple cascade as described above
Any one shift register cell (RS1, RS2......RSn).
The first signal end IN1 connection initial signal end STV of first order shift register cell RS1, in addition to the first order is moved
Other than bit register unit R S1, the signal output end OUTPUT and next stage of upper level shift register cell RS (n-1) is shifted
The first signal end IN1 of register cell RS (n) is connected.Wherein, initial signal end STV is for exporting initial signal, the grid
The first order shift register cell RS1 of pole driving circuit start after receiving above-mentioned initial signal to grid line (G1,
G2......Gn it) is progressively scanned.
In addition, other than afterbody shift register cell RSn, the second signal of next stage shift register cell
Hold the signal output end OUTPUT of IN2 connection upper level shift register cell, the of afterbody shift register cell RSn
The above-mentioned initial signal end STV of binary signal end IN2 connection.So, when the initial signal of initial signal end STV inputs the first order
When the first signal end IN1 of shift register cell RS1, the second signal end IN2 of afterbody shift register cell RSn can
The initial signal of initial signal end STV to be exported as signal of the reset signal to afterbody shift register cell RSn
End OUTPUT is resetted.
On this basis, the first voltage end V1 connection high level VDD of every level-one shift register cell, second voltage end
V2 connection low level VSS, tertiary voltage end V3 connection low level VGL.
In addition, gate driving circuit shown in fig. 6 is the connection side of each control signal when carrying out forward scan to grid line
Method.When carrying out reverse scan to grid line using the gate driving circuit, the second signal of first order shift register cell RS1
Hold IN2 connection initial signal end STV, other than first order shift register cell RS1, upper level shift register cell RS
(n-1) signal output end OUTPUT is connected with the second signal end IN2 of next stage shift register cell RS (n).In addition to
Other than afterbody shift register cell RSn, the first signal end IN1 connection upper level of next stage shift register cell is moved
The signal output end OUTPUT of bit register unit.In the first signal end IN1 connection of afterbody shift register cell RSn
State initial signal end STV.
On this basis, the first voltage end V1 connection low level VSS of every level-one shift register cell, second voltage end
V2 connection high level VDD, tertiary voltage end V3 connection low level VGL.
As can be seen from Figure 6, each shift register cell in gate driving circuit connects same root third signal end IN3,
When third signal end IN3 input high level, entire gate driving circuit is completed to signal output end OUTPUT and pull-up node
The reset of PU.
The embodiment of the present invention provides a kind of display device, including any one gate driving circuit as described above, has
Structure identical with the gate driving circuit that previous embodiment provides and beneficial effect.Since previous embodiment drives grid
The structure and beneficial effect of dynamic circuit are described in detail, and details are not described herein again.
The embodiment of the present invention provides a kind of method for driving above-mentioned gate driving circuit, specifically, the method packet
It includes:
In a picture frame:
The first order shift register cell of gate driving circuit receives the initial signal of initial signal end STV, opens step by step
Open the shift register cell in gate driving circuit.
Wherein, after the shift register cell output gated sweep signal in addition to afterbody, pull-up node PU current potential
Drag down is that the signal of tertiary voltage end V3 is input to pull-up node under the control of second signal end IN2 by the second input circuit 20
PU is completed；After afterbody bit shift register unit exports gated sweep signal, dragging down for pull-up node PU current potential is
The signal of tertiary voltage end V3 is input to pull-up node PU under the control of third signal end IN3 by pull-up node reset circuit 40
Come what is completed.
Between two picture frames:
All shift register cells in gate driving circuit receive the open signal of third signal end IN3, multiple simultaneously
The pull-up node PU of all shift register cells in position.
The beneficial effect of the driving method of gate driving circuit provided in an embodiment of the present invention and above-mentioned shift register list
The beneficial effect of member is identical, and details are not described herein again.
The embodiment of the present invention provides a kind of method for driving any one of the above shift register cell, the method
Include:
Input phase P1 as shown in Figure 5:
Under the control of the first signal end IN1, the first input circuit 10 extremely pulls up the voltage output of first voltage end V1
Node PU.Under the control of pull-up node PU, output circuit 30 is defeated by the clock signal (low-potential signal) of clock signal terminal CLK
Out to signal output end OUTPUT.
When circuit each in above-mentioned shift register cell structure as shown in figure 3 or 4, and the transistor in each circuit
When being N-type transistor, as shown in figure 5, in input phase P1, clock signal terminal CLK input low level, the first signal end
IN1 input high level, second signal end IN2 input low level, third signal end IN3 input low level, the 4th voltage end V4 are defeated
Enter high voltage, pull-up node PU is high level, and signal output end OUTPUT exports low level.
Based on this, the first signal end IN1 input high level, high level of first input circuit 10 in the first signal end IN1
Control under by the high level output of first voltage end V1 to pull-up node PU.Specifically, above-mentioned each in input phase P1
The break-make situation of transistor in a circuit are as follows: since the first signal end IN1 exports high level, third transistor M3 is connected,
Thus by the high level output of first voltage end V1 to pull-up node PU.Under the control of pull-up node PU, the 5th transistor M5
Conducting, by the low level output of clock signal terminal CLK to signal output end OUTPUT.
In addition, third signal end IN3 input low level, so that the first transistor M1 and second transistor M2 are turned off, the
Binary signal end IN2 input low level, so that the 4th transistor M4 ends.
In output stage P2:
Under the control of pull-up node PU, output circuit 30 is by the clock signal (high potential signal) of clock signal terminal CLK
It exports to signal output end OUTPUT, signal output end OUTPUT and exports gated sweep signal.
When circuit each in above-mentioned shift register cell structure as shown in figure 3 or 4, and the transistor in each circuit
When being N-type transistor, as shown in figure 5, in output stage P2, clock signal terminal CLK input high level, the first signal end
IN1 input low level, second signal end IN2 input low level, third signal end IN3 input low level, the 4th voltage end V4 are defeated
Enter high level；Pull-up node PU is high level, and signal output end OUTPUT exports high level.
Based on this, under the control of pull-up node PU high level, output circuit 30 is defeated by the high level of clock signal terminal CLK
Out to signal output end OUTPUT.Specifically, in output stage P2 in above-mentioned each circuit transistor break-make situation are as follows:
Since the first signal end IN1 exports low level, third transistor M3 is in off state.Capacitor C deposits input phase P1
The high level of storage charges to pull-up node PU, so that the 5th transistor M5 is kept it turned on.In the case, when
The high level of clock signal end CLK is exported by the 5th transistor M5 to signal output end OUTPUT.In addition, in the bootstrapping of capacitor C
(Bootstrapping) under acting on, the current potential of pull-up node PU is further increased, to maintain the 5th transistor M5 to be on
State so that the high level of clock signal terminal CLK can as gated sweep signal export to signal output end
On the grid line that OUTPUT is connected.
In addition, third signal end IN3 input low level, so that the first transistor M1 and second transistor M2 are turned off, the
Binary signal end IN2 input low level, so that the 4th transistor M4 ends.
The beneficial effect of driving method provided by the invention and the beneficial effect of above-mentioned driving circuit are all the same, herein no longer
It repeats.
The shift register cell further includes signal output end reset circuit 50, pull-down control circuit 60, pull-down circuit
70, when Dolby circuit 80, the driving method for example can be with are as follows:
Input phase P1 as shown in Figure 5:
Under the control of the first signal end IN1, the first input circuit 10 extremely pulls up the voltage output of first voltage end V1
Node PU.Under the control of pull-up node PU, output circuit 30 is defeated by the clock signal (low-potential signal) of clock signal terminal CLK
Out to signal output end OUTPUT.
In addition, under the control of pull-up node PU high potential, the current potential of pull-down node PD is pulled down for pull-down control circuit 60
To the low potential of tertiary voltage end V3.At this point, the second input circuit 20, pull-down circuit 70, Dolby circuit 80, pull-up node reset
Circuit 40 is not opened.
When circuit each in above-mentioned shift register cell structure as shown in figure 3 or 4, and the transistor in each circuit
When being N-type transistor, as shown in figure 5, in input phase P1, clock signal terminal CLK input low level, the first signal end
IN1 input high level, second signal end IN2 input low level, third signal end IN3 input low level, the 4th voltage end V4 are defeated
Enter high voltage, pull-up node PU is high level, and pull-down node PD is low level, and signal output end OUTPUT exports low level.
Based on this, the first signal end IN1 input high level, high level of first input circuit 10 in the first signal end IN1
Control under by the high level output of first voltage end V1 to pull-up node PU.Specifically, above-mentioned each in input phase P1
The break-make situation of transistor in a circuit are as follows: since the first signal end IN1 exports high level, third transistor M3 is connected,
Thus by the high level output of first voltage end V1 to pull-up node PU.Under the control of pull-up node PU, the 5th transistor M5
Conducting, by the low level output of clock signal terminal CLK to signal output end OUTPUT.
As shown in figure 3, under the control of pull-up node PU high potential, the 7th transistor M7 conducting, in the 4th voltage end V4
Under the control of high level, the 6th transistor M6 conducting, but since the breadth length ratio of the 7th transistor M7 channel is greater than the 6th transistor
The breadth length ratio of M6 channel, so that the current potential of pull-down node PD still can be pulled down to the low of tertiary voltage end V3 by the 7th transistor M7
Level.In the case, the tenth transistor M10 and the 11st transistor M11 are in off state.
As shown in figure 4, under the control of pull-up node PU high potential, the 7th transistor M7 and the 9th transistor M9 conducting,
Under the control of the 4th voltage end V4 high level, the 8th transistor M8 conducting, but due to the breadth length ratio of the 9th transistor M9 channel
Greater than the breadth length ratio of the 8th transistor M8 channel, so that the 6th transistor M6 grid is low level, the 6th transistor M6 of control is cut
Only, so that the current potential of pull-down node PD can still be pulled down to the low level of tertiary voltage end V3 by the 7th transistor M7.In this feelings
Under condition, the tenth transistor M10 and the 11st transistor M11 are in off state.
In addition, third signal end IN3 input low level, so that the first transistor M1 and second transistor M2 are turned off, the
Binary signal end IN2 input low level, so that the 4th transistor M4 ends.
In output stage P2:
Under the control of pull-up node PU, output circuit 30 is by the clock signal (high potential signal) of clock signal terminal CLK
It exports to signal output end OUTPUT, signal output end OUTPUT and exports gated sweep signal.
In addition, under the control of pull-up node PU high potential, the current potential of pull-down node PD is pulled down for pull-down control circuit 60
To the low potential of tertiary voltage end V3.At this point, at this stage, the first input circuit 10, the second input circuit 20, Dolby circuit
80, pull-down circuit 70 and pull-up node reset circuit 40 are not opened.
When circuit each in above-mentioned shift register cell structure as shown in figure 3 or 4, and the transistor in each circuit
When being N-type transistor, as shown in figure 5, in output stage P2, clock signal terminal CLK input high level, the first signal end
IN1 input low level, second signal end IN2 input low level, third signal end IN3 input low level, the 4th voltage end V4 are defeated
Enter high level；Pull-up node PU is high level, and pull-down node PD is low level, and signal output end OUTPUT exports high level.
Based on this, under the control of pull-up node PU high level, output circuit 30 is defeated by the high level of clock signal terminal CLK
Out to signal output end OUTPUT.Specifically, in output stage P2 in above-mentioned each circuit transistor break-make situation are as follows:
Since the first signal end IN1 exports low level, third transistor M3 is in off state.Capacitor C to pull-up node PU into
Row charging, so that the 5th transistor M5 is kept it turned on.In the case, the high level of clock signal terminal CLK passes through
5th transistor M5 is exported to signal output end OUTPUT.In addition, under bootstrapping (Bootstrapping) effect of capacitor C, on
The current potential of node PU is drawn further to increase, with the state for maintaining the 5th transistor M5 to be on, so that clock signal terminal
The high level of CLK can be exported to the grid line being connected with signal output end OUTPUT as gated sweep signal.
As shown in figure 3, under the control of pull-up node PU high potential, the 7th transistor M7 conducting, in the 4th voltage end V4
Under the control of high level, the 6th transistor M6 conducting, but since the breadth length ratio of the 7th transistor M7 channel is greater than the 6th transistor
The breadth length ratio of M6 channel, so that the current potential of pull-down node PD still can be pulled down to the low of tertiary voltage end V3 by the 7th transistor M7
Level.In the case, the tenth transistor M10 and the 11st transistor M11 are in off state.
As shown in figure 4, under the control of pull-up node PU high potential, the 7th transistor M7 and the 9th transistor M9 conducting,
Under the control of the 4th voltage end V4 high level, the 8th transistor M8 conducting, but due to the breadth length ratio of the 9th transistor M9 channel
Greater than the breadth length ratio of the 8th transistor M8 channel, so that the 6th transistor M6 grid is low level, the 6th transistor M6 of control is cut
Only, so that the current potential of pull-down node PD can still be pulled down to the low level of tertiary voltage end V3 by the 7th transistor M7.In this feelings
Under condition, the tenth transistor M10 and the 11st transistor M11 are in off state.
In addition, third signal end IN3 input low level, so that the first transistor M1 and second transistor M2 are turned off, the
Binary signal end IN2 input low level, so that the 4th transistor M4 ends.
Drop-down stage P3:
Under the control of second signal end IN2, the second input circuit 20 extremely pulls up the voltage output of second voltage end V2
Node PU, control output circuit 30 are closed.Under the control of pull-up node PU, pull-down control circuit 60 is defeated by the 4th voltage end V4
The cut-in voltage (high level signal) entered is exported to pull-down node PD.Under the control of pull-down node PD, pull-down circuit 70 is by
The voltage output of three voltage end V3 to signal output end OUTPUT, Dolby circuit 80 by by the voltage output of tertiary voltage end V3 extremely
Pull-up node PU.
In addition, at this stage, the first input circuit 10, the second input circuit 20, pull-up node reset circuit 40 are not opened
It opens.
When circuit each in above-mentioned shift register cell structure as shown in figure 3 or 4, and the transistor in each circuit
When being N-type transistor, as shown in figure 5, in drop-down stage P3, clock signal terminal CLK input low level, the first signal end
IN1 input low level, second signal end IN2 input high level；Pull-up node PU is low level, and pull-down node PD is high level,
Signal output end OUTPUT exports low level.
Based on this, pull-down control circuit 60 saves the high level output of the 4th voltage end V4 to pull-down node PD in drop-down
Under the control of point PD, pull-down circuit 70 is by the low level output of tertiary voltage end V3 to signal output end OUTPUT, Dolby circuit
80 by the low level output of tertiary voltage end V3 to pull-up node PU.Specifically, above-mentioned each circuit in drop-down stage P3
The break-make situation of middle transistor are as follows: since second signal end IN2 exports high level, the 4th transistor M4 conducting, thus will pull-up
The current potential of node PU is pulled down to the low level of second voltage end V2, and the 5th transistor M5 is in off state.
As shown in figure 3, the 7th transistor M7 cut-off, the 6th transistor M6 exists under the control of pull-up node PU low potential
It is connected under the control of 4th voltage end V4 high level, and by the high level output of the 4th voltage end V4 to pull-down node PD, under
Under the control for drawing node PD high potential, the tenth transistor M10 and the 11st transistor M11 are both turned on, and pass through the 11st transistor
The current potential of pull-up node PU is pulled down to the low level of tertiary voltage end V3 by M11, and is exported signal by the tenth transistor M10
The current potential of end OUTPUT is pulled down to the low level of tertiary voltage end V3.
As shown in figure 4, the 7th transistor M7 and the 9th transistor M9 are cut under the control of pull-up node PU low potential
Only, the 8th transistor M8 is connected under the control of the 4th voltage end V4 high level, and by the high level output of the 4th voltage end V4
To the grid of the 6th transistor M6, the 6th transistor M6 conducting is controlled, the 6th transistor M6 is by the high level of the 4th voltage end V4
Output is to pull-down node PD, and under the control of pull-down node PD high potential, the tenth transistor M10 and the 11st transistor M11 are equal
The current potential of pull-up node PU, is pulled down to the low level of tertiary voltage end V3 by the 11st transistor M11 by conducting, and passes through the
The current potential of signal output end OUTPUT is pulled down to the low level of tertiary voltage end V3 by ten transistor M10.
In addition, the first signal end IN1 input low level, so that third transistor M3 ends；Third signal end IN3 input is low
Level, so that the first transistor M1 and second transistor M2 are turned off.
Reseting stage P4:
Under the control of third signal end IN3, pull-up node reset circuit 40 by the voltage output of tertiary voltage end V3 extremely
Pull-up node PU resets pull-up node PU, and control output circuit 30 is closed；Signal output end reset circuit 50 is by third
The voltage output of voltage end V3 resets signal output end OUTPUT to signal output end OUTPUT.
At this point, at this stage, the first input circuit 10, the second input circuit 20, pull-down control circuit 60, pull-down circuit 70
It is not opened with Dolby circuit 80.
When circuit each in above-mentioned shift register cell structure as shown in figure 3 or 4, and the transistor in each circuit
When being N-type transistor, as shown in figure 5, in reseting stage P4, the first signal end IN1 input low level, second signal end IN2
Input low level, third signal end IN3 input high level, the 4th voltage end V4 input low level；Pull-up node PU is low level,
Pull-down node PD is low level, and signal output end OUTPUT exports low level.
Based on this, the high level of clock signal terminal CLK can not be exported, under the control of third signal end IN3, pull-up node
The voltage of pull-up node PU is pulled down to the low level of tertiary voltage end V3 by reset circuit 40.Specifically, in reseting stage P4
In in above-mentioned each circuit transistor break-make situation are as follows: third signal end IN3 enters and leaves high level, and the first transistor M1 is led
It is logical, make the first transistor M1 that the low level of tertiary voltage end V3 is input to pull-up node PU, is cut with controlling the 5th transistor M5
Only；Third signal end IN3 enters and leaves high level, and second transistor M2 is connected, makes second transistor M2 by tertiary voltage end V3's
Low level is input to signal output end OUTPUT, resets to signal output end OUTPUT.
In addition, this stage, in addition to the first transistor M1 and second transistor M2 is connected, remaining transistor is in cut-off shape
State.
It should be noted that first, as shown in fig. 6, for afterbody shift register cell, third signal end
After IN3 inputs open signal, until next frame starts, second signal end IN2 could input open signal, that is to say, that most
Rear stage shift register cell is in the aforementioned four stage, can be advanced after having executed input phase P1 and output stage P2
Row reseting stage P4, then carries out drop-down stage P3 again；And for other grade of shift register cell, from input phase P1
It is successively executed to reseting stage P4.So, the waveform diagram of pull-up node PU point current potential is as shown in fig. 7, afterbody shifts
The pull-up node of register cell until next frame starts without being pulled low, but the reseting stage P4 after this frame end is opened
It is directly pulled low when the beginning.
Second, when there is no signal output end reset circuit 50 in shift register cell, will be closed in above-mentioned driving method
It is all removed in the step of Dolby circuit 80, remaining step does not change.
The driving method of shift register cell provided in an embodiment of the present invention, its advantages and above-mentioned shift register
Unit is identical, and details are not described herein again.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (15)
1. a kind of shift register cell, which is characterized in that including the first input circuit, the second input circuit, output circuit and
Pull-up node reset circuit；
First input circuit connects the first signal end, first voltage end, pull-up node, in first signal end
Control under, by the voltage output at the first voltage end to the pull-up node；
Second input circuit connects second signal end, second voltage end, the pull-up node, in second letter
Number end control under, by the voltage output at the second voltage end to the pull-up node；
The output circuit connects clock signal terminal, the pull-up node, signal output end, in the pull-up node
Under control, by the voltage output of the clock signal terminal to the signal output end；
The pull-up node reset circuit connects third signal end, tertiary voltage end, the pull-up node, for described the
Under the control of three signal ends, by the voltage output at the tertiary voltage end to the pull-up node.
2. shift register cell according to claim 1, which is characterized in that the shift register cell further includes letter
Number output end reset circuit；
The signal output end reset circuit connects the third signal end, the tertiary voltage end, the signal output end,
For under the control of the third signal end, by the voltage output at the tertiary voltage end to the signal output end.
3. shift register cell according to claim 1, which is characterized in that under the shift register cell further includes
Draw control circuit, pull-down circuit, Dolby circuit；
The pull-down control circuit connects tertiary voltage end, the 4th voltage end, the pull-up node, pull-down node, for institute
The level for stating pull-down node is controlled；
The pull-down circuit connects the pull-down node, the tertiary voltage end, the signal output end, under described
Under the control for drawing node, by the voltage output at the tertiary voltage end to the signal output end；
The Dolby circuit connects the pull-down node, the tertiary voltage end, the pull-up node, in the drop-down
The control of node is by the voltage output at the tertiary voltage end to the pull-up node.
4. shift register cell according to claim 1, which is characterized in that the pull-up node reset circuit includes the
One transistor；
The grid of the first transistor connects the third signal end, and the first pole connects the tertiary voltage end, and the second pole connects
Connect the pull-up node.
5. shift register cell according to claim 2, which is characterized in that the signal output end reset circuit includes
Second transistor；
The grid of the second transistor connects the third signal end, and the first pole connects the tertiary voltage end, and the second pole connects
Connect the signal output end.
6. shift register cell according to claim 1, which is characterized in that first input circuit includes third crystalline substance
Body pipe；Second input circuit includes the 4th transistor；
The grid of the third transistor connects first signal end, and the first pole connects the first voltage end, and the second pole connects
Connect the pull-up node；
The grid of 4th transistor connects the second signal end, and the first pole connects the second voltage end, and the second pole connects
Connect the pull-up node.
7. shift register cell according to claim 1, which is characterized in that the output circuit includes the 5th transistor
And capacitor；
The grid of 5th transistor connects the pull-up node, and the first pole connects the clock signal terminal, the connection of the second pole
The second end of the signal output end and the capacitor；
The first end of the capacitor connects the pull-up node, and second end is also connected with the signal output end.
8. shift register cell according to claim 3, which is characterized in that the pull-down control circuit includes the 6th brilliant
Body pipe, the 7th transistor；
The grid of 6th transistor connects the 4th voltage end, and the first pole connects the 4th voltage end, and the second pole connects
Connect the pull-down node；
The grid of 7th transistor connects the pull-up node, and the first pole connects the tertiary voltage end, the connection of the second pole
The pull-down node.
9. shift register cell according to claim 8, which is characterized in that the pull-down control circuit further includes the 8th
Transistor, the 9th transistor；
The grid of 8th transistor connects the 4th voltage end, and the first pole connects the 4th voltage end, and the second pole connects
Connect the grid of the 6th transistor；
The grid of 9th transistor connects the pull-up node, and the first pole connects the tertiary voltage end, the connection of the second pole
The grid of 6th transistor.
10. shift register cell according to claim 3, which is characterized in that the pull-down circuit includes the tenth crystal
Pipe；The Dolby circuit includes the 11st transistor；
The grid of tenth transistor connects the pull-down node, and the first pole connects the tertiary voltage end, the connection of the second pole
The signal output end；
The grid of 11st transistor connects the pull-down node, and the first pole connects the tertiary voltage end, and the second pole connects
Connect the pull-up node.
11. a kind of gate driving circuit, which is characterized in that including at least two-stage cascade as described in claim any one of 1-10
Shift register cell；
First signal end of first order shift register cell is connected with initial signal end；
Other than the first order shift register cell, the signal output end and next stage of upper level shift register cell
First signal end of shift register cell is connected；
Other than afterbody shift register cell, the signal output end and upper level of next stage shift register cell are moved
The second signal end of bit register unit is connected；
The second signal end of the afterbody shift register cell connects the initial signal end.
12. a kind of display device, which is characterized in that including the gate driving circuit described in claim 11.
13. a kind of for driving the driving method of the described in any item shift register cells of claim 1-10, feature exists
In, which comprises
Input phase:
Under the control of the first signal end, the first input circuit is by the voltage output at first voltage end to pull-up node；
Output stage:
Under the control of the pull-up node, the output circuit exports the clock signal of the clock signal terminal to the letter
Number output end, the signal output end export gated sweep signal.
14. driving method according to claim 13, which is characterized in that the shift register cell further includes drop-down control
Circuit processed, pull-down circuit, Dolby circuit；
The method also includes:
The drop-down stage:
Under the control at second signal end, the second input circuit controls the voltage output at second voltage end to the pull-up node
The output circuit is made to close；
Under the control of the pull-up node, the pull-down control circuit exports the cut-in voltage that the 4th voltage end inputs under
Draw node；
Under the control of the pull-down node, the pull-down circuit is by the voltage output at tertiary voltage end to signal output end；Institute
Dolby circuit is stated by the voltage output at the tertiary voltage end to the pull-down node.
15. a kind of for driving the driving method of gate driving circuit described in claim 11, which is characterized in that the method
Include:
In a picture frame:
The first order shift register cell of gate driving circuit receives the initial signal at initial signal end, opens grid step by step and drives
Shift register cell in dynamic circuit；
Between two picture frames:
All shift register cells in gate driving circuit receive the open signal of third signal end, while resetting all shiftings
The pull-up node of bit register unit.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710910077.6A CN107464521B (en) | 2017-09-29 | 2017-09-29 | Shift register cell, gate driving circuit and driving method, display device |
| US16/336,274 US11315472B2 (en) | 2017-09-29 | 2018-07-06 | Shift register unit, gate driving circuit and driving method thereof, display device |
| PCT/CN2018/094849 WO2019062265A1 (en) | 2017-09-29 | 2018-07-06 | Shift register unit, gate driving circuit and driving method, and display device |
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| CN201710910077.6A CN107464521B (en) | 2017-09-29 | 2017-09-29 | Shift register cell, gate driving circuit and driving method, display device |
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| CN107464521B (en) * | 2017-09-29 | 2019-09-20 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit and driving method, display device |
| CN108154835B (en) | 2018-01-02 | 2020-12-25 | 京东方科技集团股份有限公司 | Shifting register unit, driving method thereof, grid driving circuit and display device |
| CN107945762A (en) * | 2018-01-03 | 2018-04-20 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| CN107978265B (en) * | 2018-01-22 | 2021-01-26 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN108428469B (en) * | 2018-03-19 | 2021-01-26 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN110299116B (en) * | 2018-03-23 | 2021-01-26 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN108399906B (en) | 2018-05-25 | 2021-01-26 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit and display device |
| CN108766358B (en) * | 2018-06-12 | 2020-01-10 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN108665846B (en) * | 2018-07-13 | 2022-01-28 | 京东方科技集团股份有限公司 | Shift register unit, grid driving circuit, display device and driving method |
| CN110246447A (en) * | 2019-06-18 | 2019-09-17 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN110459185B (en) * | 2019-07-19 | 2021-09-17 | 信利半导体有限公司 | Low-noise GOA (Gate driver on array) driving circuit, driving method and display device |
| CN110675803B (en) * | 2019-11-14 | 2023-06-23 | 京东方科技集团股份有限公司 | Shift register unit and driving method thereof, grid driving circuit and display device |
| CN110706639A (en) * | 2019-11-15 | 2020-01-17 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN210865579U (en) | 2020-02-24 | 2020-06-26 | 北京京东方显示技术有限公司 | Shift register circuit, gate drive circuit and display device |
| CN111210789B (en) * | 2020-02-25 | 2022-03-04 | 合肥京东方光电科技有限公司 | Shift register, driving method, gate driving circuit and display panel |
| CN114586089A (en) * | 2020-09-28 | 2022-06-03 | 京东方科技集团股份有限公司 | Shift register, driving method, light-emitting control driving circuit and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20150052633A (en) * | 2013-11-06 | 2015-05-14 | 에스케이하이닉스 주식회사 | Serializer |
| CN106023874A (en) * | 2016-07-29 | 2016-10-12 | 上海中航光电子有限公司 | Bidirectional scanning unit, driving method and grid driving circuit |
| CN106057147A (en) * | 2016-06-28 | 2016-10-26 | 京东方科技集团股份有限公司 | Shift register unit and driving method thereof, grid drive circuit, and display device |
| CN106128364A (en) * | 2016-07-15 | 2016-11-16 | 京东方科技集团股份有限公司 | Shift register cell and driving method, gate driver circuit, display device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101777386B (en) * | 2010-01-06 | 2013-04-24 | 友达光电股份有限公司 | Shift register circuit |
| CN104637462A (en) * | 2015-03-17 | 2015-05-20 | 合肥京东方光电科技有限公司 | Shifting register unit, driving method thereof, grid drive circuit and display device |
| CN104866141B (en) * | 2015-06-10 | 2018-03-23 | 京东方科技集团股份有限公司 | Touch drive circuit, display device and its driving method |
| CN105976755B (en) * | 2016-07-19 | 2018-07-10 | 京东方科技集团股份有限公司 | A kind of display driver circuit and its control method, display device |
| CN107464521B (en) | 2017-09-29 | 2019-09-20 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit and driving method, display device |
-
2017
- 2017-09-29 CN CN201710910077.6A patent/CN107464521B/en active Active
-
2018
- 2018-07-06 WO PCT/CN2018/094849 patent/WO2019062265A1/en active Application Filing
- 2018-07-06 US US16/336,274 patent/US11315472B2/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20150052633A (en) * | 2013-11-06 | 2015-05-14 | 에스케이하이닉스 주식회사 | Serializer |
| CN106057147A (en) * | 2016-06-28 | 2016-10-26 | 京东方科技集团股份有限公司 | Shift register unit and driving method thereof, grid drive circuit, and display device |
| CN106128364A (en) * | 2016-07-15 | 2016-11-16 | 京东方科技集团股份有限公司 | Shift register cell and driving method, gate driver circuit, display device |
| CN106023874A (en) * | 2016-07-29 | 2016-10-12 | 上海中航光电子有限公司 | Bidirectional scanning unit, driving method and grid driving circuit |
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| US11315472B2 (en) | 2022-04-26 |
| CN107464521A (en) | 2017-12-12 |
| US20210366351A1 (en) | 2021-11-25 |
| WO2019062265A1 (en) | 2019-04-04 |
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