CN107301833B - Gate driving unit, gate driving circuit, driving method of gate driving circuit and display device - Google Patents
Gate driving unit, gate driving circuit, driving method of gate driving circuit and display device Download PDFInfo
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- CN107301833B CN107301833B CN201710736643.6A CN201710736643A CN107301833B CN 107301833 B CN107301833 B CN 107301833B CN 201710736643 A CN201710736643 A CN 201710736643A CN 107301833 B CN107301833 B CN 107301833B
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The invention relates to a grid driving unit, a grid driving circuit, a driving method thereof and a display device, wherein the grid driving unit comprises: a pull-up module controlling a level of an output signal of the output terminal in response to a signal level of the pull-up control node; an input module which outputs an input control signal to a pull-up control node in response to a pull-up control signal; a denoising module which cancels noise of the pull-up control node in response to a level of the noise control node; a noise control module outputting a noise control signal to a noise control node in response to the noise control driving signal; and a reset module resetting a level of the pull-up control node in response to a reset control signal. Wherein the input module and the noise control module are configured to pull the pull-up control node down to a low level before pulling up the level of the noise control node. The invention can prevent the pull-up control node and the noise control node in the gate drive unit from being in high level at the same time, thereby improving the display effect.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a gate driving unit and a gate driving circuit and a driving method thereof, and a display device.
Background
In the existing display panel technology, in order to achieve low cost and narrow frame, a goa (gate driver On array) technology is adopted for many products, that is, a gate driving circuit is integrated inside a panel through a thin film transistor process, so that the advantages of reducing IC and assembly cost and the like are achieved. In addition, the Gate bias time of each thin film transistor in the GOA circuit is mainly considered during design, and the situation that the GOA circuit fails due to overlarge threshold voltage shift (Vth shift) to cause the working life to meet design requirements is prevented. Otherwise, the GOA circuit is prone to failure and the lifetime is reduced. From the aspects of user comfort, operability and the like, narrow frames, low power consumption and high stability are the development trend of the current LCD products.
Disclosure of Invention
To solve the defects in the prior art, aspects of the present invention provide a gate driving unit and a gate driving circuit and a driving method thereof, and a display device.
According to an aspect of the present invention, a gate driving unit includes: a pull-up module controlling a level of an output signal of the output terminal in response to a signal level of the pull-up control node; an input module to output an input control signal to the pull-up control node in response to a pull-up control signal; a denoising module which cancels noise of the pull-up control node in response to a level of a noise control node; a noise control module outputting a noise control signal to the noise control node in response to a noise control driving signal; and a reset module that resets a level of the pull-up control node in response to a reset control signal. The input module and the noise control module are configured to pull the pull-up control node down to a low level before pulling the level of the noise control node.
Optionally, the denoising module further removes signal noise of the output terminal in response to the noise control signal.
Optionally, the noise control module includes a first noise control module that pulls down the noise control node to a low level before a signal level of the pull-up control node is pulled up.
Optionally, the noise control module includes a second noise control module, and the noise control node is pulled up after the signal level of the pull-up control node is pulled down to a low level.
According to another aspect of the present invention, a gate driving circuit includes a plurality of gate driving units according to the present invention cascaded.
According to still another aspect of the present invention, a method of driving a gate driving circuit includes:
in a first time period, a starting signal pulls up the level of a pull-up control node through an input module, and simultaneously pulls down the level of a noise control node;
in a second time period, the first clock signal is increased, the pull-up control node transmits the high level of the first clock signal to the output end through the pull-up control module, and meanwhile, the input module continues to pull down the level of the noise control node;
in the third time period, the reset signal pulls down the level of the pull-up control node through the reset module, and the electric charge at the output end is discharged through the pull-up module.
Optionally, in the first time period, the pull-up control signal of the nth-1 stage gate driving unit is input to the noise control module of the nth stage gate driving unit as the noise control driving signal of the nth stage gate driving unit, and the level of the noise control node of the nth stage gate driving unit is pulled down, where n is a positive integer.
Optionally, in the first time period, the output signal of the nth-4 th stage gate driving unit is input to the noise control module of the nth stage gate driving unit as the noise control driving signal of the nth stage gate driving unit, and the level of the noise control node of the nth stage gate driving unit is pulled down, where n is a positive integer.
Optionally, in a third time period, the pull-up control signal of the (n + 1) th stage gate driving unit is input to the noise control module of the nth stage gate driving unit as the noise control driving signal of the nth stage gate driving unit, and the level of the noise control node of the nth stage gate driving unit is pulled up, where n is a positive integer.
Optionally, in the second period, the pull-up control signal of the (n + 1) th stage gate driving unit is input to the pull-up module of the nth stage gate driving unit as a signal of the pull-up control node of the nth stage gate driving unit, where n is a positive integer.
Optionally, in a third period, the output signal of the (n + 4) th stage gate driving unit is used as a reset signal of the nth stage gate driving unit to reset the level of the pull-up control node of the nth stage gate driving unit, where n is a positive integer.
Optionally, the signal duty cycle of the first clock signal is less than 50%.
Optionally, the signal duty cycle of the first clock signal is between 40% -50%.
Optionally, the activation signal comprises a pulsed activation signal.
According to an aspect of the present invention, there is provided a display device including the gate driving circuit according to the present invention.
According to a gate driving unit and a gate driving circuit of the present invention, the gate driving unit includes: a pull-up module controlling a level of an output signal of the output terminal in response to a signal level of the pull-up control node; an input module to output an input control signal to the pull-up control node in response to a pull-up control signal; a denoising module which cancels noise of the pull-up control node in response to a level of a noise control node; a noise control module outputting a noise control signal to the noise control node in response to a noise control driving signal; and a reset module that resets a level of the pull-up control node in response to a reset control signal. The input module and the noise control module are configured to pull the pull-up control node down to a low level before pulling the level of the noise control node. Therefore, the noise control module and the input module of the gate driving unit can be optimized, so that the pull-up control node and the noise control node of the same gate driving unit can be prevented from being simultaneously at a high level on the basis of keeping the maximum bias time of the TFT, the charging of the pull-up control node and the leakage current of a clock signal are prevented from being influenced, the delay of an output signal can be reduced, the power consumption of the gate driving circuit is reduced, and the stability of the gate driving circuit is improved. Therefore, the gate driving circuit can have better service life, better power consumption performance and better working stability.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic block diagram of a gate driving unit;
FIG. 2 is a schematic circuit diagram of one particular implementation of the gate drive unit of FIG. 1;
FIG. 3 is a schematic timing diagram for the circuit of FIG. 2;
fig. 4 is a schematic diagram of a gate driving circuit constituted by the gate driving unit of fig. 2;
fig. 5 is a schematic circuit diagram of a specific implementation of a gate driving unit according to an embodiment of the present invention;
FIG. 6 is a schematic timing diagram for the circuit of FIG. 5;
fig. 7 is a schematic diagram of a gate driving circuit constituted by the gate driving unit of fig. 5;
fig. 8 is a schematic circuit diagram of a specific implementation of a gate driving unit according to an embodiment of the present invention;
fig. 9 is a schematic circuit diagram of a specific implementation of a gate driving unit according to an embodiment of the present invention; and
fig. 10 is a schematic circuit diagram of a specific implementation of a gate driving unit according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present disclosure, a gate driving unit and a gate driving circuit provided in the present disclosure are described in further detail below with reference to the accompanying drawings and the detailed description.
Fig. 1 is a schematic block diagram of a gate driving unit, fig. 2 is a schematic circuit diagram of a specific implementation of the gate driving unit of fig. 1, fig. 3 is a schematic timing diagram for the circuit of fig. 2, and fig. 4 is a schematic diagram of a gate driving circuit constituted by the gate driving unit of fig. 2. Referring to fig. 1 to 4, the gate driving circuit may employ a dc noise reduction mode.
In this example, a group of GOA circuits composed of 6 clock signals CLK is taken as an example for explanation, and the GOA circuits composed of the groups of clock signals generally operate independently of each other without affecting each other. However, the present invention is not limited thereto. For example, in practical applications, a circuit layout such as 8CLK or 10CLK may be used depending on the actual load requirements and refresh rate.
Generally, the GOA circuit implements a shift register function, which is used to provide a pulse signal with a certain width to all gate lines row by row in a frame, the time width of the pulse signal is generally one to several times of the charging time allocated to each row, and the waveform is generally a square wave. The source electrode driving circuit can provide correct video signal voltage for each pixel line by matching with the generation time of the grid line pulse, thereby realizing the normal display of the picture.
Generally, in order to facilitate design and production, a GOA circuit has a minimum GOA unit circuit, and a single-side driving method is generally adopted for small and medium-sized display products, such as mobile phones, tablet computers, and the like, that is, one GOA unit circuit is used for driving corresponding to a gate line in each row, one side drives a gate line in an odd-numbered row, the other side drives a gate line in an even-numbered row, and both sides are alternately turned on. In large and medium size display products, such as notebook computers (Note books), monitors (monitors), TVs, etc., a bilateral driving method is generally adopted, i.e., one gate line is driven by using two GOA unit circuits on the left and right, and the GOA unit circuits on both sides simultaneously output identical pulse signals to the gate line, so as to reduce the delay time of output.
In the above manner, during the operation, each GOA unit circuit outputs a pulse signal to its corresponding gate line in each frame.
The control signals of the GOA unit circuit generally include an enable signal (INPUT), a clock signal (CLK), a low level signal (VGL), a RESET signal (RESET), and an optional high level (VGH) signal. The start signal is generally generated by the GOA of the line preceding the GOA of the current line, and for the first GOA unit or units, the system provides a dedicated square wave signal as an INPUT signal for each frame to which a pulsed start signal, generally referred to as an STV signal, is provided at the beginning of each frame.
The OUTPUT signal of the GOA unit circuit is generally an OUTPUT signal (OUTPUT) provided to the gate line, and a start signal of the GOA unit circuit below the gate line, which may share the gate line OUTPUT signal OUTPUT, or may be a separately generated start signal (the last GOA unit does not need to OUTPUT an INPUT signal, and its reset signal is also provided by the system, or a dedicated reset circuit may be made to provide a reset signal to it, and the circuit generally consists of a plurality of transistors, and the occupied area is smaller than the area of one GOA unit circuit).
In a-Si or oxide process, etc. a-a circuits that cannot implement cmos devices generally adopt a boot-mapping structure, which generally has 2 important nodes, a pull-up node pu (pulling up) and a pull-down node pd (pulling down), and these 2 nodes generally adopt a design structure of reciprocal inverter (inverter), which will be described in detail below.
Referring to fig. 1, the gate driving unit according to the present embodiment may include: a pull-up module 110 controlling a level of an Output signal of the Output terminal Output in response to a signal level of the pull-up control node PU; an input module 120 outputting an input control signal STV to a pull-up control node PU in response to a pull-up control signal; a denoising module 130, 140 which cancels noise of the pull-up control node PU in response to a level of the noise control node PD; a noise control module 150 outputting a noise control signal GCH to a noise control node PD in response to the noise control driving signal; and a reset module 160 resetting a level of the pull-up control node PU in response to a reset control signal RST _ PU. In addition, the gate driving circuit may further include a pull-down block 170 controlling a level of an Output signal of the Output terminal Output in response to a pull-down control signal GCL.
In the specific implementation circuit shown in fig. 2, M1(M denotes a switching element, which may be a transistor, for example), M6 and M8 may constitute the input module 120, M5 and M9 may constitute the noise control module 150, M3 may constitute the pull-up module 110, M2 may constitute the reset module 160, M4 may constitute the pull-down module 170, and M10 and M11 may constitute the noise control modules 130 and 140, respectively. The operation of the circuit shown in fig. 2 will be described in more detail below in conjunction with the timing diagram shown in fig. 3.
As shown in fig. 3, the first phase is an input phase, the STV signal pulls up the PU point of the pull-up control node through the input module, and pulls down the signal (including the PD point) related to the noise control module.
And the second phase is an Output phase, the first clock signal CLK is increased, the pull-up control node PU transmits the high level of the first clock signal CLK to the Output terminal Output through the pull-up control module, and the Output terminal Output can be connected to a gate line in the display panel, so that the gate line voltage becomes the high level, and at this time, a pixel in the display panel starts to be charged to a required voltage to display a normal video signal. While the input module continues to pull the noise control module related signal (including the noise control point PD) low.
And the third stage is a reset stage, the reset signal RST _ PU pulls down the PU point through a reset module, and the electric charge at the Output end Output can be discharged through an upward pulling module. The duty ratio of the first clock signal CLK is less than 50% (between 40% and 50%), and OUTPUT discharge is performed through M3 after a row of GOA is OUTPUT.
In one frame, the first step and the second step work periodically. The GCH high-level denoising is adopted, the denoising capability is good, in the display period, the noise control node PD controls the high level all the time, and the denoising TFT takes a rest in the Blanking time (Blanking time). The GCL discharges the output outputs of all rows during Blanking (Blanking) through M4.
In the timing sequence of fig. 3, the first clock signal CLK and the second clock signal CLKB output reciprocal square wave signals and are alternately used as the first clock signal CLK and the second clock signal CLKB of the GOA unit, thereby implementing the function of outputting the gate row by row.
In the gate driving circuit shown in fig. 4, a plurality of gate driving units according to the foregoing embodiments are cascaded with each other, and a high level GCH is employed as a control signal. Since the first clock signal CLK is the highest frequency signal of the GOA control signals, the power consumption of the GOA unit is mostly the power consumption generated by charging and discharging the capacitive load on the first clock signal CLK signal. Therefore, this approach still has certain problems.
For example, in the period of time of fig. 3, the pull-up control node PU is required to pull down the noise control node PD and the control node PD _ CN of the noise control module, when switches (e.g., TFTs) such as M6 and M8 are too small, M10 is too large, or process differences cause mobility of M6 and M8 to be too small, and mobility of M10 to be too large, the pull-down speed of the noise control node PD is too slow, the pull-up speed of the pull-up control node PU point is too slow, and the pull-up control node PU cannot reach a set value in the period of time of t, which affects charging.
In the period of time c in fig. 3, when the switches (e.g., TFTs) of M6, M8, etc. are too large, M11, M10 are too small, or when the mobility of M6, M8, M3 is too large due to process variation, M10, M11 is too small, the pull-down speed of the PU voltage of the pull-up control node is too slow, and the pull-up speed of the PD voltage of the noise control node is too slow, so that the first clock signal CLK is shorted to the VSS signal through M3, M11, etc., resulting in power loss.
In another embodiment of the present invention, the input module 120 and the noise control module 150 are configured to pull the pull-up control node PU down to a low level before pulling the level of the noise control node PD.
According to the present embodiment, the denoising module may include a first denoising module 130 and a second denoising module 140, wherein the first denoising module 130 may remove noise of the pull-up control node PU in response to a level of the noise control node PD, and the second denoising module 140 may remove signal noise of the Output terminal Output in response to the noise control signal.
More specifically, the present invention will be described in detail below with reference to further examples thereof. Fig. 5 is a schematic circuit diagram of a specific implementation of a gate driving unit according to an embodiment of the present invention, fig. 6 is a schematic timing diagram for the circuit of fig. 5, fig. 7 is a schematic diagram of a gate driving circuit composed of the gate driving unit of fig. 5, and as shown in fig. 7, the gate driving circuit according to the present embodiment includes a plurality of cascaded gate driving units.
Referring to fig. 5 to 7, the circuit structures of the gate driving unit and the gate driving circuit according to this embodiment are substantially the same as those of the previous embodiments, and the differences are mainly: the signal Prior _ PU of the pull-up control node of the previous gate drive unit (GOA) is used as a control signal to be input to the gates of M6 and M8, so that the noise control node PD and the control node PD _ CN of the noise control module can be reduced to low level in the time period of (i), and the pull-up control node PU of the current gate drive unit can be pulled up conveniently. In addition, the pull-up control node PU of the current stage gate driving unit controls only M3 of the GOA unit of the current row during the current stage time. In addition, the signal Next _ PU of the pull-up control node of the Next stage is input to the gates of M6 'and M8' as a control signal, so that the pull-up of the noise control node PD is delayed in a period of time (c), and the first clock signal CLK leakage caused by the fact that the pull-up control node PU and the noise control node PD of the current stage gate driving unit are high at the same time is avoided.
According to the present embodiment, the voltage of the noise control node PD of the previous stage gate driving unit is controlled by the voltage (Prior _ PU) of the pull-up control node PU of the previous stage gate driving unit, so that the voltage of the noise control node PD of the previous stage gate driving unit is reduced before the pull-up control node PU of the previous stage gate driving unit is pulled up, and thus the pull-up control node PU of the previous stage gate driving unit can be pulled up better and faster.
In addition, according to the present embodiment, the voltage pull-up time point of the noise control node PD of the preceding stage gate driving unit is controlled with the voltage (Next _ PU) of the pull-up control node PU of the Next stage gate driving unit, and the noise control node PD point voltage pull-up of the preceding stage gate driving unit is delayed. First, after the pull-up control node PU of the previous stage gate driving unit is completely pulled down and M3 is completely turned off, then, the pull-up control node (Next _ PU) of the Next stage gate driving unit is pulled down, so that M6 'and M8' are turned off, so that the noise control node PD of the current stage gate driving unit no longer passes through the ground (VSS), and starts to be pulled up. The leakage caused by the fact that the first clock signal CLK is short-circuited to VSS through M3 and M11 due to the simultaneous high level of the pull-up control node PU and the noise control node PD of the preceding stage gate driving unit caused by the delay is avoided.
In addition, according to the present embodiment, the Output of the (N + 4) th-stage gate driving unit is used as the Reset (Reset) signal of the pull-up control node PU of the nth-stage gate driving unit, so that the GOA discharge time in the period of time (c) can be increased.
In the present embodiment, the switching elements M8 and M6 may constitute a first noise control block that pulls down the noise control node PD to a low level before the signal level of the pull-up control node PU is pulled up.
In addition, the switching elements M8 'and M6' may constitute a second noise control block that pulls up the noise control node PU after the signal level thereof is pulled down to a low level.
In other words, in the gate driving circuit according to the present embodiment, the pull-up control signal of the n-1 th stage gate driving unit is input to the noise control block of the nth stage gate driving unit as the noise control driving signal of the nth stage gate driving unit, and the level of the noise control node of the nth stage gate driving unit is pulled down, where n is a positive integer.
In addition, in the gate driving circuit according to the present embodiment, the output signal of the n +4 th stage gate driving unit resets the level of the pull-up control node of the nth stage gate driving unit as the reset signal of the nth stage gate driving unit, where n is a positive integer.
Therefore, according to a gate driving unit and a gate driving circuit of the present invention, the gate driving unit includes: a pull-up module controlling a level of an output signal of the output terminal in response to a signal level of the pull-up control node; an input module to output an input control signal to the pull-up control node in response to a pull-up control signal; a denoising module which cancels noise of the pull-up control node in response to a level of a noise control node; a noise control module outputting a noise control signal to the noise control node in response to a noise control driving signal; and a reset module that resets a level of the pull-up control node in response to a reset control signal. The input module and the noise control module are configured to pull the pull-up control node down to a low level before pulling the level of the noise control node. Therefore, the noise control module and the input module of the gate driving unit can be optimized, so that the pull-up control node and the noise control node of the same gate driving unit can be prevented from being simultaneously at a high level on the basis of keeping the maximum bias time of the TFT, the charging of the pull-up control node and the leakage current of a clock signal are prevented from being influenced, the delay of an output signal can be reduced, the power consumption of the gate driving circuit is reduced, and the stability of the gate driving circuit is improved. Therefore, the gate driving circuit can have better service life, better power consumption performance and better working stability.
The circuit of the NMOS TFT process is described in the above embodiments, but the present invention is obviously also a circuit structure for the PMOS TFT process. For example, in a PMOS TFT circuit structure, the respective operating voltages and timings may be inverted from those in an NMOS TFT circuit.
In addition, it should be understood that the aspects of the present disclosure are applicable to a-Si, Oxide, LTPS, HTPS, and the like, various manufacturing processes.
The aspects of the present invention are described in detail above with reference to specific circuit configurations, however, the present invention is not limited to the above specific circuit configurations. For example, in other embodiments of the present invention, other specific circuit configurations may be employed to pull down the pull-up control node PU to a low level before pulling up the level of the noise control node PD.
Fig. 8 to 10 are schematic circuit diagrams of specific implementations of another gate driving unit according to an embodiment of the present invention, respectively. The embodiment of fig. 8 to 10 is substantially the same as the previous embodiment, and differences of the embodiment of fig. 8 to 10 from the previous embodiment will be mainly described below, and repetitive description will be omitted.
Referring to fig. 8, the gate driving unit according to the present embodiment is mainly different from the previous embodiments in that the voltage Prior _ PU of the pull-up control node PU of the previous stage gate driving unit in the previous embodiments is replaced with the output out _ N (N-4) of the nth-4 stage gate driving unit to pull down the voltage of the noise control node PD for the period of (r).
In other words, in the gate driving circuit according to the present embodiment, the output signal of the n-4 th stage gate driving unit is input to the noise control block of the nth stage gate driving unit as the noise control driving signal of the nth stage gate driving unit, and the level of the noise control node of the nth stage gate driving unit is pulled down, where n is a positive integer.
According to the present embodiment, another circuit configuration is applied, and it is also realized that the pull-up control node PU is pulled down to a low level before the level of the noise control node PD is pulled up.
Referring to fig. 9, the gate driving unit according to the present embodiment is mainly different from the previous embodiments in that, in addition to controlling the voltage pull-up time point of the noise control node PD of the previous stage gate driving unit with the voltage (Next _ PU) of the pull-up control node PU of the Next stage gate driving unit, the voltage (Next _ PU) is OUTPUT to the control terminal of the pull-up module M3 to control the OUTPUT of the gate driving unit.
In other words, in the gate driving circuit according to the present embodiment, the pull-up control signal of the (n + 1) th stage gate driving unit is input to the noise control module of the nth stage gate driving unit as the noise control driving signal of the nth stage gate driving unit to pull up the level of the noise control node of the nth stage gate driving unit in the period of time (c), where n is a positive integer.
In addition, in the gate driving circuit according to the present embodiment, a pull-up control signal of an n +1 th stage gate driving unit is input to a pull-up module of an nth stage gate driving unit as a signal of a pull-up control node of the nth stage gate driving unit to control a level of an output terminal for a time period of (ii), where n is a positive integer.
In addition, the gate driving unit may have other circuit structures. For example, fig. 10 shows a gate driving circuit of a dual VGL. In fig. 10, in the gate driving unit according to the present embodiment, by controlling the voltage pull-up time point of the noise control node PD of the previous stage gate driving unit using the voltage of the pull-up control node PU of the previous stage gate driving unit and using the voltage (Next _ PU) of the pull-up control node PU of the Next stage gate driving unit, it is possible to first pull down PU and then pull up PD in the third time period, avoiding a case where PU and PD are simultaneously high.
Although implementations of the present disclosure have been described with reference to several specific circuit configurations, it will be understood by those skilled in the art that embodiments of the present disclosure may also be applied to other circuit configurations.
Another embodiment of the present invention further provides a display device including the gate driving circuit according to any one of the foregoing embodiments. The display device may be a Liquid Crystal Display (LCD), however, the present invention is not limited thereto, and the display device may also be other types of display devices, such as an Organic Light Emitting Diode (OLED) display, an electronic paper display, an electroluminescent display, and any other display device to which the gate driving circuit according to the foregoing embodiments can be applied.
According to a gate driving unit and a gate driving circuit of the present invention, the gate driving unit includes: a pull-up module controlling a level of an output signal of the output terminal in response to a signal level of the pull-up control node; an input module to output an input control signal to the pull-up control node in response to a pull-up control signal; a denoising module which cancels noise of the pull-up control node in response to a level of a noise control node; a noise control module outputting a noise control signal to the noise control node in response to a noise control driving signal; and a reset module that resets a level of the pull-up control node in response to a reset control signal. The input module and the noise control module are configured to pull the pull-up control node down to a low level before pulling the level of the noise control node. Therefore, the noise control module and the input module of the gate driving unit can be optimized, so that the pull-up control node and the noise control node of the same gate driving unit can be prevented from being simultaneously at a high level on the basis of keeping the maximum bias time of the TFT, the charging of the pull-up control node and the leakage current of a clock signal are prevented from being influenced, the delay of an output signal can be reduced, the power consumption of the gate driving circuit is reduced, and the stability of the gate driving circuit is improved. Therefore, the gate driving circuit can have better service life, better power consumption performance and better working stability.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (14)
1. A gate drive unit comprising:
a pull-up module controlling a level of an output signal of the output terminal in response to a signal level of the pull-up control node;
an input module outputting an input control signal to the pull-up control node in response to an input control signal;
a denoising module which cancels noise of the pull-up control node in response to a level of a noise control node;
a noise control module outputting a noise control signal to the noise control node in response to a noise control driving signal, the noise control module including a fifth transistor, a ninth transistor, and a first noise control module; a first end of the fifth transistor is connected with the noise control signal, a control end of the fifth transistor is connected with a second end of the ninth transistor, the second end of the fifth transistor is connected with the noise control node, and the first end and the control end of the ninth transistor are connected with the noise control signal; the first noise control module is respectively connected with a second end of the ninth transistor, a noise control node, a low-level signal end and a noise control driving signal; and
a reset module resetting a level of the pull-up control node in response to a reset control signal,
the input module and the noise control module are configured to pull down the pull-up control node to a low level before pulling up a level of the noise control node, the first noise control module is configured to pull down the noise control node to a low level before pulling up a signal level of the pull-up control node, the noise control drive signal is a pull-up control signal of a previous-stage gate drive unit or an output signal of an nth-4-stage gate drive unit, and the nth-stage gate drive unit is a current gate drive unit.
2. The gate driving unit of claim 1, wherein the de-noising module further removes signal noise at the output in response to the noise control signal.
3. The gate driving unit of claim 1, wherein the noise control module comprises a second noise control module pulling up the noise control node after a signal level of the pull-up control node is pulled down to a low level.
4. A gate drive circuit comprising a plurality of cascaded gate drive units as claimed in any one of claims 1 to 3.
5. A method of driving the gate drive circuit of claim 4, comprising:
in a first time period, a starting signal pulls up the level of a pull-up control node through an input module, and simultaneously pulls down the level of a noise control node;
in a second time period, the first clock signal is increased, the pull-up control node transmits the high level of the first clock signal to the output end through the pull-up control module, and meanwhile, the input module continues to pull down the level of the noise control node;
in the third time period, the reset signal pulls down the level of the pull-up control node through the reset module, and the electric charge at the output end is discharged through the pull-up module.
6. The method of claim 5, wherein in the first period, the pull-up control signal of the nth-1 th stage gate driving unit is input to the noise control module of the nth stage gate driving unit as the noise control driving signal of the nth stage gate driving unit, and the level of the noise control node of the nth stage gate driving unit is pulled down, wherein n is a positive integer.
7. The method as claimed in claim 5, wherein, in the first period, the output signal of the nth-4 th stage gate driving unit is input to the noise control module of the nth stage gate driving unit as the noise control driving signal of the nth stage gate driving unit, and the level of the noise control node of the nth stage gate driving unit is pulled down, where n is a positive integer.
8. The method of claim 5, wherein in the third period, the pull-up control signal of the n +1 th stage gate driving unit is input to the noise control module of the nth stage gate driving unit as the noise control driving signal of the nth stage gate driving unit, and the level of the noise control node of the nth stage gate driving unit is pulled down, wherein n is a positive integer.
9. The method of claim 5, wherein in the second period, the pull-up control signal of the (n + 1) th stage gate driving unit is input to the pull-up module of the nth stage gate driving unit as a signal of the pull-up control node of the nth stage gate driving unit, where n is a positive integer.
10. The method of claim 5, wherein in the third period, the output signal of the n +4 th stage gate driving unit resets a level of a pull-up control node of the nth stage gate driving unit as a reset signal of the nth stage gate driving unit, wherein n is a positive integer.
11. The method of claim 5, wherein the signal duty cycle of the first clock signal is less than 50%.
12. The method of claim 5, wherein the signal duty cycle of the first clock signal is between 40% -50%.
13. The method of claim 5, wherein the initiation signal comprises a pulsed initiation signal.
14. A display device comprising the gate driver circuit as claimed in claim 4.
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| CN107945762A (en) | 2018-01-03 | 2018-04-20 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| CN108447453B (en) * | 2018-04-10 | 2021-04-23 | 京东方科技集团股份有限公司 | GOA circuit, driving method thereof and touch display device |
| CN108665846B (en) * | 2018-07-13 | 2022-01-28 | 京东方科技集团股份有限公司 | Shift register unit, grid driving circuit, display device and driving method |
| CN110992896A (en) * | 2019-11-19 | 2020-04-10 | 复旦大学 | Gate drive circuit unit for semiconductor display, drive circuit and display device |
| CN111025808B (en) * | 2019-12-30 | 2022-07-01 | 厦门天马微电子有限公司 | Display panel, working method thereof and display device |
| CN112885284B (en) * | 2021-02-25 | 2024-01-19 | 福建华佳彩有限公司 | GIP circuit of touch display screen and control method thereof |
| CN114333701B (en) * | 2022-01-10 | 2023-03-28 | 信利(仁寿)高端显示科技有限公司 | Grid driving circuit and method |
| CN114495801B (en) * | 2022-03-10 | 2023-11-28 | 北京京东方显示技术有限公司 | Display device, gate driving circuit, shift register unit and driving method thereof |
| WO2023201715A1 (en) * | 2022-04-22 | 2023-10-26 | 京东方科技集团股份有限公司 | Gate driving circuit, display panel, driving method and display apparatus |
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| CN202443728U (en) * | 2012-03-05 | 2012-09-19 | 京东方科技集团股份有限公司 | Shift register, gate driver and display device |
| CN102945657B (en) * | 2012-10-29 | 2014-09-10 | 京东方科技集团股份有限公司 | Shift register unit, grid drive circuit, array substrate and display device |
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