CN105702225B - Gate driving circuit and its driving method and display device - Google Patents
Gate driving circuit and its driving method and display device Download PDFInfo
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- CN105702225B CN105702225B CN201610270466.2A CN201610270466A CN105702225B CN 105702225 B CN105702225 B CN 105702225B CN 201610270466 A CN201610270466 A CN 201610270466A CN 105702225 B CN105702225 B CN 105702225B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention belongs to display technology fields, and in particular to gate driving circuit and driving method and display device.In the gate driving circuit：Input module connects this grade of pull-up node, input signal and power supply, for being high level, tie point of this grade of pull-up node between input module and output module by the voltage pull-up of this grade of pull-up node；Output module connects this grade of pull-up node, the first clock signal, for exporting gate drive signal by output end under the control of the first clock signal and this grade of pull-up node；Reseting module connects reset signal, this grade of pull-up node and reference voltage, the voltage for resetting this grade of pull-up node under the control of reset signal；Module connection input signal, the signal of next stage pull-up node, the first clock signal, second clock signal, reference voltage, this grade of pull-up node and output module are kept, for persistently pull down the output signal of the voltage of this grade of pull-up node and output module as low level.The gate driving circuit noise is small.
Description
Technical field
The invention belongs to display technology fields, and in particular to a kind of gate driving circuit and its driving method and display fill
It sets.
Background technology
In the prior art, in display screen each dot structure include thin film transistor (TFT) (Thin Film Transistor,
Abbreviation TFT), grid line drive signal therein is provided by driving chip (Driver IC), by sequence controller Tcon by rectangle
Waveform shifts the grid line that display screen is supplied to as gate drive signal.
With the rapid development of thin-film transistor technologies, each manufacturer just make great efforts study new technology to reduce cost,
To promote the competitiveness of product in market.Array substrate row driving (Gate On Array, abbreviation GOA) technology is come into being,
It is that the gate switch circuit of thin film transistor (TFT) is integrated in array substrate, removes grid integrated circuits part, to save
Material and processing step achieve the purpose that reduce cost.
Existing tool has plenty of there are one in the GOA circuits of capacitance and controls pull-down node PD by a clock signal, so
Pass through the drop-down of pull-down node PD control pull-up node PU and output end OUT again afterwards.But due to the duty ratio of pull-down node PD
It is 50%, so output end OUT is pulled down in scan period half the time, the other half time suspension floating causes defeated
The noise of outlet OUT is bigger；Some controls pull-down node PD by power vd D, to make pull-down node PD be constantly in height
Voltage status can be such that pull-up node PU and output end OUT is pulled low always in this way, although such structure solves noise and asks
Topic, but it is detrimental to the service life of thin film transistor (TFT).
As it can be seen that designing, a kind of noise is small, can guarantee that there is thin film transistor (TFT) the driving circuit of longer life to become at present urgently
Technical problem to be solved.
Invention content
The technical problem to be solved by the present invention is to aiming at the above shortcomings existing in the prior art, provide a kind of grid drive
Dynamic circuit and its driving method and display device, the gate driving circuit noise is small, and it is more long-lived to can guarantee that thin film transistor (TFT) has
Life.
Technical solution is the gate driving circuit, including multiple cascade grids used by solving present invention problem
Driving unit, each drive element of the grid are used to provide gate drive signal, the drive element of the grid for a grid line
Including input module, output module, reseting module and module is kept, wherein：
The input module is separately connected the pull-up node, input signal and power supply of this grade of drive element of the grid, uses
It is high level, this grade of drive element of the grid in pulling up the voltage of the pull-up node of this grade of drive element of the grid
Tie point of the pull-up node between the input module and output module；
The output module is separately connected the pull-up node, the first clock signal of this grade of drive element of the grid,
For being exported by output end under the control of the first clock signal and the pull-up node of this grade of drive element of the grid
Gate drive signal；
The reseting module is separately connected the pull-up node and ginseng of reset signal, this grade of drive element of the grid
Voltage is examined, the voltage of the pull-up node for resetting this grade of drive element of the grid under the control of reset signal；
The holding module is separately connected the pull-up node of drive element of the grid described in input signal, next stage
The pull-up section of signal, first clock signal, second clock signal, reference voltage, this grade of drive element of the grid
Point and the output module are used for the voltage of the pull-up node of this grade of drive element of the grid and the output module
Output signal persistently pull down be low level.
Preferably, the input module includes the first transistor, and the grid of the first transistor connects input signal,
First pole connects the power supply, and the second pole connects the pull-up node of this grade of drive element of the grid.
Preferably, the reseting module includes second transistor, and the grid of the second transistor connects reset signal,
First pole connects the pull-up node of this grade of drive element of the grid, and the second pole connects the reference voltage.
Preferably, the output module includes third transistor and the first capacitance, wherein：
The third transistor, grid connect the pull-up node of this grade of drive element of the grid, and the first pole connects
First clock signal is connect, the second pole connects the second end of first capacitance；
First capacitance, first end connect the pull-up node of this grade of drive element of the grid, and described first
The connecting pin of the second end of capacitance and the second pole of the third transistor is the output end.
Preferably, the holding module includes the 4th transistor, the 5th transistor, the 6th transistor and the 7th crystal
Pipe, wherein：
4th transistor, grid connect second clock signal, and the first pole connects input signal, and the connection of the second pole is originally
The pull-up node of the grade drive element of the grid；
5th transistor, grid connect the first clock signal, and the first pole connects this grade of drive element of the grid
The pull-up node, the second pole connect next stage described in drive element of the grid the pull-up node；
6th transistor, grid connect second clock signal, and the first pole connects the output end, the connection of the second pole
Reference voltage；
7th transistor, grid connect second clock signal, and the first pole connects the output end, the connection of the second pole
The signal of the pull-up node of drive element of the grid described in next stage.
Preferably, further include closedown module in the drive element of the grid of end, the closedown module includes the
Eight transistor M8, the grid connection control signal of the 8th transistor, the first pole connects this grade of drive element of the grid
The pull-up node, the second pole connect reference signal.
A kind of array substrate, including above-mentioned gate driving circuit.
A kind of display device, including above-mentioned array substrate.
A kind of driving method of above-mentioned gate driving circuit, including input phase, output stage, reseting stage, holding
Stage, wherein：
In input phase：The input module receives the output of the output module of drive element of the grid described in upper level
Input signal is stored in the pull-up node of this grade of drive element of the grid by signal as input signal；
In the output stage：Under the control of the first clock signal, high level is exported by the output end of the output module；
In reseting stage：The output signal of the output module of drive element of the grid described in following one level is believed as resetting
Number, drag down the voltage of the pull-up node of this grade of drive element of the grid；
In the stage of holding：Under the control of the first clock signal and second clock signal, holding drags down this grade of grid
The voltage of the pull-up node and the output end of driving unit.
Preferably, in input phase：Input signal is high level, and the first transistor is opened, this grade of gate driving
The pull-up node of unit is high level；Third transistor is opened, and the first clock signal is low level, and output end exports low level；
Second clock signal is high level, and the 4th transistor, the 6th transistor are opened, the pull-up node of this grade of drive element of the grid
For high level, output end is pulled low；First clock signal is low level, and the 5th transistor, the 7th transistor are closed；
In the output stage：Due to the boot strap of the first capacitance, the pull-up node level of this grade of drive element of the grid
Continue to increase, third transistor is opened, and the first clock signal is high level, and output end exports high level as this grade of grid
The gate drive signal of driving unit；Meanwhile the 5th transistor, the 7th transistor are opened, at this point, gate driving described in next stage
The pull-up node of unit is high level, and the pull-up node of this grade of drive element of the grid is still high level；
In reseting stage：Reset signal is high level, and second transistor is opened, the pull-up of this grade of drive element of the grid
Node is pulled low, and second clock signal is high level, and the 4th transistor, the 6th transistor are opened, this grade of gate driving list
The pull-up node and output end of member are pulled low；First clock signal is low level, and the 5th transistor, the 7th transistor are closed；
In the stage of holding：Second clock signal is low level, and the 4th transistor, the 6th transistor are closed, the first clock letter
Number be high level, the 5th transistor, the 7th transistor open, the pull-up node and output end quilt of this grade of drive element of the grid
It drags down；Second clock signal and the first clock signal are alternately low and high level later, control the 4th transistor, the 6th crystal respectively
Pull-up node and the output end holding of pipe and the 5th transistor, the 7th transistor, this grade of drive element of the grid are pulled low.
Preferably, first clock signal and the second clock signal are that a pair of of sequential is identical, opposite in phase
Rectangular wave pulse, low and high level respectively account for 50%；Also, the high level of the second clock signal is believed prior to first clock
Number.
Preferably, further include dwell period, in the dwell period, the 8th transistor is opened, this grade of grid drives
Pull-up node and the output end holding of moving cell are pulled low；
Wherein：
It is opened from frame start signal STV, the output end to the drive element of the grid of end exports high level, control letter
Number it is low level；After the output end of the drive element of the grid of end exports high level, until next frame start signal
Effectively, control signal is high level.
The beneficial effects of the invention are as follows：The gate driving circuit and its corresponding grid drive method make this grade of grid
The pull-up node PU and output end OUT of pole driving unit are pulled low always, when middle transistor 100% is opened compared with the existing technology
Between the case where or 50% time suspend the case where, efficiently solve noise problem, and be conducive to the longevity of thin film transistor (TFT)
Life.
Description of the drawings
Fig. 1 is the modular structure schematic diagram of gate driving circuit in the embodiment of the present invention 1；
Fig. 2 is the circuit diagram of drive element of the grid in the embodiment of the present invention 1；
Fig. 3 is a kind of timing waveform of drive element of the grid in the embodiment of the present invention 2；
Fig. 4 is the circuit diagram of the unidirectional drive of Fig. 2；
Fig. 5 is the circuit diagram with end drive element of the grid in 1 gate driving circuit of the embodiment of the present invention；
In figure：
1- input modules；2- keeps module；3- reseting modules；4- output modules；5- closedown modules.
Specific implementation mode
To make those skilled in the art more fully understand technical scheme of the present invention, below in conjunction with the accompanying drawings and specific embodiment party
Formula is described in further detail gate driving circuit of the present invention and its driving method, display device.
Embodiment 1：
The present embodiment provides a kind of gate driving circuits, and the gate driving circuit noise is small, can guarantee that thin film transistor (TFT) has
There is longer life.
A kind of gate driving circuit as shown in Figure 1, including multiple cascade drive element of the grid, each gate driving list
Member for a grid line for providing gate drive signal.Wherein, as shown in Fig. 2, drive element of the grid include input module 1, it is defeated
Go out module 4, reseting module 3 and keeps module 2, wherein：
Input module 1, be separately connected this grade of drive element of the grid pull-up node PU (hereinafter referred to as this grade of pull-up node),
Input signal INPUT and power vd D, for being high level, this grade of pull-up node PU by the voltage pull-up of this grade of pull-up node PU
For the tie point between input module 1 and output module 4；
Output module 4 is separately connected this grade of pull-up node PU, the first clock signal clk, in the first clock signal
Gate drive signal is exported by output end OUT under the control of CLK and this grade of pull-up node PU；
Reseting module 3 is separately connected reset signal RESET, this grade of pull-up node PU and reference voltage VGL, in weight
The voltage of this grade of pull-up node PU is resetted under the control of confidence RESET；
Module 2 is kept, the signal N+ of the pull-up node of input signal INPUT, next stage drive element of the grid is separately connected
1PU, the first clock signal clk, second clock signal CLKB, reference voltage VGL, this grade of pull-up node PU and output module 4 are used
It is low level in persistently pulling down the output signal of the voltage of this grade of pull-up node PU and output module 4.
Wherein, input module 1 includes the first transistor M1, and the grid of the first transistor M1 connects input signal INPUT, the
One pole connects power vd D, and the second pole connects this grade of pull-up node PU.
Output module 4 includes third transistor M3 and the first capacitance C1, wherein：
Third transistor M3, grid connect this grade of pull-up node PU, and the first pole connects the first clock signal clk, and second
Pole connects the second end of the first capacitance；
First capacitance C1, first end connect this grade of pull-up node PU, the second end and third transistor of the first capacitance C1
The connecting pin of the second pole of M3 is the output end OUT of output module 4.
Module 2 is kept to include the 4th transistor M4, the 5th transistor M5, the 6th transistor M6 and the 7th transistor M7,
In：
4th transistor M4, grid connect second clock signal CLKB, the first pole connection input signal INPUT, second
Pole connects this grade of pull-up node PU；
5th transistor M5, grid connect the first clock signal clk, and the first pole connects this grade of pull-up node PU, and second
Pole connects the pull-up node N+1PU of next stage drive element of the grid；
6th transistor M6, grid connect second clock signal CLKB, and the first pole connects output end OUT, and the second pole connects
Meet reference voltage VGL；
7th transistor M7, grid connect second clock signal CLKB, and the first pole connects output end OUT, and the second pole connects
Connect the signal of the pull-up node N+1PU of next stage drive element of the grid.
Reseting module 3 includes second transistor M2, and the grid of second transistor M2 connects reset signal RESET, the first pole
This grade of pull-up node PU is connected, the second pole connects reference voltage VGL.In some applications, second transistor M2 is removed, you can
Form the gate driving mode of only simple scanning.
A kind of simplification structure of above-mentioned gate driving circuit is as shown in figure 4, can be by power vd D with input signal INPUT generations
It replaces.It can reduce rise time Tr (Rise Time), fall time Tf (Fall by adjusting the size of each transistor at this time
) and noise Time.Under normal conditions, the size of transistor is bigger, and rise time and fall time are smaller, but the bigger side of size
Frame is also bigger therewith, therefore can weigh and determine in a particular application the ruler of transistor according to frame size and noise qualities synthesis
It is very little, it does not limit here.
Wherein, the first transistor M1 to the 7th transistor M7 is P-type transistor, at this point, its first extremely can be drain electrode,
Second extremely can be source electrode；Alternatively, the first transistor M1 to the 7th transistor M7 is N-type transistor, at this point, its first pole can
To be source electrode, second extremely can be drain electrode；Alternatively, the first transistor T1 is mixed to the 7th transistor T7 selects N-type transistor and P
Transistor npn npn only needs simultaneously by the port polarity of the 7th transistor T7 of the first transistor T1- of selection type by the present embodiment the
The port polarity of the 7th transistor T7 of one transistor T1- makes corresponding change in connection, and I will not elaborate.
Gate driving circuit in the present embodiment, each of which drive element of the grid only include seven transistors and one
Capacitance, not only control easy to implement, but also be conducive to display panel and realize narrow frame design.
Correspondingly, the present embodiment also provides a kind of driving method of gate driving circuit comprising input phase, output rank
Section, is kept for the stage at reseting stage, wherein：
In input phase I：Input module 1 receives the output signal conduct of the output module 4 of upper level drive element of the grid
Input signal INPUT, and input signal INPUT is stored in this grade of pull-up node PU；
In output stage II：It is high by the output end OUT outputs of output module 4 under the control of the first clock signal clk
Level；
In reseting stage III：The output signal of the output module 4 of following one level drive element of the grid is as reset signal
RESET drags down the voltage of this grade of pull-up node PU；
Keeping stage IV：Under the control of the first clock signal clk and second clock signal CLKB, holding drags down this grade
The voltage of pull-up node PU and output end OUT.
Wherein, the first clock signal clk and second clock signal CLKB are that a pair of of sequential is identical, rectangle arteries and veins of opposite in phase
Wave is rushed, low and high level respectively accounts for 50%；Also, the high level of second clock signal CLKB is prior to the first clock signal clk.
With reference to the timing waveform of each input signal INPUT of figure 3, this grade of pull-up node PU and output end OUT.The present embodiment
In the driving method of middle gate driving circuit, the state of clock signal and transistor is specific as follows in each stage：
In input phase I：Input signal INPUT is high level, and the first transistor M1 is opened, this grade of pull-up node PU is height
Level；Third transistor M3 is opened, and the first clock signal clk is low level, and output end OUT exports low level；Second clock is believed
Number CLKB is high level, and the 4th transistor M4, the 6th transistor M6 are opened, this grade of pull-up node PU is high level, output end OUT
It is pulled low；First clock signal clk is low level, and the 5th transistor M5, the 7th transistor M7 are closed；
In output stage II：Due to the boot strap of the first capacitance C1, the level of this grade of pull-up node PU continues to increase, the
Three transistor M3 are opened, and the first clock signal clk is high level, and output end OUT exports high level as this grade of gate driving list
The gate drive signal of member；Simultaneously as the first clock signal clk is high level, the 5th transistor M5, the 7th transistor M7 are beaten
It opens, at this point, the pull-up node N+1PU of next stage drive element of the grid (i.e. the N+1 GOA unit) is high level, this grade of grid
This grade of pull-up node PU of driving unit is still high level；
In reseting stage III：Reset signal RESET is high level, and second transistor M2 is opened, this grade of pull-up node PU quilt
Drag down, second clock signal CLKB is high level, and the 4th transistor M4, the 6th transistor M6 are opened, this grade of pull-up node PU and
Output end OUT is pulled low；First clock signal clk is low level, and the 5th transistor M5, the 7th transistor M7 are closed；
Keeping stage IV：Second clock signal CLKB is low level, and the 4th transistor M4, the 6th transistor M6 are closed,
First clock signal clk is high level, and the 5th transistor M5, the 7th transistor M7 are opened, this grade of pull-up node PU and output end
OUT is pulled low.
Later, second clock signal CLKB and the first clock signal clk are alternately low and high level, control the 4th crystal respectively
The opening and closing of pipe M4, the 6th transistor M6 and the 5th transistor M5, the 7th transistor M7, this grade of pull-up node PU and output
End OUT holdings are pulled low.
Gate driving circuit in the present embodiment is alternately controlled by the first clock signal clk and second clock signal CLKB
The drop-down of this grade of pull-up node PU and output end OUT stablize the effect of row output signal to realize the effect for eliminating noise.
In addition, in the presence of having blanking clock signal (Dummy CLK), the drive element of the grid of end can not be answered normally
Position, at this time as shown in figure 5, further including closedown module 5 in drive element of the grid, closedown module 5 includes the 8th transistor M8,
Grid connection control signal GCL, the first pole connect this grade of pull-up node PU, and the second pole connects reference signal VGL.
Correspondingly, the driving method of the gate driving circuit further includes dwell period, that is, increasing the 8th transistor
M8 simultaneously connects corresponding control signal GCL, is opened from frame start signal STV, to the output end OUT of the drive element of the grid of end
High level is exported, GCL is low level；After the output end OUT of the drive element of the grid of end exports high level, until under
One STV is effective, and GCL is high level, and the 8th transistor M8 is opened, this grade of pull-up node PU dragged down, to make output end OUT
Also it is low level.
Gate driving circuit in the present embodiment and its corresponding driving method make this grade of pull-up node PU and output end
OUT is pulled low always, compared with the existing technology in 100% opening time of transistor the case where or 50% time suspend feelings
Condition, time of the transistor in addition to the opening time in the present embodiment is pull-down state, it is thus eliminated that due to leakage current causes
Noise, efficiently solve noise problem, and be conducive to the service life of thin film transistor (TFT).
Embodiment 2：
The present embodiment provides a kind of array substrate of gate driving circuit including embodiment 1 and corresponding display dresses
It sets.
The display device can be：Liquid crystal display panel, Electronic Paper, mobile phone, tablet computer, television set, display, notebook electricity
Any product or component with display function such as brain, Digital Frame, navigator.
The gate driving circuit and its corresponding gate driving circuit used due to it has preferably performance and longer
Service life, therefore there is the array substrate preferably performance and longer service life, corresponding display device to have better picture product
Matter and longer service life.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, however the present invention is not limited thereto.For those skilled in the art, in the essence for not departing from the present invention
In the case of refreshing and essence, various changes and modifications can be made therein, these variations and modifications are also considered as protection scope of the present invention.
Claims (12)
1. a kind of gate driving circuit, including multiple cascade drive element of the grid, each drive element of the grid is for being
One grid line provides gate drive signal, which is characterized in that the drive element of the grid includes input module, output module, answers
Position module and holding module, wherein：
The input module is separately connected the pull-up node, input signal and power supply of this grade of drive element of the grid, and being used for will
The voltage pull-up of the pull-up node of this grade of drive element of the grid is high level, the institute of this grade of drive element of the grid
State tie point of the pull-up node between the input module and output module；
The output module is separately connected the pull-up node, the first clock signal of this grade of drive element of the grid, is used for
Grid is exported by output end under the control of the first clock signal and the pull-up node of this grade of drive element of the grid
Drive signal；
The reseting module is separately connected reset signal, the pull-up node of this grade of drive element of the grid and with reference to electricity
Pressure, the voltage of the pull-up node for resetting this grade of drive element of the grid under the control of reset signal；
The holding module, be separately connected the pull-up node of drive element of the grid described in input signal, next stage signal,
First clock signal, second clock signal, reference voltage, the pull-up node of this grade of drive element of the grid and institute
Output module is stated, is used for the output of the voltage and the output module of the pull-up node of this grade of drive element of the grid
It is low level that signal, which persistently pulls down,.
2. gate driving circuit according to claim 1, which is characterized in that the input module includes the first transistor,
The grid of the first transistor connects input signal, and the first pole connects the power supply, and the second pole connects this grade of grid and drives
The pull-up node of moving cell.
3. gate driving circuit according to claim 1, which is characterized in that the reseting module includes second transistor,
The grid of the second transistor connects reset signal, and the first pole connects the pull-up section of this grade of drive element of the grid
Point, the second pole connect the reference voltage.
4. gate driving circuit according to claim 1, which is characterized in that the output module include third transistor and
First capacitance, wherein：
The third transistor, grid connect the pull-up node of this grade of drive element of the grid, and the first pole connects institute
The first clock signal is stated, the second pole connects the second end of first capacitance；
First capacitance, first end connect the pull-up node of this grade of drive element of the grid, first capacitance
The connecting pin of the second pole of second end and the third transistor be the output end.
5. gate driving circuit according to claim 1, which is characterized in that the holding module include the 4th transistor,
5th transistor, the 6th transistor and the 7th transistor, wherein：
4th transistor, grid connect second clock signal, and the first pole connects input signal, and the second pole connects this grade of institute
State the pull-up node of drive element of the grid；
5th transistor, grid connect the first clock signal, and the first pole connects the institute of this grade of drive element of the grid
Pull-up node is stated, the second pole connects the pull-up node of drive element of the grid described in next stage；
6th transistor, grid connect second clock signal, and the first pole connects the output end, the connection reference of the second pole
Voltage；
7th transistor, grid connect second clock signal, and the first pole connects the output end, and the connection of the second pole is next
The signal of the pull-up node of the grade drive element of the grid.
6. gate driving circuit according to claim 1, which is characterized in that in the drive element of the grid of end also
Including closedown module, the closedown module includes the 8th transistor M8, and the grid connection of the 8th transistor controls signal, the
One pole connects the pull-up node of this grade of drive element of the grid, and the second pole connects reference signal.
7. a kind of array substrate, which is characterized in that including claim 1-6 any one of them gate driving circuits.
8. a kind of display device, which is characterized in that including the array substrate described in claim 7.
9. a kind of driving method of claim 1-6 any one of them gate driving circuits, which is characterized in that including inputting rank
Section, reseting stage, is kept for the stage at the output stage, wherein：
In input phase：The input module receives the output signal of the output module of drive element of the grid described in upper level
As input signal, and input signal is stored in the pull-up node of this grade of drive element of the grid；
In the output stage：Under the control of the first clock signal, high level is exported by the output end of the output module；
In reseting stage：The output signal of the output module of drive element of the grid described in following one level as reset signal,
Drag down the voltage of the pull-up node of this grade of drive element of the grid；
In the stage of holding：Under the control of the first clock signal and second clock signal, holding drags down this grade of gate driving
The voltage of the pull-up node and the output end of unit.
10. the driving method of gate driving circuit according to claim 9, which is characterized in that using claim 2-5
When the structure of the gate driving circuit in any one,
In input phase：Input signal is high level, and the first transistor is opened, the pull-up node of this grade of drive element of the grid
For high level；Third transistor is opened, and the first clock signal is low level, and output end exports low level；Second clock signal is
High level, the 4th transistor, the 6th transistor are opened, and the pull-up node of this grade of drive element of the grid is high level, output
End is pulled low；First clock signal is low level, and the 5th transistor, the 7th transistor are closed；
In the output stage：Due to the boot strap of the first capacitance, the pull-up node level of this grade of drive element of the grid continues
It increases, third transistor is opened, and the first clock signal is high level, and output end exports high level as this grade of gate driving
The gate drive signal of unit；Meanwhile the 5th transistor, the 7th transistor are opened, at this point, drive element of the grid described in next stage
Pull-up node be high level, the pull-up node of this grade of drive element of the grid is still high level；
In reseting stage：Reset signal is high level, and second transistor is opened, the pull-up node of this grade of drive element of the grid
It is pulled low, second clock signal is high level, and the 4th transistor, the 6th transistor are opened, this grade of drive element of the grid
Pull-up node and output end are pulled low；First clock signal is low level, and the 5th transistor, the 7th transistor are closed；
In the stage of holding：Second clock signal is low level, and the 4th transistor, the 6th transistor are closed, and the first clock signal is
High level, the 5th transistor, the 7th transistor are opened, the pull-up node and output end of this grade of drive element of the grid are drawn
It is low；Second clock signal and the first clock signal are alternately low and high level later, control the 4th transistor, the 6th transistor respectively
Pull-up node and output end holding with the 5th transistor, the 7th transistor, this grade of drive element of the grid is pulled low.
11. the driving method of gate driving circuit according to claim 9, which is characterized in that first clock signal
For a pair of of sequential, identical, opposite in phase rectangular wave pulse, low and high level respectively account for 50% with the second clock signal；And
And the high level of the second clock signal is prior to first clock signal.
12. the driving method of gate driving circuit according to claim 10, which is characterized in that using further including right
It is required that when the structure of the gate driving circuit in 6,
Further include dwell period, in the dwell period, the 8th transistor is opened, the pull-up section of this grade of drive element of the grid
Point and output end holding are pulled low；Wherein：
It is opened from frame start signal STV, the output end to the drive element of the grid of end exports high level, and control signal is equal
For low level；After the output end of the drive element of the grid of end exports high level, until next frame start signal is effective,
Control signal is high level.
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| CN106328080B (en) * | 2016-09-27 | 2019-02-19 | 南京中电熊猫液晶显示科技有限公司 | A kind of method of GOA circuit control |
| CN107301833B (en) * | 2017-08-24 | 2020-11-13 | 京东方科技集团股份有限公司 | Gate driving unit, gate driving circuit, driving method of gate driving circuit and display device |
| CN107403602B (en) * | 2017-09-25 | 2020-05-19 | 京东方科技集团股份有限公司 | Shift register unit, shift register circuit and display device |
| CN107978294A (en) * | 2018-01-12 | 2018-05-01 | 京东方科技集团股份有限公司 | Shift register cell, shift-register circuit, display panel |
| CN108564910A (en) * | 2018-03-12 | 2018-09-21 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN108648716B (en) * | 2018-07-25 | 2020-06-09 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN114187868B (en) * | 2021-12-31 | 2022-11-25 | 长沙惠科光电有限公司 | Row driving circuit, array substrate and display panel |
| CN114974163B (en) * | 2022-06-28 | 2023-05-26 | 惠科股份有限公司 | Scanning driving circuit, array substrate and display panel |
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