CN205069085U - Shift register , grid integrated drive electronics and display device - Google Patents
Shift register , grid integrated drive electronics and display device Download PDFInfo
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- CN205069085U CN205069085U CN201520848146.1U CN201520848146U CN205069085U CN 205069085 U CN205069085 U CN 205069085U CN 201520848146 U CN201520848146 U CN 201520848146U CN 205069085 U CN205069085 U CN 205069085U
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Abstract
The utility model discloses a shift register, grid integrated drive electronics and display device has increased and has used as low level signal end in the sweep time section, holds the compensation signal end that uses as high level signal in non - sweep time section, the compensation signal end links to each other with the first output of first drop -down unit and drop -down the control unit's second output respectively, and the first control end of first drop -down unit links to each other with the 2nd clock signal end, and drop -down the control unit's third control end and clock signal end link to each other. Consequently, forward drift that threshold voltage between the first control of first drop -down unit end and the first output produced in the sweep time section and the negative sense drift cancel each other out who produces in non - sweep time section, same, the forward drift that drop -down the control unit's third control end and the threshold voltage between the second output produced in the sweep time section and the negative sense that produces in the non - sweep time section cancel each other out that drifts about avoids the problem that threshold voltage drifted about and result in sweep time 0 easily to lose efficacy.
Description
Technical field
The utility model relates to display technique field, particularly relates to a kind of shift register, grid integrated drive electronics and display device.
Background technology
In recent years, liquid crystal display (LiquidCrystalDisplay, LCD) there is the advantages such as the frivolous and low power consumption of profile, therefore be widely used in various electronic product, and grid integrated drive electronics (Gate-driveronArray, GOA) technology is a field of liquid crystal display development technology branch rapidly, key concept is integrated on image element array substrates by shift register, by to thin film transistor (TFT) (ThinFilmTransistor on shift register, TFT) control realizes the turntable driving to liquid crystal panel, and GOA can complete under same making technology with image element array substrates, save cost of manufacture, brilliant film (ChiponFilm is covered with traditional, and chip bonding (ChiponGlass on glass substrate COF), COG) technique is compared, GOA technology not only reduces power consumption, and improve the integrated level of liquid crystal panel, thus reduction packing surface, meet the design requirement of narrow frame instantly.
Although there is above-mentioned advantage in GOA technology, but still there are some problems, problem is that shift register is very high to the dependence of TFT characteristic, especially the threshold voltage of TFT is especially huge on the impact of shift register stability, this is because the instability of the threshold voltage of TFT causes, as shown in Figure 1, label is the curve of A is the Ids-Vgs curve of TFT when just starting working, label is the curve of B is the Ids-Vgs curve occurring after TFT loads forward bias for a long time to drift about, because TFT is under long duty, TFT threshold voltage can produce positive excursion along with the impact of normal stress, the Ids-Vgs curve of TFT is caused to move right, under same voltage, On current diminishes, the function designed just can not be realized to a certain degree, and then affect the normal output of whole shift register, thus cause shift register maloperation or inefficacy.
Utility model content
The utility model embodiment provides a kind of shift register, grid integrated drive electronics and display device, in order to solve the problem that existing shift register easily lost efficacy when working long hours.
Therefore, a kind of shift register that the utility model embodiment provides, comprising: output control unit, the first drop-down unit, the second drop-down unit, and drop-down control unit; Wherein,
The control end of described output control unit is connected with signal input part by first node, and input end is connected with the first clock signal terminal, and output terminal is connected with signal output part; Described output control unit is used for the current potential drawing high described first node when described signal input part input high level, at described first clock signal terminal input high level and described first node is noble potential time, control described signal output part and export the signal of high level;
First control end of described first drop-down unit is connected with second clock signal end, and input end is connected with described signal output part, and the first output terminal is connected with compensating signal end; Described first drop-down unit is used for when described second clock signal end input high level, controls described signal output part and the conducting of described compensating signal end;
The control end of described second drop-down unit is connected with Section Point, and input end is connected with described first node, and output terminal is connected with described compensating signal end; Described second drop-down unit is used for when described Section Point is noble potential, controls described first node and the conducting of described compensating signal end;
First control end of described drop-down control unit is connected with described input signal end, second control end is connected with described first node, 3rd control end is connected with described first clock signal terminal, input end is connected with described Section Point, first output terminal is connected with low level signal end, and the second output terminal is connected with described compensating signal end; Described drop-down control unit is used for when described first clock signal terminal input high level, drags down the current potential of described Section Point, and when described signal input part or described first node are noble potential, drags down the current potential of described Section Point; Described Section Point is connected with described second clock signal end;
Described first clock signal terminal is contrary at the signal phase of section input sweep time with second clock signal end, the signal of input low level the Non-scanning mode time period while; Described compensating signal end at the signal of section input low level sweep time, at the signal of Non-scanning mode time period input high level.
In a kind of possible embodiment, the above-mentioned shift register that the utility model embodiment provides, also comprises: the 3rd drop-down unit;
The control end of described 3rd drop-down unit is connected with described compensating signal end, and input end is connected with described low level signal end, and output terminal is connected with described Section Point; Described 3rd drop-down unit is used for when described compensating signal end input high level, drags down the current potential of described Section Point.
In a kind of possible embodiment, in the above-mentioned shift register that the utility model embodiment provides, described 3rd drop-down unit specifically comprises: the first film transistor; Wherein, the grid of described the first film transistor is connected with described compensating signal end, and source electrode is connected with described low level signal end, drains to be connected with described Section Point.
In a kind of possible embodiment, in the above-mentioned shift register that the utility model embodiment provides, described first drop-down unit specifically comprises: the second thin film transistor (TFT); Wherein, the grid of described second thin film transistor (TFT) is connected with described second clock signal end, and source electrode is connected with described signal output part, drains to be connected with described compensating signal end.
In a kind of possible embodiment, in the above-mentioned shift register that the utility model embodiment provides, described first drop-down unit also comprises: the second control end be connected with described Section Point, the second input end be connected with described signal output part, the second output terminal be connected with described compensating signal end; Described first drop-down unit, also for when described Section Point is noble potential, controls described signal output part and the conducting of described compensating signal end.
In a kind of possible embodiment, in the above-mentioned shift register that the utility model embodiment provides, described first drop-down unit specifically also comprises: the 3rd thin film transistor (TFT); Wherein, the grid of described 3rd thin film transistor (TFT) is connected with described Section Point, and source electrode is connected with described signal output part, drains to be connected with described compensating signal end.
In a kind of possible embodiment, in the above-mentioned shift register that the utility model embodiment provides, described second drop-down unit specifically comprises: the 4th thin film transistor (TFT); Wherein, the grid of described 4th thin film transistor (TFT) is connected with described Section Point, and source electrode is connected with described first node, drains to be connected with described compensating signal end.
In a kind of possible embodiment, in the above-mentioned shift register that the utility model embodiment provides, described drop-down control unit specifically comprises: the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), and the 7th thin film transistor (TFT); Wherein, the grid of described 5th thin film transistor (TFT) is connected with described input signal end, and source electrode is connected with described Section Point, drains to be connected with described low level signal end; The grid of described 6th thin film transistor (TFT) is connected with described first node, and source electrode is connected with described Section Point, drains to be connected with described low level signal end; The grid of described 7th thin film transistor (TFT) is connected with described first clock signal terminal, and source electrode is connected with described Section Point, drains to be connected with described compensating signal end.
In a kind of possible embodiment, in the above-mentioned shift register that the utility model embodiment provides, specifically also comprise: be connected to the 8th thin film transistor (TFT) between described second clock signal end and described Section Point; Wherein, the grid of described 8th thin film transistor (TFT) is all connected with described second clock signal end with source electrode, drains to be connected with described Section Point.
In a kind of possible embodiment, in the above-mentioned shift register that the utility model embodiment provides, described shift register also comprises: reset unit;
The control end of described reset unit is connected with reset signal end, and first input end is connected with described signal output part, and the second input end is connected with described first node, and output terminal is connected with described low level signal end;
Described reset unit, for when described reset signal end input high level, control described signal output part and described first node respectively with the conducting of described low level signal end.
In a kind of possible embodiment, in the above-mentioned shift register that the utility model embodiment provides, described reset unit, specifically comprises: the 9th thin film transistor (TFT) and the tenth thin film transistor (TFT); Wherein, the grid of described 9th thin film transistor (TFT) is connected with described reset signal end respectively with the grid of the tenth thin film transistor (TFT); The drain electrode of described 9th thin film transistor (TFT) is connected with described low level signal end respectively with the drain electrode of the tenth thin film transistor (TFT); The source electrode of described 9th thin film transistor (TFT) is connected with described signal output part; The source electrode of described tenth thin film transistor (TFT) is connected with described first node.
In a kind of possible embodiment, in the above-mentioned shift register that the utility model embodiment provides, described shift register also comprises: cut-off reset cell;
The control end of described cut-off reset cell is connected with reset signal end, and input end is connected with described first node, and output terminal is connected with described low level signal end;
Described cut-off reset cell is used for when described reset signal end input high level, controls described first node and the conducting of described low level signal end.
In a kind of possible embodiment, in the above-mentioned shift register that the utility model embodiment provides, described cut-off reset cell, specifically comprises: the 11 thin film transistor (TFT); Wherein, the grid of described 11 thin film transistor (TFT) is connected with described reset signal end, and source electrode is connected with described first node, drains to be connected with described low level signal end.
In a kind of possible embodiment, in the above-mentioned shift register that the utility model embodiment provides, described shift register also comprises: initial reset unit;
The control end of described initial reset unit is connected with frame start signal end respectively with input end, and output terminal is connected with described Section Point;
Described initial reset unit is used for when described frame start signal end input high level, draws high the current potential of described Section Point.
In a kind of possible embodiment, in the above-mentioned shift register that the utility model embodiment provides, described initial reset unit comprises: the 12 thin film transistor (TFT); Wherein, the grid of described 12 thin film transistor (TFT) is connected with described frame start signal end respectively with source electrode, drains to be connected with described Section Point.
In a kind of possible embodiment, in above-mentioned arbitrary shift register that the utility model embodiment provides, described output control unit comprises: the 13 thin film transistor (TFT) and electric capacity; Wherein, the grid of described 13 thin film transistor (TFT) is connected with described first node, and source electrode is connected with described first clock signal terminal, drains to be connected with described signal output part; Described electric capacity is connected between described first node and described signal output part.
In a kind of possible embodiment, in the above-mentioned shift register that the utility model embodiment provides, also comprise: be connected to the 14 thin film transistor (TFT) between described signal input part and described first node; Wherein, the grid of described 14 thin film transistor (TFT) is connected with described signal input part respectively with source electrode, drains to be connected with described first node.
A kind of shift register that the utility model embodiment provides, comprising: the second thin film transistor (TFT), the 4th thin film transistor (TFT), the 5th thin film transistor (TFT), 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th thin film transistor (TFT), 13 thin film transistor (TFT), the 14 thin film transistor (TFT), and electric capacity; Wherein,
The grid of described second thin film transistor (TFT) is connected with second clock signal end, and source electrode is connected with signal output part, drains to be connected with compensating signal end;
The grid of described 4th thin film transistor (TFT) is connected with Section Point, and source electrode is connected with first node, drains to be connected with described compensating signal end;
The grid of described 5th thin film transistor (TFT) is connected with signal input part, and source electrode is connected with described Section Point, drains to be connected with low level signal end;
The grid of described 6th thin film transistor (TFT) is connected with described first node, and source electrode is connected with described Section Point, drains to be connected with described low level signal end;
The grid of described 7th thin film transistor (TFT) is connected with the first clock signal terminal, and source electrode is connected with described Section Point, drains to be connected with described compensating signal end;
The grid of described 8th thin film transistor (TFT) is connected with described second clock signal end respectively with source electrode, drains to be connected with described Section Point;
The grid of described 13 thin film transistor (TFT) is connected with described first node, and source electrode is connected with described first clock signal terminal, drains to be connected with described signal output part;
The grid of described 14 thin film transistor (TFT) is connected with described signal input part respectively with source electrode, drains to be connected with described first node;
Described electric capacity, is connected between described first node and described signal output part.
In a kind of possible embodiment, the above-mentioned shift register that the utility model embodiment provides, also comprises: the first film transistor; Wherein,
The grid of described the first film transistor is connected with described compensating signal end, and source electrode is connected with described Section Point, drains to be connected with described low level signal end.
In a kind of possible embodiment, the above-mentioned shift register that the utility model embodiment provides, also comprises: the 3rd thin film transistor (TFT); Wherein,
The grid of described 3rd thin film transistor (TFT) is connected with described Section Point, and source electrode is connected with described signal output part, drains to be connected with described compensating signal end.
In a kind of possible embodiment, the above-mentioned shift register that the utility model embodiment provides, also comprises: the 9th thin film transistor (TFT) and the tenth thin film transistor (TFT); Wherein,
The grid of described 9th thin film transistor (TFT) is connected with reset signal end, and source electrode is connected with described signal output part, drains to be connected with described low level signal end;
The grid of described tenth thin film transistor (TFT) is connected with described reset signal end, and source electrode is connected with described first node, drains to be connected with described low level signal end.
In a kind of possible embodiment, the above-mentioned shift register that the utility model embodiment provides, also comprises: the 11 thin film transistor (TFT); Wherein,
The grid of described 11 thin film transistor (TFT) is connected with reset signal end, and source electrode is connected with described first node, drains to be connected with described low level signal end.
In a kind of possible embodiment, the above-mentioned shift register that the utility model embodiment provides, also comprises: the 12 thin film transistor (TFT); Wherein,
The grid of described 12 thin film transistor (TFT) is connected with frame start signal end respectively with source electrode, drains to be connected with described Section Point.
A kind of grid integrated drive electronics that the utility model embodiment provides, comprise the shift register described in above-mentioned any one of multiple series connection, except last shift register, the signal output part of all the other each shift registers is all to the signal input part input trigger pip of adjacent next shift register.
In a kind of possible embodiment, the above-mentioned grid integrated drive electronics that the utility model embodiment provides, except first shift register, the signal output part of all the other each shift registers is all to the reset signal end input reset signal of an adjacent upper shift register.
A kind of display device that the utility model embodiment provides, comprises the grid integrated drive electronics described in above-mentioned any one.
The beneficial effect of the utility model embodiment, comprising:
A kind of shift register that the utility model embodiment provides, grid integrated drive electronics and display device, add sweep time section as low level signal end use, at the compensating signal end that the Non-scanning mode time period uses as high level signal end; And the compensating signal end increased is connected with the second output terminal of drop-down control unit with the first output terminal of the first drop-down unit respectively, and the first control end of the first drop-down unit is connected with second clock signal end, 3rd control end of drop-down control unit is connected with the first clock signal terminal, first clock signal terminal and second clock signal end at the contrary signal of section input phase sweep time, at the signal of Non-scanning mode time period input low level simultaneously.Therefore, be loaded into voltage between the first control end of the first drop-down unit and the first output terminal sweep time section contrary with in the polarity of Non-scanning mode time period, equally, be loaded into voltage between the 3rd control end of drop-down control unit and the second output terminal sweep time section contrary with in the polarity of Non-scanning mode time period, threshold voltage to be drifted about with the negative sense to produce in the Non-scanning mode time period in positive excursion that section produces sweep time cancel out each other, thus reduce total drift value of threshold voltage, and then avoid the problem that the shift register job insecurity that causes due to the threshold voltage shift when working long hours easily lost efficacy.
Accompanying drawing explanation
Fig. 1 is source-drain current and gate source voltage (Ids-Vgs) performance diagram of TFT in prior art;
One of structural representation of the shift register that Fig. 2 provides for the utility model embodiment;
The sequential chart of the first clock signal terminal that Fig. 3 provides for the utility model embodiment, second clock signal end and signal compensation end;
The structural representation two of the shift register that Fig. 4 provides for the utility model embodiment;
The concrete structure schematic diagram of the shift register that Fig. 5 provides for the utility model embodiment;
The working timing figure of the shift register that Fig. 6 provides for the utility model embodiment;
The structural representation of the grid integrated drive electronics that Fig. 7 provides for the utility model embodiment.
Embodiment
Below in conjunction with accompanying drawing, a kind of shift register, grid integrated drive electronics and the display device embodiment that the utility model embodiment provides is described in detail.
The utility model embodiment provides a kind of shift register, as shown in Figure 2, comprising: output control unit 100, the first drop-down unit 200, second drop-down unit 300, and drop-down control unit 400; Wherein,
The control end of output control unit 100 is connected with signal input part Gout (n-1) by first node PU, and input end is connected with the first clock signal terminal CLK, and output terminal is connected with signal output part Gout (n); Output control unit 100 is for drawing high the current potential of first node PU when signal input part Gout (n-1) input high level, at the first clock signal terminal CLK input high level and first node PU is noble potential time, control signal output terminal Gout (n) exports the signal of high level;
First control end of the first drop-down unit 200 is connected with second clock signal end CLKB, and the second control end is connected with Section Point PD, and input end is connected with signal output part Gout (n), and output terminal is connected with compensating signal end CKV; First drop-down unit 200 for when second clock signal end CLKB input high level, control signal output terminal Gout (n) and compensating signal end CKV conducting;
The control end of the second drop-down unit 300 is connected with Section Point PD, and input end is connected with first node PU, and output terminal is connected with compensating signal end CKV; Second drop-down unit 300, for when Section Point PD is noble potential, controls first node PU and compensating signal end CKV conducting;
First control end of drop-down control unit 400 is connected with input signal end Gout (n-1), second control end is connected with first node PU, 3rd control end is connected with the first clock signal terminal CLK, input end is connected with Section Point PD, first output terminal is connected with low level signal end VGL, and the second output terminal is connected with compensating signal end CKV; Drop-down control unit 400, for when the first clock signal terminal CLK input high level, drags down the current potential of Section Point PD, and when signal input part Gout (n-1) or first node PU is noble potential, drags down the current potential of Section Point PD; Section Point PD is connected with second clock signal end CLKB;
As shown in Figure 3, the first clock signal terminal CLK and second clock signal end CLKB is contrary at the signal phase of section input sweep time, the signal of input low level the Non-scanning mode time period while; Compensating signal end CKV at the signal of section input low level sweep time, at the signal of Non-scanning mode time period input high level.
The above-mentioned shift register that the utility model embodiment provides, add sweep time section as low level signal end use, at the compensating signal end CKV that the Non-scanning mode time period uses as high level signal end; And the compensating signal end CKV increased is connected with the second output terminal of drop-down control unit 400 with the first output terminal of the first drop-down unit 200 respectively, and the first control end of the first drop-down unit 200 is connected with second clock signal end CLKB, 3rd control end of drop-down control unit 400 is connected with the first clock signal terminal CLK, first clock signal terminal CLK and second clock signal end CLKB at the contrary signal of section input phase sweep time, at the signal of Non-scanning mode time period input low level simultaneously.Due to the first clock signal terminal CLK and second clock signal end CLKB sweep time section have the time of 50% to be high level, such correspondence sweep time section have the time of 50% voltage be loaded between the first control end of the first drop-down unit 200 and the first output terminal to be forward bias, the voltage be loaded into equally between the 3rd control end of drop-down control unit 400 and the second output terminal is forward bias, easily causes the forward migration of threshold voltage.Therefore, in the above-mentioned shift register that the utility model embodiment provides, by the compensating signal end CKV increased make to be loaded into voltage between the first control end of the first drop-down unit 200 and the first output terminal sweep time section contrary with in the polarity of Non-scanning mode time period, equally, be loaded into voltage between the 3rd control end of drop-down control unit 400 and the second output terminal sweep time section contrary with in the polarity of Non-scanning mode time period, threshold voltage can be made to drift about with the negative sense to produce in the Non-scanning mode time period in positive excursion that section produces sweep time cancel out each other, thus reduce total drift value of threshold voltage, and then avoid the problem that the shift register job insecurity that causes due to the threshold voltage shift when working long hours easily lost efficacy.
In the specific implementation, in the above-mentioned shift register that the utility model embodiment provides, because Section Point PD is connected with second clock signal end CLKB, and Section Point PD is connected with the control end of the second drop-down unit 300, the output terminal of the second control end is connected with compensating signal end CKV, therefore, the second drop-down unit 300 appears in sweep time section equally and is loaded into the problem of the forward migration of the threshold voltage between control end and output terminal.
Based on this, in the above-mentioned shift register that the utility model embodiment provides, as shown in Figure 4, can also comprise: the 3rd drop-down unit 500; The control end of the 3rd drop-down unit 500 is connected with compensating signal end CKV, and input end is connected with low level signal end VGL, and output terminal is connected with Section Point PD; 3rd drop-down unit 500, for when compensating signal end CKV input high level, drags down the current potential of Section Point PD.Thus ensure to be loaded into voltage between the control end of the second drop-down unit 300 and output terminal sweep time section contrary with in the polarity of Non-scanning mode time period, threshold voltage can be made to drift about with the negative sense to produce in the Non-scanning mode time period in positive excursion that section produces sweep time cancel out each other, thus reduce total drift value of threshold voltage, and then avoid the problem that the shift register job insecurity that causes due to the threshold voltage shift when working long hours easily lost efficacy.
In the specific implementation, the 3rd drop-down unit 500 in the above-mentioned shift register that the utility model embodiment provides can have multiple concrete structure to realize its function, such as, shown in Fig. 4, can specifically comprise: the first film transistor M1; Wherein, the grid of the first film transistor M1 is connected with compensating signal end CKV, and source electrode is connected with low level signal end VGL, drains to be connected with Section Point PD.In section sweep time, due to compensating signal end CKV input low level, therefore, the first film transistor M1 is in cut-off state.In the Non-scanning mode time period, due to compensating signal end CKV input high level, therefore, the first film transistor M1 is in conducting state, and conducting Section Point PD and low level signal end VGL, drags down the current potential of Section Point PD then.
In the specific implementation, the first drop-down unit 200 in the above-mentioned shift register that the utility model embodiment provides can have multiple concrete structure to realize its function, such as, shown in Fig. 4, can specifically comprise: the second thin film transistor (TFT) M2; Wherein, the grid of the second thin film transistor (TFT) M2 is connected with second clock signal end CLKB, and source electrode is connected with signal output part Gout (n), drains to be connected with compensating signal end CKV.In section sweep time, when second clock signal end CLKB is high level, second thin film transistor (TFT) M2 is in conducting state, then Continuity signal output terminal Gout (n) and the compensating signal end CKV as low level signal end, thus remove the noise of signal output part Gout (n).Within 50% time of section sweep time, all can load forward bias between the grid of the second thin film transistor (TFT) M2 and drain electrode, easily there is positive excursion in the threshold voltage of the second thin film transistor (TFT) M2.In the Non-scanning mode time period, compensating signal end CKV is in noble potential, bias polarity between the grid and drain electrode of the second thin film transistor (TFT) M2 is contrary with section sweep time, therefore, negative sense drift can be there is in the threshold voltage of the second thin film transistor (TFT) M2, play the compensating action to the second thin film transistor (TFT) M2 threshold voltage, thus reduce the total drift value of the second thin film transistor (TFT) M2 threshold voltage.
Further, the first drop-down unit 200 in the above-mentioned shift register that the utility model embodiment provides, as shown in Figure 4, can also comprise: the second control end be connected with Section Point PD, the second input end be connected with signal output part Gout (n), the second output terminal be connected with compensating signal end CKV; First drop-down unit 200 also for when Section Point PD is noble potential, control signal output terminal Gout (n) and compensating signal end CKV conducting, thus the noise removing signal output part Gout (n).
Accordingly, the first drop-down unit 200 in the above-mentioned shift register that the utility model embodiment provides, as shown in Figure 4, can also comprise: the 3rd thin film transistor (TFT) M3; Wherein, the grid of the 3rd thin film transistor (TFT) M3 is connected with Section Point PD, and source electrode is connected with signal output part Gout (n), drains to be connected with compensating signal end CKV.In section sweep time, when Section Point PD is noble potential, 3rd thin film transistor (TFT) M3 is in conducting state, thus by signal output part Gout (n) and compensating signal end CKV conducting, the current potential of degrade signal output terminal Gout (n), removes the noise of signal output part Gout (n).Because Section Point PD is connected with second clock signal end CLKB, therefore, within 50% time of section sweep time, all can load forward bias between the grid of the 3rd thin film transistor (TFT) M3 and drain electrode, easily there is positive excursion in the threshold voltage of the 3rd thin film transistor (TFT) M3.In the Non-scanning mode time period, by the effect of the 3rd drop-down unit 500, the current potential of Section Point PD is dragged down, now, compensating signal end CKV is in noble potential, bias polarity between the grid and drain electrode of the 3rd thin film transistor (TFT) M3 is contrary with section sweep time, and therefore, negative sense drift can occur the threshold voltage of the 3rd thin film transistor (TFT) M3, play the compensating action to the 3rd thin film transistor (TFT) M3 threshold voltage, thus reduce the total drift value of the 3rd thin film transistor (TFT) M3 threshold voltage.
In the specific implementation, the second drop-down unit 300 in the above-mentioned shift register that the utility model embodiment provides can have multiple concrete structure to realize its function, such as, shown in Fig. 4, can specifically comprise: the 4th thin film transistor (TFT) M4; Wherein, the grid of the 4th thin film transistor (TFT) M4 is connected with Section Point PD, and source electrode is connected with first node PU, drains to be connected with compensating signal end CKV.In section sweep time, when Section Point PD is noble potential, 4th thin film transistor (TFT) M4 is in conducting state, thus conducting first node PU and compensating signal end CKV, and now compensating signal end CKV is electronegative potential, therefore can by drop-down for first node PU be low level, remove the noise of first node PU.Because Section Point PD is connected with second clock signal end CLKB, therefore, within 50% time of section sweep time, all can load forward bias between the grid of the 4th thin film transistor (TFT) M4 and drain electrode, easily there is positive excursion in the threshold voltage of the 4th thin film transistor (TFT) M4.In the Non-scanning mode time period, compensating signal end CKV is in noble potential, bias polarity between the grid and drain electrode of the 4th thin film transistor (TFT) M4 is contrary with section sweep time, therefore, negative sense drift can be there is in the threshold voltage of the 4th thin film transistor (TFT) M4, play the compensating action to the 4th thin film transistor (TFT) M4 threshold voltage, thus reduce the total drift value of the 4th thin film transistor (TFT) M4 threshold voltage.
In the specific implementation, drop-down control unit 400 in the above-mentioned shift register that the utility model embodiment provides can have multiple concrete structure to realize its function, such as shown in Fig. 4, can specifically comprise: the 5th thin film transistor (TFT) M5,6th thin film transistor (TFT) M6, and the 7th thin film transistor (TFT) M7; Wherein,
The grid of the 5th thin film transistor (TFT) M5 is connected with signal input part Gout (n-1), and source electrode is connected with Section Point PD, drains to be connected with low level signal end VGL;
The grid of the 6th thin film transistor (TFT) M6 is connected with first node PU, and source electrode is connected with Section Point PD, drains to be connected with low level signal end VGL;
The grid of the 7th thin film transistor (TFT) M7 is connected with the first clock signal terminal CLK, and source electrode is connected with Section Point PD, drains to be connected with compensating signal end CKV.
In section sweep time, during signal input part Gout (n-1) input high level, the 5th thin film transistor (TFT) M5 is in conducting state; The current potential of first node PU can be drawn high during synchronous signal input end Gout (n-1) input high level, the 6th thin film transistor (TFT) M6 is made to be in conducting state, thus by Section Point PD current potential and low level signal end VGL conducting, remove the noise of Section Point PD.Further, when the first clock signal terminal CLK input high level, the 7th thin film transistor (TFT) M7 also can be in conducting state, thus by Section Point PD and compensating signal end CKV conducting, removes the noise of Section Point PD.Due to the effect of the first clock signal terminal CLK, within 50% time of section sweep time, all can load forward bias between the grid of the 7th thin film transistor (TFT) M7 and drain electrode, easily there is positive excursion in the threshold voltage of the 7th thin film transistor (TFT) M7.In the Non-scanning mode time period, compensating signal end CKV is in noble potential, bias polarity between the grid and drain electrode of the 7th thin film transistor (TFT) M7 is contrary with section sweep time, therefore, negative sense drift can be there is in the threshold voltage of the 7th thin film transistor (TFT) M7, play the compensating action to the 7th thin film transistor (TFT) M7 threshold voltage, thus reduce the total drift value of the 7th thin film transistor (TFT) M7 threshold voltage.
Further, in the above-mentioned shift register that the utility model embodiment provides, in section sweep time, in order to ensure at second clock signal end CLKB and first node PU simultaneously for Section Point PD during noble potential can be dragged down, as shown in Figure 4, can also comprise: be connected to the 8th thin film transistor (TFT) M8 between second clock signal end CKV and Section Point PD; Wherein, the grid of the 8th thin film transistor (TFT) M8 is all connected with second clock signal end CLKB with source electrode, drains to be connected with Section Point PD.In the specific implementation, 6th thin film transistor (TFT) M6 can be arranged to the size that size is greater than the 8th thin film transistor (TFT) M8, the resistance of the 6th thin film transistor (TFT) M6 is made to be less than the resistance of the 8th thin film transistor (TFT) M8 like this, ensure, when the 6th thin film transistor (TFT) M6 and the 8th thin film transistor (TFT) M8 is in conducting state simultaneously, the current potential of Section Point PD to be dragged down.
Further, in the specific implementation, in order to ensure the time period after signal output part Gout (n) exports high level signal, the current potential of signal output part Gout (n) and first node PU can be dragged down, avoid output noise signal, in the above-mentioned shift register that the utility model embodiment provides, as shown in Figure 4, can also comprise: reset unit 600; The control end of reset unit 600 is connected with reset signal end Gout (n+1), and first input end is connected with signal output part Gout (n), and the second input end is connected with first node PU, and output terminal is connected with low level signal end VGL; Reset unit 600 for when reset signal end Gout (n+1) input high level, control signal output terminal Gout (n) and first node PU respectively with low level signal end VGL conducting.
In the specific implementation, the reset unit 600 in the above-mentioned shift register that the utility model embodiment provides can have multiple concrete structure to realize its function, such as, shown in Fig. 4, can specifically comprise: the 9th thin film transistor (TFT) M9 and the tenth thin film transistor (TFT) M10; Wherein,
The grid of the 9th thin film transistor (TFT) M9 is connected with reset signal end Gout (n+1) respectively with the grid of the tenth thin film transistor (TFT) M10;
The drain electrode of the 9th thin film transistor (TFT) M9 is connected with low level signal end VGL respectively with the drain electrode of the tenth thin film transistor (TFT) M10;
The source electrode of the 9th thin film transistor (TFT) M9 is connected with signal output part Gout (n); The source electrode of the tenth thin film transistor (TFT) M10 is connected with first node PU.
In section sweep time, during reset signal end Gout (n+1) input high level, thin film transistor (TFT) M9 and thin film transistor (TFT) M10 is all in conducting state, thus dragged down the current potential of first node PU and signal output part Gout (n), remove the noise of first node PU and signal output part Gout (n).
Further, in the specific implementation, in the above-mentioned shift register that the utility model embodiment provides, as shown in Figure 4, can also comprise: cut-off reset cell 700, wherein, the control end of cut-off reset cell 700 is connected with reset signal end T_RST, input end is connected with described first node PU, and output terminal is connected with low level signal end VGL; Cut-off reset cell 700, for when reset signal end T_RST input high level, controls first node PU and low level signal end VGL conducting.Like this, the current potential of first node can be dragged down after the every frame end scanning of section sweep time.
In the specific implementation, the cut-off reset cell 700 in the above-mentioned shift register that the utility model embodiment provides can have multiple concrete structure to realize its function, such as, shown in Fig. 4, can specifically comprise: the 11 thin film transistor (TFT) M11; Wherein, the grid of the 11 thin film transistor (TFT) M11 is connected with reset signal end T_RST, and source electrode is connected with first node PU, drains to be connected with low level signal end VGL.Reset signal end T_RST input high level after the every frame end scanning of section sweep time, thin film transistor (TFT) M11 is in conducting state, by first node PU and low level signal end VGL conducting, drags down the current potential of first node PU, removes the noise of first node PU.
Further, in the specific implementation, in the above-mentioned shift register that the utility model embodiment provides, as shown in Figure 4, can also comprise: initial reset unit 800; Wherein, the control end of initial reset unit 800 is connected with frame start signal end STV respectively with input end, and output terminal is connected with Section Point PD; Initial reset unit 800, for when frame start signal end STV input high level, draws high the current potential of Section Point PD.Like this when Section Point PD is noble potential, can conducting the 3rd thin film transistor (TFT) M3 and the 4th thin film transistor (TFT) M4, then drag down the current potential of first node PU and signal output part Gout (n) respectively, avoid the output of noise.
In the specific implementation, the initial reset unit 800 in the above-mentioned shift register that the utility model embodiment provides can have multiple concrete structure to realize its function, such as, shown in Fig. 4, can specifically comprise: the 12 thin film transistor (TFT) M12; Wherein, the grid of the 12 thin film transistor (TFT) M12 is connected with frame start signal end STV respectively with source electrode, drains to be connected with Section Point PD.In section sweep time, the frame start signal end STV input high level signal when every frame starts to scan, thin film transistor (TFT) M12 is in conducting state, then the current potential of Section Point PD is drawn high, thus conducting membrane transistor M3 and thin film transistor (TFT) M4, drag down the current potential of first node PU and signal output part Gout (n), remove the noise of first node PU and signal output part Gout (n).
In the specific implementation, the output control unit 100 in the above-mentioned shift register that the utility model embodiment provides can have multiple concrete structure to realize its function, such as, shown in Fig. 4, can specifically comprise: the 13 thin film transistor (TFT) M13 and electric capacity C1; Wherein, the grid of the 13 thin film transistor (TFT) M13 is connected with first node PU, and source electrode is connected with the first clock signal terminal CLK, and drain electrode is connected with signal output part Gout (n); Electric capacity is connected between first node CLK and signal output part Gout (n).In section sweep time, when signal input part Gout (n-1) input high level, first node PU is pulled to noble potential, like this, 13 thin film transistor (TFT) M13 is in conducting state, charge, and now the first clock signal terminal CLK is electronegative potential to electric capacity C1, therefore, signal output part Gout (n) can not export the signal of noble potential.At subsequent time, when first clock signal terminal CLK is noble potential, due to the boot strap of electric capacity C1, first node PU current potential is further drawn high, 13 thin film transistor (TFT) M13 is held open state, the signal of the first clock signal terminal CLK outputs to signal output part Gout (n) through the 13 transistor M13, now, and the signal of the high level that signal output part Gout (n) exports.
Further, in order to prevent after signal input part Gout (n-1) input high level signal charges to first node PU, after signal input part Gout (n-1) becomes low level, first node PU produces electric discharge, in the above-mentioned shift register that the utility model embodiment provides, as shown in Figure 4, can also comprise: be connected to the 14 thin film transistor (TFT) M14 between signal input part Gout (n-1) and first node PU; Wherein, the grid of the 14 thin film transistor (TFT) M14 is connected with signal input part Gout (n-1) respectively with source electrode, drains to be connected with first node PU.The existence of the 14 thin film transistor (TFT) M14 can prevent first node PU from signal input part Gout (n-1) electric discharge, makes first node PU remain on the state of noble potential.
Below in conjunction with the shift register shown in Fig. 5 concrete structure figure and Fig. 6 shown in the input and output sequential chart of Fig. 5, the course of work of the shift register that the utility model embodiment provides is described.Particularly, choose in Fig. 6 sweep time section six stages of T1 ~ T6.Represent high level signal with 1 in following description, 0 represents low level signal.
In the T1 stage, STV=1, CLKB=0, Gout (n-1)=0, CLK=0, Gout (n+1)=0, T_RST=0, CKV=0.Due to STV=1, therefore, 12 thin film transistor (TFT) M12 is in conducting state, then the current potential of Section Point is drawn high by the 12 thin film transistor (TFT) M12 of conducting by frame start signal end STV, the Section Point PD of noble potential makes the 3rd thin film transistor (TFT) M3 and the 4th thin film transistor (TFT) M4 be in conducting state, thus by signal output part Gout (n) and first node PU respectively with compensating signal end CKV conducting, drag down the current potential of signal output part Gout (n) and first node PU respectively, avoid signal output part Gout (n) output noise.
In the T2 stage, STV=0, CLKB=1, Gout (n-1)=1, CLK=0, Gout (n+1)=0, T_RST=0, CKV=0.Due to CLKB=1, therefore the second thin film transistor (TFT) M2 conducting, drags down the current potential of signal output part Gout (n) then.Due to Gout (n-1)=1, therefore the 5th thin film transistor (TFT) M5 conducting, drags down the current potential of Section Point PD.Simultaneously, due to Gout (n-1)=1,14 thin film transistor (TFT) M14 conducting, drawn high by the current potential of first node PU, like this, the 13 thin film transistor (TFT) M13 is in conducting state, electric capacity C1 is charged, and now CLK=0, therefore, signal output part Gout (n) can not export the signal of noble potential.Further, the first node PU being in noble potential makes the 6th thin film transistor (TFT) M6 conducting, also can drag down the current potential of Section Point PD.
In the T3 stage, STV=0, CLKB=0, Gout (n-1)=0, CLK=1, Gout (n+1)=0, T_RST=0, CKV=0.Due to CLK=1, therefore the 7th thin film transistor (TFT) M7 conducting, keeps the electronegative potential of Section Point PD.Simultaneously, when CLK=1 due to the boot strap of electric capacity C1, the current potential of first node PU is drawn high further, 13 thin film transistor (TFT) M13 is held open state, the signal of the first clock signal terminal CLK outputs to signal output part Gout (n) through the 13 transistor M13, now, the signal of high level that exports of signal output part Gout (n).
In the T4 stage, STV=0, CLKB=1, Gout (n-1)=0, CLK=0, Gout (n+1)=1, T_RST=0, CKV=0.Due to Gout (n+1)=1, therefore the 9th thin film transistor (TFT) M9 and the tenth thin film transistor (TFT) M10 conducting, respectively the current potential of signal output part Gout (n) and first node PU is dragged down, remove the noise of signal output part Gout (n) and first node PU.Due to CLKB=1, therefore Section Point PD is noble potential, thus conducting the 3rd thin film transistor (TFT) M3 and the 4th thin film transistor (TFT) M4, also can respectively signal output part Gout (n) and first node PU current potential be dragged down, meanwhile, due to CLKB=1, therefore the second thin film transistor (TFT) M2 also can conducting, then the current potential of signal output part Gout (n) is dragged down, signal output part Gout (n) output low level.
In the T5 stage, STV=0, CLKB=0, Gout (n-1)=0, CLK=1, Gout (n+1)=0, T_RST=0, CKV=0.Due to CLK=1, therefore the 7th thin film transistor (TFT) M7 conducting, drags down the current potential of Section Point PD.First node PU keeps electronegative potential.
And, between the T5-T6 stage, second clock signal CLKB is periodically for Section Point PD charges, when Section Point PD is noble potential, 3rd thin film transistor (TFT) M3 and the 4th thin film transistor (TFT) M4 conducting, for first node PU and signal output part Gout (n) remove noise.
In the T6 stage, STV=0, CLKB=0, Gout (n-1)=0, CLK=0, Gout (n+1)=0, T_RST=1, CKV=0.Due to T_RST=1, therefore the 11 thin film transistor (TFT) M11 conducting, makes first node PU keep electronegative potential.
In the Non-scanning mode time period, STV=0, CLKB=0, Gout (n-1)=0, CLK=0, Gout (n+1)=0, T_RST=0, CKV=1.Due to CKV=1, therefore, the first film transistor M1 conducting, the current potential of Section Point PD is dragged down, thus ensure to load reverse biased between the grid and drain electrode of the second thin film transistor (TFT) M2, the 3rd thin film transistor (TFT) M3, the 4th thin film transistor (TFT) M4 and the 7th thin film transistor (TFT) M7, the threshold voltage generation negative sense of the second thin film transistor (TFT) M2, the 3rd thin film transistor (TFT) M3, the 4th thin film transistor (TFT) M4 and the 7th thin film transistor (TFT) M7 is drifted about, play the compensating action to threshold voltage, decrease the drift value that threshold voltage is total.
Conceive based on same utility model, the utility model embodiment provides a kind of shift register, as shown in Figure 5, comprising: the second thin film transistor (TFT) M2,4th thin film transistor (TFT) M4,5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7,8th thin film transistor (TFT) M8,13 thin film transistor (TFT) M13, the 14 thin film transistor (TFT) M14, and electric capacity C1; Wherein,
The grid of the second thin film transistor (TFT) M2 is connected with second clock signal end CLKB, and source electrode is connected with signal output part Gout (n), drains to be connected with compensating signal end CLK;
The grid of the 4th thin film transistor (TFT) M4 is connected with Section Point PD, and source electrode is connected with first node PU, drains to be connected with described compensating signal end CLK;
The grid of the 5th thin film transistor (TFT) M5 is connected with signal input part Gout (n-1), and source electrode is connected with Section Point PD, drains to be connected with low level signal end VGL;
The grid of the 6th thin film transistor (TFT) M6 is connected with first node PU, and source electrode is connected with Section Point PD, drains to be connected with low level signal end VGL;
The grid of the 7th thin film transistor (TFT) M7 is connected with the first clock signal terminal CLK, and source electrode is connected with Section Point PD, drains to be connected with compensating signal end CLK;
The grid of the 8th thin film transistor (TFT) M8 is connected with second clock signal end CLKB respectively with source electrode, drains to be connected with Section Point PD;
The grid of the 13 thin film transistor (TFT) M13 is connected with first node PU, and source electrode is connected with the first clock signal terminal CLK, and drain electrode is connected with signal output part Gout (n);
The grid of the 14 thin film transistor (TFT) M14 is connected with signal input part Gout (n-1) respectively with source electrode, drains to be connected with first node PU;
Electric capacity C1, is connected between first node PU and signal output part Gout (n).
In the specific implementation, at the above-mentioned shift register that the utility model embodiment provides, as shown in Figure 5, can also comprise: the first film transistor M1; Wherein,
The grid of the first film transistor M1 is connected with compensating signal end CLK, and source electrode is connected with Section Point PD, drains to be connected with low level signal end VGL.
In the specific implementation, at the above-mentioned shift register that the utility model embodiment provides, as shown in Figure 5, can also comprise: the 3rd thin film transistor (TFT) M3; Wherein,
The grid of the 3rd thin film transistor (TFT) M3 is connected with Section Point PD, and source electrode is connected with signal output part Gout (n), drains to be connected with compensating signal end CLK.
In the specific implementation, at the above-mentioned shift register that the utility model embodiment provides, as shown in Figure 5, can also comprise: the 9th thin film transistor (TFT) M9 and the tenth thin film transistor (TFT) M10; Wherein,
The grid of the 9th thin film transistor (TFT) M9 is connected with reset signal end Gout (n+1), and source electrode is connected with signal output part Gout (n), drains to be connected with low level signal end VGL;
The grid of the tenth thin film transistor (TFT) M10 is connected with reset signal end Gout (n+1), and source electrode is connected with first node PU, drains to be connected with low level signal end VGL.
In the specific implementation, at the above-mentioned shift register that the utility model embodiment provides, as shown in Figure 5, can also comprise: the 11 thin film transistor (TFT) M11; Wherein,
The grid of the 11 thin film transistor (TFT) M11 is connected with reset signal end T_RST, and source electrode is connected with first node PU, drains to be connected with low level signal end VGL.
In the specific implementation, at the above-mentioned shift register that the utility model embodiment provides, as shown in Figure 5, can also comprise: the 12 thin film transistor (TFT) M12; Wherein,
The grid of the 12 thin film transistor (TFT) M12 is connected with frame start signal end STV respectively with source electrode, drains to be connected with Section Point PD.
Conceive based on same utility model, the utility model embodiment still provides a kind of grid integrated drive electronics, as shown in Figure 7, the above-mentioned shift register that the multiple the utility model embodiments specifically comprising series connection provide, except last shift register, signal output part Gout (n) of all the other each shift registers all inputs trigger pip to the signal input part Gout (n-1) of adjacent next shift register.
Further, in the above-mentioned grid integrated drive electronics that the utility model embodiment provides, except first shift register, signal output part Gout (n) of all the other each shift registers all inputs reset signal to the reset signal end Gout (n+1) of an adjacent upper shift register.
Fig. 7 shows the structural representation of the grid integrated drive electronics be made up of five shift registers, wherein, signal output part Gout (n) of N level shift register, not only to N-1 level shift register output reset signal, simultaneously also to N+1 level shift register output trigger pip.
Conceive based on same utility model, the utility model embodiment still provides a kind of display device, specifically comprise the above-mentioned grid integrated drive electronics that the utility model embodiment provides, by this grid integrated drive electronics for each grid line on array base palte in display device provides sweep signal, it is specifically implemented can see the description of above-mentioned grid integrated drive electronics, and something in common repeats no more.
A kind of shift register that the utility model embodiment provides, grid integrated drive electronics and display device, add sweep time section as low level signal end use, at the compensating signal end that the Non-scanning mode time period uses as high level signal end; And the compensating signal end increased is connected with the second output terminal of drop-down control unit with the first output terminal of the first drop-down unit respectively, and the first control end of the first drop-down unit is connected with second clock signal end, 3rd control end of drop-down control unit is connected with the first clock signal terminal, first clock signal terminal and second clock signal end at the contrary signal of section input phase sweep time, at the signal of Non-scanning mode time period input low level simultaneously.Therefore, be loaded into voltage between the first control end of the first drop-down unit and the first output terminal sweep time section contrary with in the polarity of Non-scanning mode time period, equally, be loaded into voltage between the 3rd control end of drop-down control unit and the second output terminal sweep time section contrary with in the polarity of Non-scanning mode time period, threshold voltage to be drifted about with the negative sense to produce in the Non-scanning mode time period in positive excursion that section produces sweep time cancel out each other, thus reduce total drift value of threshold voltage, and then avoid the problem that the shift register job insecurity that causes due to the threshold voltage shift when working long hours easily lost efficacy.
Obviously, those skilled in the art can carry out various change and modification to the utility model and not depart from spirit and scope of the present utility model.Like this, if these amendments of the present utility model and modification belong within the scope of the utility model claim and equivalent technologies thereof, then the utility model is also intended to comprise these change and modification.
Claims (26)
1. a shift register, is characterized in that, comprising: output control unit, the first drop-down unit, the second drop-down unit, and drop-down control unit; Wherein,
The control end of described output control unit is connected with signal input part by first node, and input end is connected with the first clock signal terminal, and output terminal is connected with signal output part; Described output control unit is used for the current potential drawing high described first node when described signal input part input high level, at described first clock signal terminal input high level and described first node is noble potential time, control described signal output part and export the signal of high level;
First control end of described first drop-down unit is connected with second clock signal end, and input end is connected with described signal output part, and the first output terminal is connected with compensating signal end; Described first drop-down unit is used for when described second clock signal end input high level, controls described signal output part and the conducting of described compensating signal end;
The control end of described second drop-down unit is connected with Section Point, and input end is connected with described first node, and output terminal is connected with described compensating signal end; Described second drop-down unit is used for when described Section Point is noble potential, controls described first node and the conducting of described compensating signal end;
First control end of described drop-down control unit is connected with described input signal end, second control end is connected with described first node, 3rd control end is connected with described first clock signal terminal, input end is connected with described Section Point, first output terminal is connected with low level signal end, and the second output terminal is connected with described compensating signal end; Described drop-down control unit is used for when described first clock signal terminal input high level, drags down the current potential of described Section Point, and when described signal input part or described first node are noble potential, drags down the current potential of described Section Point; Described Section Point is connected with described second clock signal end;
Described first clock signal terminal is contrary at the signal phase of section input sweep time with second clock signal end, the signal of input low level the Non-scanning mode time period while; Described compensating signal end at the signal of section input low level sweep time, at the signal of Non-scanning mode time period input high level.
2. shift register as claimed in claim 1, is characterized in that, also comprise: the 3rd drop-down unit; The control end of described 3rd drop-down unit is connected with described compensating signal end, and input end is connected with described low level signal end, and output terminal is connected with described Section Point; Described 3rd drop-down unit is used for when described compensating signal end input high level, drags down the current potential of described Section Point.
3. shift register as claimed in claim 2, it is characterized in that, described 3rd drop-down unit, specifically comprises: the first film transistor; Wherein, the grid of described the first film transistor is connected with described compensating signal end, and source electrode is connected with described low level signal end, drains to be connected with described Section Point.
4. shift register as claimed in claim 1, it is characterized in that, described first drop-down unit, specifically comprises: the second thin film transistor (TFT); Wherein, the grid of described second thin film transistor (TFT) is connected with described second clock signal end, and source electrode is connected with described signal output part, drains to be connected with described compensating signal end.
5. shift register as claimed in claim 4, it is characterized in that, described first drop-down unit also comprises: the second control end be connected with described Section Point, the second input end be connected with described signal output part, the second output terminal be connected with described compensating signal end; Described first drop-down unit, also for when described Section Point is noble potential, controls described signal output part and the conducting of described compensating signal end.
6. shift register as claimed in claim 5, it is characterized in that, described first drop-down unit, also comprises: the 3rd thin film transistor (TFT); Wherein, the grid of described 3rd thin film transistor (TFT) is connected with described Section Point, and source electrode is connected with described signal output part, drains to be connected with described compensating signal end.
7. shift register as claimed in claim 1, it is characterized in that, described second drop-down unit, specifically comprises: the 4th thin film transistor (TFT); Wherein, the grid of described 4th thin film transistor (TFT) is connected with described Section Point, and source electrode is connected with described first node, drains to be connected with described compensating signal end.
8. shift register as claimed in claim 1, it is characterized in that, described drop-down control unit, specifically comprises: the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), and the 7th thin film transistor (TFT); Wherein,
The grid of described 5th thin film transistor (TFT) is connected with described input signal end, and source electrode is connected with described Section Point, drains to be connected with described low level signal end;
The grid of described 6th thin film transistor (TFT) is connected with described first node, and source electrode is connected with described Section Point, drains to be connected with described low level signal end;
The grid of described 7th thin film transistor (TFT) is connected with described first clock signal terminal, and source electrode is connected with described Section Point, drains to be connected with described compensating signal end.
9. shift register as claimed in claim 8, is characterized in that, also comprise: be connected to the 8th thin film transistor (TFT) between described second clock signal end and described Section Point; Wherein,
The grid of described 8th thin film transistor (TFT) is all connected with described second clock signal end with source electrode, drains to be connected with described Section Point.
10. shift register as claimed in claim 1, is characterized in that, also comprise: reset unit;
The control end of described reset unit is connected with reset signal end, and first input end is connected with described signal output part, and the second input end is connected with described first node, and output terminal is connected with described low level signal end;
Described reset unit, for when described reset signal end input high level, control described signal output part and described first node respectively with the conducting of described low level signal end.
11. shift registers as claimed in claim 10, it is characterized in that, described reset unit, specifically comprises: the 9th thin film transistor (TFT) and the tenth thin film transistor (TFT); Wherein,
The grid of described 9th thin film transistor (TFT) is connected with described reset signal end respectively with the grid of the tenth thin film transistor (TFT);
The drain electrode of described 9th thin film transistor (TFT) is connected with described low level signal end respectively with the drain electrode of the tenth thin film transistor (TFT);
The source electrode of described 9th thin film transistor (TFT) is connected with described signal output part; The source electrode of described tenth thin film transistor (TFT) is connected with described first node.
12. shift registers as claimed in claim 1, is characterized in that, also comprise: cut-off reset cell;
The control end of described cut-off reset cell is connected with reset signal end, and input end is connected with described first node, and output terminal is connected with described low level signal end;
Described cut-off reset cell is used for when described reset signal end input high level, controls described first node and the conducting of described low level signal end.
13. shift registers as claimed in claim 12, it is characterized in that, described cut-off reset cell, specifically comprises: the 11 thin film transistor (TFT); Wherein, the grid of described 11 thin film transistor (TFT) is connected with described reset signal end, and source electrode is connected with described first node, drains to be connected with described low level signal end.
14. shift registers as described in any one of claim 1-13, is characterized in that, also comprise: initial reset unit;
The control end of described initial reset unit is connected with frame start signal end respectively with input end, and output terminal is connected with described Section Point;
Described initial reset unit is used for when described frame start signal end input high level, draws high the current potential of described Section Point.
15. shift registers as claimed in claim 14, it is characterized in that, described initial reset unit, comprising: the 12 thin film transistor (TFT); Wherein, the grid of described 12 thin film transistor (TFT) is connected with described frame start signal end respectively with source electrode, drains to be connected with described Section Point.
16. shift registers as described in any one of claim 1-13, it is characterized in that, described output control unit comprises: the 13 thin film transistor (TFT) and electric capacity; Wherein,
The grid of described 13 thin film transistor (TFT) is connected with described first node, and source electrode is connected with described first clock signal terminal, drains to be connected with described signal output part;
Described electric capacity is connected between described first node and described signal output part.
17. shift registers as claimed in claim 16, is characterized in that, also comprise: be connected to the 14 thin film transistor (TFT) between described signal input part and described first node; Wherein, the grid of described 14 thin film transistor (TFT) is connected with described signal input part respectively with source electrode, drains to be connected with described first node.
18. 1 kinds of shift registers, is characterized in that, comprising: the second thin film transistor (TFT), the 4th thin film transistor (TFT), 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th thin film transistor (TFT), 13 thin film transistor (TFT), the 14 thin film transistor (TFT), and electric capacity; Wherein,
The grid of described second thin film transistor (TFT) is connected with second clock signal end, and source electrode is connected with signal output part, drains to be connected with compensating signal end;
The grid of described 4th thin film transistor (TFT) is connected with Section Point, and source electrode is connected with first node, drains to be connected with described compensating signal end;
The grid of described 5th thin film transistor (TFT) is connected with signal input part, and source electrode is connected with described Section Point, drains to be connected with low level signal end;
The grid of described 6th thin film transistor (TFT) is connected with described first node, and source electrode is connected with described Section Point, drains to be connected with described low level signal end;
The grid of described 7th thin film transistor (TFT) is connected with the first clock signal terminal, and source electrode is connected with described Section Point, drains to be connected with described compensating signal end;
The grid of described 8th thin film transistor (TFT) is connected with described second clock signal end respectively with source electrode, drains to be connected with described Section Point;
The grid of described 13 thin film transistor (TFT) is connected with described first node, and source electrode is connected with described first clock signal terminal, drains to be connected with described signal output part;
The grid of described 14 thin film transistor (TFT) is connected with described signal input part respectively with source electrode, drains to be connected with described first node;
Described electric capacity, is connected between described first node and described signal output part.
19. shift registers as claimed in claim 18, is characterized in that, also comprise: the first film transistor; Wherein,
The grid of described the first film transistor is connected with described compensating signal end, and source electrode is connected with described Section Point, drains to be connected with described low level signal end.
20. shift registers as claimed in claim 18, is characterized in that, also comprise: the 3rd thin film transistor (TFT); Wherein,
The grid of described 3rd thin film transistor (TFT) is connected with described Section Point, and source electrode is connected with described signal output part, drains to be connected with described compensating signal end.
21. shift registers as claimed in claim 18, is characterized in that, also comprise: the 9th thin film transistor (TFT) and the tenth thin film transistor (TFT); Wherein,
The grid of described 9th thin film transistor (TFT) is connected with reset signal end, and source electrode is connected with described signal output part, drains to be connected with described low level signal end;
The grid of described tenth thin film transistor (TFT) is connected with described reset signal end, and source electrode is connected with described first node, drains to be connected with described low level signal end.
22. shift registers as claimed in claim 18, is characterized in that, also comprise: the 11 thin film transistor (TFT); Wherein,
The grid of described 11 thin film transistor (TFT) is connected with reset signal end, and source electrode is connected with described first node, drains to be connected with described low level signal end.
23. shift registers as claimed in claim 18, is characterized in that, also comprise: the 12 thin film transistor (TFT); Wherein,
The grid of described 12 thin film transistor (TFT) is connected with frame start signal end respectively with source electrode, drains to be connected with described Section Point.
24. 1 kinds of grid integrated drive electronicss, it is characterized in that, comprise the shift register as described in any one of claim 1-23 of multiple series connection, except last shift register, the signal output part of all the other each shift registers is all to the signal input part input trigger pip of adjacent next shift register.
25. grid integrated drive electronicss as claimed in claim 24, is characterized in that, except first shift register, the signal output part of all the other each shift registers is all to the reset signal end input reset signal of an adjacent upper shift register.
26. 1 kinds of display device, is characterized in that, comprise the grid integrated drive electronics as described in claim 24 or 25.
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| CN201520848146.1U CN205069085U (en) | 2015-10-28 | 2015-10-28 | Shift register , grid integrated drive electronics and display device |
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| CN201520848146.1U CN205069085U (en) | 2015-10-28 | 2015-10-28 | Shift register , grid integrated drive electronics and display device |
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| CN205069085U true CN205069085U (en) | 2016-03-02 |
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| CN105206243A (en) * | 2015-10-28 | 2015-12-30 | 京东方科技集团股份有限公司 | Shift register, gate electrode integrated drive circuit and display device |
| CN105702225A (en) * | 2016-04-27 | 2016-06-22 | 京东方科技集团股份有限公司 | Grid driving circuit and driving method thereof, array substrate and display device |
| CN106652958A (en) * | 2017-01-16 | 2017-05-10 | 昆山龙腾光电有限公司 | Gate drive circuit and control method |
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| WO2018192026A1 (en) * | 2017-04-21 | 2018-10-25 | 深圳市华星光电半导体显示技术有限公司 | Scan drive circuit |
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- 2015-10-28 CN CN201520848146.1U patent/CN205069085U/en not_active Withdrawn - After Issue
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| CN105206243A (en) * | 2015-10-28 | 2015-12-30 | 京东方科技集团股份有限公司 | Shift register, gate electrode integrated drive circuit and display device |
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| CN105206243B (en) * | 2015-10-28 | 2017-10-17 | 京东方科技集团股份有限公司 | A kind of shift register, grid integrated drive electronics and display device |
| US10192504B2 (en) | 2015-10-28 | 2019-01-29 | Boe Technology Group Co., Ltd | Shift register, GOA circuit containing the same, and related display device |
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| CN105702225B (en) * | 2016-04-27 | 2018-09-04 | 京东方科技集团股份有限公司 | Gate driving circuit and its driving method and display device |
| CN106652958A (en) * | 2017-01-16 | 2017-05-10 | 昆山龙腾光电有限公司 | Gate drive circuit and control method |
| WO2018192026A1 (en) * | 2017-04-21 | 2018-10-25 | 深圳市华星光电半导体显示技术有限公司 | Scan drive circuit |
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| CN107452318A (en) * | 2017-09-20 | 2017-12-08 | 京东方科技集团股份有限公司 | Reset control module, its driving method and shift register cell, display device |
| CN112639953A (en) * | 2018-09-26 | 2021-04-09 | 深圳市柔宇科技股份有限公司 | GOA circuit, array substrate and display device |
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Inventor after: Han Mingfu Inventor after: Han Chengyou Inventor after: Shang Guangliang Inventor after: Cui Xianzhi Inventor after: Yao Xing Inventor after: Zheng Haoliang Inventor after: Dong Xue Inventor after: Tian Zhengmu Inventor after: Lin Yunzhi Inventor before: Han Mingfu Inventor before: Han Chengyou Inventor before: Shang Guangliang Inventor before: Jin Zhihe Inventor before: Yao Xing Inventor before: Zheng Haoliang Inventor before: Dong Xue Inventor before: Tian Zhengmu Inventor before: Lin Yunzhi |
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Granted publication date: 20160302 Effective date of abandoning: 20171017 |