CN112639953A

CN112639953A - GOA circuit, array substrate and display device

Info

Publication number: CN112639953A
Application number: CN201880094223.5A
Authority: CN
Inventors: 颜尧
Original assignee: Shenzhen Royole Technologies Co Ltd
Current assignee: Shenzhen Royole Technologies Co Ltd
Priority date: 2018-09-26
Filing date: 2018-09-26
Publication date: 2021-04-09
Also published as: WO2020061802A1

Abstract

The embodiment of the invention discloses a GOA circuit, an array substrate and a display device, wherein the GOA circuit comprises cascaded multi-stage GOA units, and the GOA units comprise: the pull-up module (220; 320), the pull-up module (220; 320) includes the first node (PU), the voltage signal at the first node (PU) is used for controlling the output of the scanning signal, the first node (PU) has a maintaining stage for maintaining high level in one period of the GOA circuit; the pull-down control module (230; 330; 430) includes a fifth thin film transistor (M5), a second terminal of the fifth thin film transistor (M5) is electrically connected with the low level signal line (250), a first terminal is electrically connected with the first node (PU), a gate is electrically connected with the second node (PD), the second node (PD) is used for receiving a pull-down control signal, and when the first node (PU) is in a maintaining stage, the voltage at the second node (PD) is pulled down to a low level by the low level signal line (250). The GOA circuit has the advantage of preventing the scanning signals after being pulled up from being turned off in advance.

Description

GOA circuit, array substrate and display device

Technical Field

The invention relates to the technical field of display, in particular to a GOA circuit, an array substrate and a display device.

Background

In recent years, a Gate driver on array (GOA) circuit is widely used in an electronic display such as an LCD and an AMOLED, and is a key part of a display panel for providing a scanning signal to a pixel matrix.

The GOA circuit includes a plurality of cascaded GOA units, fig. 1 is a circuit diagram of an nth level GOA unit in the prior art, please refer to fig. 1, the GOA unit includes a pull-up control module 110, a pull-up module 120, a pull-down control module 130, a pull-down module 140, and a low level signal line 150, where specific circuits of the pull-up control module 110, the pull-up module 120, the pull-down control module 130, and the pull-down module 140 please refer to fig. 1, which is not described herein again, where a first node PU exists in the pull-up module 120, and a voltage at the first node PU is used for controlling the third thin film transistor M3 to be turned on or turned off. Fig. 2 is a timing diagram of the GOA circuit, in conjunction with fig. 1 and 2, when the output Gout N-1 of the N-1 th stage GOA unit goes high, the first capacitor C1 is charged, when Gout N-1 goes low, the first node PU is maintained high, the third tft M3 is maintained in an on state, when one of the VDD Odd signal and the VDD Even signal is high in general, and assuming that the VDD Odd signal is high, the second tft M2 and the eighth tft M8 are turned on to form the paths of the second tft M2, the eighth tft M8 and the low signal line 150, so that the voltage at the second node PD Odd is higher than the low VGL on the low signal line 150, and also when the VDD Even signal is high, the voltage at the third node Even is higher than the low VGL on the low signal line 150, therefore, the leakage current of the fourth thin film transistors M4 and M4' is increased, the high level at the first node PU is lowered, and the third transistor M3 is turned off early, so that the pulled-up scan signal Gout N is turned off early, and the pixels in the pixel matrix are insufficiently charged.

Disclosure of Invention

The embodiment of the invention aims to solve the technical problem of providing a GOA circuit, an array substrate and a display device. The problem that the raised scanning signal is closed in advance can be prevented.

In order to solve the above technical problem, an embodiment of a first aspect of the present invention provides a GOA circuit, where the GOA circuit includes cascaded multiple levels of GOA units, and the GOA unit includes:

the pull-up control module is used for generating a scanning control signal of the current level according to the control of the scanning signal output by the GOA unit of the previous level;

the pull-up module is used for pulling up the scanning signal of the current stage according to the scanning control signal of the current stage and a clock signal, and comprises a first node, wherein a voltage signal at the first node is used for controlling the output of the scanning signal, and a maintaining stage for maintaining a high level exists in the first node in one period of the GOA circuit;

the pull-down control module is used for outputting a pull-down control signal according to the clock signal and pulling down the level signal of the first node according to the pull-down control signal;

the pull-down module is used for pulling down the scanning signal of the current stage according to the pull-down control signal;

the low-level signal line is used for outputting a low-level signal and is respectively and electrically connected with the pull-down control module and the pull-down module;

the pull-down control module comprises a fifth thin film transistor, wherein a second end of the fifth thin film transistor is electrically connected with the low level signal line, a first end of the fifth thin film transistor is electrically connected with the first node, a grid electrode of the fifth thin film transistor is electrically connected with the second node, the second node is used for receiving a pull-down control signal, and when the first node is in a maintaining stage, the voltage at the second node is pulled down to be low level by the low level signal line

In a second aspect, an embodiment of the invention provides an array substrate, including the above GOA circuit;

in an embodiment of the third aspect of the invention, a display device is provided, which includes the array substrate.

The embodiment of the invention has the following beneficial effects:

the pull-down control module comprises a fifth thin film transistor, wherein the first end of the fifth thin film transistor is electrically connected with the first node, the second end of the fifth thin film transistor is electrically connected with the low-level signal line, and the grid electrode of the fifth thin film transistor is electrically connected with the second node. When the first node is in the maintaining stage, the voltage at the second node is pulled down to be low level by the low-level signal line, the voltage at the second node is close to the same as the voltage on the low-level signal line, the fifth thin film transistor is in a closing state at the moment, the leakage current is very small, therefore, the high-level signal at the first node is reduced very little, the output of the pulled-up scanning signal cannot be closed in advance, and the problem of insufficient charging of pixels cannot occur. Moreover, the GOA unit of the invention needs fewer components and is suitable for the circuit design of narrow frames.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a circuit diagram of a prior art nth level GOA unit;

FIG. 2 is a timing diagram of a prior art GOA circuit;

fig. 3 is a circuit diagram of an nth level GOA unit according to the first embodiment of the present invention;

FIG. 4 is a timing diagram of a GOA circuit according to a first embodiment of the present invention;

fig. 5 is a circuit diagram of an nth level GOA unit according to a second embodiment of the present invention;

FIG. 6 is a timing diagram of a GOA circuit according to a second embodiment of the present invention;

fig. 7 is a circuit diagram of a third embodiment of an nth level GOA unit in accordance with the present invention;

FIG. 8 is a timing diagram of a GOA circuit according to a third embodiment of the present invention;

reference numbers of the drawings:

110. 210-a pull-up control module; 120. 220, 320-pull-up module; 130. 230, 330, 430-pull-down control module; 140. 240-a pull-down module; 150. 250-low level signal line; M1-M6-first-sixth thin film transistors; m7', M7-seventh thin film transistor; m8', M8-eighth thin film transistor; m9, M10-ninth and tenth thin film transistors; m14-a fourteenth thin film transistor; m20-twentieth thin film transistor; PU-first node; PD, PD Odd-second node; PD Even-third node; VGL-low level signal; VGH — high level signal; CK 1-first clock signal; CK 2-second clock signal; CK 3-third clock signal; CK 4-fourth clock signal.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "comprising" and "having," and any variations thereof, as appearing in the specification, claims and drawings of this application, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," and "third," etc. are used to distinguish between different objects and are not used to describe a particular order.

First embodiment

The embodiment of the invention provides a GOA circuit, wherein the GOA circuit is electrically connected with a plurality of scanning lines, each scanning line is electrically connected with the grids of a plurality of thin film transistors, the drains of the thin film transistors are electrically connected with a pixel capacitor, and the sources of the thin film transistors are used for inputting pixel voltage. The GOA circuit comprises cascaded multiple levels of GOA units, each level of GOA unit is electrically connected with one scanning line, each GOA unit outputs scanning signals to the corresponding scanning line, and a plurality of thin film transistors electrically connected with the scanning lines are turned on or turned off according to the scanning signals. In this embodiment, the GOA circuit includes M-level GOA units, wherein the second-level GOA unit is electrically connected to the first-level GOA unit, the third-level GOA unit is electrically connected to the second-level GOA unit, the fourth-level GOA unit is electrically connected to the third-level GOA unit …, the M-level GOA unit is electrically connected to the M-1-level GOA unit, and each level of GOA unit is electrically connected to one scan line. Here, taking the nth level GOA unit as an example, where N is a positive integer and 1 < N ≦ M, please refer to fig. 3, the nth level GOA unit includes a pull-up control module 210, a pull-up module 220, a pull-down control module 230, a pull-down module 240, and a low signal line 250.

In this embodiment, the pull-up control module 210 is configured to generate the scan control signal of the current stage according to the scan signal Gout N-1 output by the GOA unit of the previous stage, and the scan control signal of the current stage is output to the pull-up module 220, where the scan control signal is an output signal of the pull-up control module 210. In this embodiment, the pull-up control module 210 includes a first thin film transistor M1, a gate of the first thin film transistor M1 receives the scan signal Gout N-1 output by the previous GOA unit, a first end of the first thin film transistor M1 receives a high level signal VGH, a voltage of the high level signal VGH is always maintained at a high level, a second end of the first thin film transistor M1 is electrically connected to the pull-up module 220 and the pull-down control module 230, respectively, and a second end of the first thin film transistor M1 is an output end of the pull-up control module 210.

In this embodiment, the pull-up module 220 is configured to pull up the scan signal Gout N of the present stage according to the scan control signal and the clock signal of the present stage, so as to output the pulled-up scan signal Gout N to the corresponding scan line, where the pulled-up scan signal Gout N is a high level signal, and further control a thin film transistor electrically connected to the scan line, so as to control charging of the pixel. In the present embodiment, the pull-up module 220 includes a second thin film transistor M2 and a third thin film transistor M3. A first terminal of the second thin film transistor M2 is electrically connected to a second terminal of the first thin film transistor M1, a gate of the second thin film transistor M2 receives the high level signal VGH, and a second terminal of the second thin film transistor M2 is electrically connected to the first node PU, in this embodiment, the second thin film transistor M2 is always turned on, and in this embodiment, the first node PU is located between the second thin film transistor M2 and the third thin film transistor M3. The gate of the third thin film transistor M3 is electrically connected to the first node PU, the first terminal of the third thin film transistor M3 receives the second clock signal CK2, the second terminal of the third thin film transistor M3 is electrically connected to the corresponding scan line and the pull-down module 240, and the second terminal of the third thin film transistor M3 outputs the scan signal Gout N of the present stage. In this embodiment, the voltage signal at the first node PU is used to control the output of the scan signal Gout N, for example, when the voltage signal at the first node PU is at a high level, the third thin film transistor M3 is turned on, when the voltage signal at the first node PU is at a low level, the third thin film transistor M3 is turned off, and there is a maintaining phase of maintaining the high level at the first node PU in one cycle of the GOA circuit, which begins when the first thin film transistor M1 is turned from on to off, at which time the first node PU is maintained at the high level, until the second clock signal CK2 is turned from the high level to the low level and is turned off, that is, the output of the pulled-up scan signal Gout N at this stage is turned off, at which time the first node PU is maintained at the high level. In addition, in other embodiments of the present invention, in order to better maintain the first node PU at a high level, the pull-up module 220 may further set up a second capacitor, one electrode of which is electrically connected to the first node PU, and the other electrode of which is electrically connected to the second terminal of the third tft M3. In addition, in other embodiments of the present invention, the second tft M2 may not be provided, and the first node PU may be directly electrically connected to the second terminal of the first tft M1 by a wire. In addition, in other embodiments of the present invention, the first node PU may also be located at the first end of the second thin film transistor M2.

In this embodiment, the pull-down control module 230 is configured to output a pull-down control signal according to the clock signal, pull down the level signal of the first node PU according to the pull-down control signal, and pull down the level signal of the first node PU after the sustain stage of the first node PU according to the pull-down control signal, so as to prevent the third thin film transistor M3 from being turned on by mistake.

In this embodiment, the pull-down module 240 is configured to pull down the present-stage scan signal Gout N according to the pull-down control signal, so as to prevent the tft electrically connected to the scan line from being turned on by mistake. Specifically, the pull-down module 240 includes a fourth thin film transistor M4 and a first capacitor C1, a first terminal of the fourth thin film transistor M4 is electrically connected to the pull-up module 220, specifically, to a second terminal of the third thin film transistor M3, that is, to the scan line, a second terminal of the fourth thin film transistor M4 is electrically connected to the low-level signal line 250, and a gate of the fourth thin film transistor M4 is electrically connected to the pull-down control module 230 for receiving a pull-down control signal, where the gate of the fourth thin film transistor M4 is electrically connected to a second node PD mentioned later. One electrode of the first capacitor C1 is electrically connected to the pull-down control module 230, specifically, to the second node PD mentioned later, and the other electrode of the first capacitor C1 is electrically connected to the low-level signal line 250.

In the present embodiment, the low-level signal line 250 is used to output a low-level signal VGL, the voltage of which is always maintained at a low level, and which is electrically connected to the pull-down control module 230 and the pull-down module 240, respectively.

In order to prevent the pulled-up scan signal Gout N from being turned off in advance, in the present embodiment, the pull-down control module 230 includes a fifth thin film transistor M5, a first terminal of the fifth thin film transistor M5 is indirectly electrically connected to the first node PU, specifically, a first terminal of the fifth thin film transistor M5 is electrically connected to the first node PU via the second thin film transistor M2, a second terminal of the fifth thin film transistor M5 is electrically connected to the low-level signal line 250, a gate of the fifth thin film transistor M5 is electrically connected to a second node PD, where a voltage at the second node PD is used for controlling the fifth thin film transistor M5 to be turned on or off, and the second node PD is further used for receiving the pull-down control signal. When the first node PU is in the sustain stage, the voltage at the second node PD is pulled down to the low level by the low level signal line 250, at this time, the voltage at the second node PD is close to the same as the voltage on the low level signal line 250, at this time, the fifth thin film transistor M5 is in the off state, the leakage current is very small, so that the high level signal at the first node PU drops very little, the output of the pulled up scan signal Gout N is not turned off in advance, and the problem of insufficient pixel charging does not occur.

In the present embodiment, the pull-down control module 230 further includes sixth to tenth thin film transistors. The first end of the sixth thin film transistor M6, the first end of the eighth thin film transistor and the gate of the eighth thin film transistor receive the third clock signal CK 3; a second terminal of the sixth thin film transistor M6 is electrically connected to the second node PD, and a gate of the sixth thin film transistor M6 is electrically connected to the second terminal of the eighth thin film transistor; a first end of the seventh thin film transistor M7 is electrically connected to the second node PD, a gate of the seventh thin film transistor M7 is electrically connected to the output end of the pull-up control module 210, that is, indirectly electrically connected to the first node PU, specifically electrically connected to the first node PU via the second thin film transistor M2, and a second end of the seventh thin film transistor M7 is electrically connected to the low-level signal line 250; a second end of the eighth thin film transistor is electrically connected to a gate of a tenth thin film transistor M10, a first end of the tenth thin film transistor M10 is electrically connected to a gate of the eighth thin film transistor, a gate and a second end of the tenth thin film transistor M10 are electrically connected to a first end of a ninth thin film transistor M9, a gate of the ninth thin film transistor M9 is electrically connected to an output end of the pull-up control module 210, and a second end of the ninth thin film transistor M9 is electrically connected to the low-level signal line 250.

Now, referring to fig. 3 and 4 in conjunction with the description of the GOA unit and the timing diagram, when the scanning signal Gout N-1 output by the previous GOA unit is a high level signal, the first thin film transistor M1 of the GOA unit of this stage is turned on, since the second thin film transistor M2 is always turned on, the voltage at the first node PU is a high level, the third thin film transistor M3 is turned on, at this time, the second clock signal CK2 is outputting a low level, and thereafter, after a high level time period, the scanning signal Gout N-1 output by the previous GOA unit of this stage is turned to a low level signal, at this time, the first thin film transistor M1 is turned off, the first node PU is maintained at a high level, the first node PU enters a maintaining stage, and the second clock signal CK2 is changed from a low level to a high level, the third thin film transistor M3 is maintained on, so that the scanning signal Gout N of this stage is output, meanwhile, in the sustain stage, since the voltage at the first node PU is at a high level, the ninth thin film transistor M9 and the seventh thin film transistor M7 are maintained to be turned on, and since the seventh thin film transistor M7 is in an on state, and the third clock signal CK3 is at a low level, the second node PD is turned on with the low level signal line 250 through the seventh thin film transistor M7, so that the voltage at the second node PD is close to the voltage on the low level signal line 250, that is, in the sustain stage of the first node PU, the voltage at the second node PD is maintained at a low level, so that the leakage current of the fifth thin film transistor M5 is small, the high level voltage at the first node PU can be maintained relatively stably, and thus the output of the present level high level scan signal Gout N is not turned off in advance, and thus the pixel charging time can be ensured. Thereafter, when the second clock signal CK2 changes to a low level and the third clock signal CK3 changes to a high level, the eighth thin film transistor M8, the sixth thin film transistor M6 and the tenth thin film transistor M10 are turned on, and the second node PD changes to a high level, so that the fifth thin film transistor M5 is turned on, and the voltage at the first node PU is forced to be pulled down to a low level and the third thin film transistor M3 is turned off. Moreover, in the present embodiment, the GOA unit only needs 10 thin film transistors and one capacitor, and needs fewer electric devices, which is suitable for circuit design with narrow frame.

In this embodiment, the high levels of the second clock signal CK2 and the third clock signal CK3 alternately cycle in sequence within one period (1 Frame), that is, when the second clock signal CK2 is at a high level, the third clock signal CK3 is at a low level, and then when the second clock signal CK2 is at a low level, the third clock signal CK3 is at a high level. However, the present invention is not limited thereto, and in other embodiments of the present invention, the clock signal further includes a first clock signal, and high levels of the first clock signal, the second clock signal, and the third clock signal are alternately cycled in sequence within one period. In addition, in other embodiments of the present invention, the clock signals further include a first clock signal and a fourth clock signal, and high levels of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are sequentially and alternately cycled in one period. In the present embodiment, in the N-1 st grade GOA cell, the first terminal of the third thin film transistor M3 receives the third clock signal CK3, and the first terminal of the sixth thin film transistor M6 receives the second clock signal CK 2. In the (N + 1) -th grade GOA cell, the first terminal of the third thin film transistor M3 receives the third clock signal CK3, and the first terminal of the sixth thin film transistor M6 receives the second clock signal CK 2. In the N +2 th grade GOA cell, the first terminal of the third thin film transistor M3 receives the second clock signal CK2, and the first terminal of the sixth thin film transistor M6 receives the third clock signal CK 3.

In this embodiment, the first end of the first to tenth thin film transistors is a source, and the second end is a drain. However, the invention is not limited thereto, and in other embodiments of the invention, the first end of the first to tenth thin film transistors may also be a drain, and the second end may be a source.

The invention also provides an array substrate which comprises the GOA circuit. In addition, the array substrate is also provided with a scanning line, a thin film transistor electrically connected with the scanning line and a pixel capacitor. In this embodiment, the number of the GOA circuits is one, and the GOA circuits are located on one side of the array substrate. However, the present invention is not limited thereto, and in other embodiments of the present invention, the number of the GOA circuits may also be multiple, for example, two, where two GOA circuits are located on two opposite sides of the array substrate.

The invention also provides a display device which comprises the array substrate.

In this embodiment, except that the voltage at the second node PD is low when the first transistor M1 is turned on and the first node PU is in the sustain phase, the voltage at the second node PD is high for the rest of the period, which may cause the device characteristics of the fifth thin film transistor M5 and the fourth thin film transistor M4 to generate a forward drift, which is not favorable for the stability of the characteristics of the fourth thin film transistor M4 and the fifth thin film transistor M5.

Second embodiment

Fig. 5 is a circuit diagram of an nth-level GOA unit according to a second embodiment of the present invention, where the circuit diagram of fig. 5 is similar to the circuit diagram of fig. 3, and therefore like reference numerals represent like components, which are not repeated herein. The main difference between this embodiment and the first embodiment is the pull-down control module.

Referring to fig. 5, in the present embodiment, the pull-down control module 330 includes a sixth-ninth thin film transistor and a third capacitor C3 in addition to the fifth thin film transistor M5, wherein the first end of the sixth thin film transistor M6, the first end of the eighth thin film transistor and the gate of the eighth thin film transistor receive the third clock signal CK3, the second end of the sixth thin film transistor M6 is electrically connected to the second node PD, the first end of the seventh thin film transistor M7 is electrically connected to the second node PD, the gate of the seventh thin film transistor M7 is electrically connected to the output terminal of the pull-up control module 210, the second end of the seventh thin film transistor M7 is electrically connected to the low-level signal line 250, the second end of the eighth thin film transistor is electrically connected to the gate of the sixth thin film transistor M6, the first end of the ninth thin film transistor M9 and an electrode of the third capacitor C3, the gate of the ninth thin film transistor M9 is electrically connected to the output terminal of the pull-up control module 210, a second terminal of the ninth thin film transistor M9 is electrically connected to the low-level signal line 250, and the other electrode of the third capacitor C3 is electrically connected to the low-level signal line 250.

Now, referring to fig. 5 and fig. 6 in combination with the GOA unit and the timing diagram, in this embodiment, when the third clock signal CK3 is at a high level, the eighth tft M6 is turned on, and the third capacitor C3 and the first capacitor C1 are charged, and when the third clock signal CK3 goes to a low level, the sixth tft M6 continues to be maintained in a conductive state, and at this time, the high level of the second node PD is released through the sixth tft M6, so that the second node PD becomes a low level, where the voltage at the second node PD varies with the high and low levels of the third clock signal CK3 for most of a period, so as to avoid that the second node PD is at a high level for most of a period, thereby preventing the device characteristics of the fifth tft M5 and the fourth tft M4 from generating a forward drift problem, the stability of the characteristics of the GOA unit is ensured.

Also, in order to prevent the characteristic of the second thin film transistor M2 from generating a forward drift, in the present embodiment, the pull-up module 320 includes a second thin film transistor M2, a third thin film transistor M3 and a second capacitor C2, the first end of the second thin film transistor M2 is electrically connected to the pull-up control module 210, the gate of the second thin film transistor M2 receives the first clock signal CK1, a second terminal of the second thin film transistor M2 is electrically connected to the first node PU, a gate of the third thin film transistor M3 is electrically connected to the first node PU, a first terminal of the third thin film transistor M3 receives the second clock signal CK2, a second terminal of the third thin film transistor M3 outputs a scan signal Gout N, one electrode of the second capacitor C2 is electrically connected to the first node PU, and the other electrode thereof is electrically connected to the second terminal of the third thin film transistor M3. Since the gate of the second thin film transistor M2 receives the first clock signal CK1 instead of a high level signal, and the change of the first clock signal CK1 with time changes between high and low levels, the problem that the device characteristics of the second thin film transistor M2 may generate a forward drift can be prevented.

In this embodiment, the pull-down control module 330 further includes a tenth tft M10, a first terminal of the tenth tft M10 is electrically connected to the output terminal of the pull-up control module 210, a gate of the tenth tft M10 receives the third clock signal CK3, and a second terminal of the tenth tft M10 receives a low-level signal. Accordingly, the high level on the line between the first thin film transistor M1 and the second thin film transistor M2 can be released by the tenth thin film transistor M10.

In the present embodiment, the high levels of the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 alternately cycle in sequence within a time period. In this embodiment, when the scan signal Gout N-1 of the previous GOA unit is at a high level, at this time, the first clock signal CK1 is also high, the second clock signal CK2 and the third clock signal CK3 are low, when the scanning signal Gout N-1 of the previous stage GOA unit is changed from high level to low level, the first clock signal CK1 also goes from high to low, the second clock signal CK2 goes from low to high, the third clock signal CK3 goes low, and, subsequently, when the second clock signal CK2 goes from high to low, the first clock signal CK1 continues to go low, the third clock signal CK3 goes from low to high, then, when the third clock signal CK3 goes from high level to low level, the first clock signal CK1 goes from low level to high level, then the second clock signal CK2 goes high and the third clock signal CK3 goes high …, alternately cycling. In addition, in other embodiments of the present invention, the clock signal is not limited to the first clock signal, the second clock signal, and the third clock signal, and may further include more clock signals, for example, a fourth clock signal, in which high levels of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are sequentially and alternately cycled in one time period. In the present embodiment, in the N-1 st grade GOA cell, the first terminal of the third thin film transistor M3 receives the first clock signal CK1, the first terminal of the sixth thin film transistor M6 receives the second clock signal CK2, and the gate of the second thin film transistor M2 receives the third clock signal CK 3. In the N +1 th grade GOA cell, the first terminal of the third thin film transistor M3 receives the third clock signal CK3, the first terminal of the sixth thin film transistor M6 receives the first clock signal CK1, and the gate of the second thin film transistor M2 receives the second clock signal CK 2.

In this embodiment, since the second clock signal CK2 goes high many times during a period, when the third thin film transistor M3 is turned off and the second clock signal CK2 goes from low to high, the first node PU may be coupled high due to coupling, so that the third thin film transistor M3 is turned on by mistake, and the GOA circuit outputs two pulled-up scan signals simultaneously, thereby causing a pixel charging error. Third embodiment

Fig. 7 is a circuit diagram of an nth-level GOA unit according to a third embodiment of the present invention, where the circuit diagram of fig. 7 is similar to the circuit diagram of fig. 5, and therefore like reference numerals represent like components and parts, which are not described herein again. The main difference between the present embodiment and the second embodiment is the pull-down control module.

Referring to fig. 7, in the present embodiment, the pull-down control module 430 includes sixth to ninth tfts in addition to the fifth tft M5. The first end of the sixth thin film transistor M6, the first end of the eighth thin film transistor M8, and the gate receive the fourth clock signal CK4, the second end of the sixth thin film transistor M6 is electrically connected to the second node PD, the first end of the seventh thin film transistor M7 is electrically connected to the second node PD, the gate of the seventh thin film transistor M7 is electrically connected to the output end of the pull-up control module 210, the second end of the seventh thin film transistor M7 is electrically connected to the low-level signal line 250, the second ends of the eighth thin film transistor M7 are electrically connected to the gate of the sixth thin film transistor M6 and the first end of the ninth thin film transistor M9, the gate of the ninth thin film transistor M9 is electrically connected to the output end of the pull-up control module 210, and the second end of the ninth thin film transistor M9 is electrically connected to the low-level signal line 250.

Now, referring to fig. 7 and 8 in conjunction with the GOA unit and the timing diagram, when the fourth clock signal CK4 is at a high level, the eighth tft M8 and the sixth tft M6 are turned on, and at this time, the second node PD is at a high level, when the fourth clock signal CK4 is turned from a high level to a low level, the sixth tft M6 and the eighth tft M8 are turned off, but at this time, the voltage at the second node PD is coupled, that is, the high level at the second node PD is coupled to a level between the low level and the high level, and there may be an intermediate level, which may turn on the fifth tft M5, when the third tft M3 is turned off, when the second clock signal CK2 is turned from a low level to a high level, if the first node PU is erroneously turned from the low level to the high level, because the fifth tft M5 is turned on, therefore, the high level is released through the fifth tft M5, so that the first node PU is maintained at the low level, and the third tft M3 is not turned on by mistake, so that the problem that the GOA circuit outputs two scan signals at the same time does not occur.

Also, in order to prevent the second node PD from being maintained at a high level or a middle level for a long time, in the present embodiment, the pull-down control module 430 includes an eleventh thin film transistor M11, a first terminal of the eleventh thin film transistor M11 is electrically connected to the second node PD, a gate thereof receives the third clock signal CK3, a high level of the third clock signal CK3 is immediately adjacent to a high level of the second clock signal CK2, and a second terminal of the eleventh thin film transistor M11 is electrically connected to the low level signal line 250. Accordingly, when the high level of the second clock signal CK2 passes, the third clock signal CK3 is immediately high, and the second node PD is pulled down to a low level.

In the present embodiment, the high levels of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 alternately cycle in sequence within one time period. In the present embodiment, when the scanning signal Gout N-1 of the previous GOA cell is at a high level, the first clock signal CK1 is also at a high level, and the duration of the high level of the first clock signal CK1 is the same as the duration of the high level of the scanning signal Gout N-1 of the previous GOA cell, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are at a low level, when the scanning signal Gout N-1 of the previous GOA cell is changed from a high level to a low level, the first clock signal CK1 is also changed from a high level to a low level, the second clock signal CK2 is changed from a low level to a high level, the third clock signal CK3, and the fourth clock signal CK4 are at a low level, and then, when the second clock signal CK2 is changed from a high level to a low level, the first clock signal CK1, the fourth clock signal CK4 continue to be at a low level, and the third clock signal CK3 is changed from a low level, then, when the third clock signal CK3 changes from high to low, the fourth clock signal CK4 changes from low to high, the first clock signal CK1 and the second clock signal CK2 are low, and then the fourth clock signal CK4 changes from high to low, the first clock signal CK1 changes from low to high, the second clock signal CK2 changes to high, the third clock signal CK3 changes to high, and the fourth clock signal CK4 changes to high …, thereby alternately cycling. In addition, in other embodiments of the present invention, the clock signals are not limited to the first clock signal, the second clock signal, and the third clock signal, and may include more clock signals. In the present embodiment, in the N-1 st grade GOA cell, the first terminal of the third thin film transistor M3 receives the first clock signal CK1, the first terminal of the sixth thin film transistor M6 receives the third clock signal CK3, the gate of the second thin film transistor M2 receives the fourth clock signal CK4, and the gate of the eleventh thin film transistor M11 receives the second clock signal CK 2. In the N +1 th grade GOA cell, the first terminal of the third thin film transistor M3 receives the third clock signal CK3, the first terminal of the sixth thin film transistor M6 receives the first clock signal CK1, the gate of the second thin film transistor M2 receives the second clock signal CK2, and the gate of the eleventh thin film transistor M11 receives the fourth clock signal CK 4. In the N +2 th grade GOA cell, the first terminal of the third thin film transistor M3 receives the fourth clock signal CK4, the first terminal of the sixth thin film transistor M6 receives the second clock signal CK2, the gate of the second thin film transistor M2 receives the third clock signal CK3, and the gate of the eleventh thin film transistor M11 receives the first clock signal CK 1.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.

The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and it is therefore to be understood that the invention is not limited by the scope of the appended claims.

Claims

A GOA circuit, comprising a cascaded plurality of levels of GOA cells, the GOA cells comprising:

the pull-up control module is used for generating a scanning control signal of the current level according to the control of the scanning signal output by the GOA unit of the previous level;

the pull-up module is used for pulling up the scanning signal of the current stage according to the scanning control signal of the current stage and a clock signal, and comprises a first node, wherein a voltage signal at the first node is used for controlling the output of the scanning signal, and a maintaining stage for maintaining a high level exists in the first node in one period of the GOA circuit;

the pull-down control module is used for outputting a pull-down control signal according to the clock signal and pulling down the level signal of the first node according to the pull-down control signal;

the pull-down module is used for pulling down the scanning signal of the current stage according to the pull-down control signal;

the low-level signal line is used for outputting a low-level signal and is respectively and electrically connected with the pull-down control module and the pull-down module;

the pull-down control module comprises a fifth thin film transistor, wherein a second end of the fifth thin film transistor is electrically connected with the low-level signal line, a first end of the fifth thin film transistor is electrically connected with the first node, a grid electrode of the fifth thin film transistor is electrically connected with the second node, the second node is used for receiving a pull-down control signal, and when the first node is in a maintaining stage, the voltage at the second node is pulled down to be at a low level by the low-level signal line.
The GOA circuit of claim 1, wherein the clock signals comprise a second clock signal, a third clock signal, wherein a high time period of the third clock signal is immediately adjacent and two high time periods of the second clock signal, the pull-up module receives the second clock signal, and the pull-down control module receives the third clock signal.
The GOA circuit of claim 2, wherein at least high periods of the second and third clock signals are alternately cycled in sequence during a time period.
The GOA circuit of claim 2, wherein the pull-down control module further comprises sixth-tenth TFTs, wherein a first terminal of the sixth TFT, a first terminal of the eighth TFT, and a gate of the eighth TFT receive the third clock signal, a second terminal of the sixth TFT is electrically connected to the second node, a gate of the sixth TFT is electrically connected to the second terminal of the eighth TFT, a first terminal of the seventh TFT is electrically connected to the second node, a gate of the seventh TFT is electrically connected to the output terminal of the pull-up control module, i.e., the first node via the second TFT, a second terminal of the seventh TFT is electrically connected to the low-level signal line, and a second terminal of the eighth TFT is electrically connected to a gate of the tenth TFT, the first end of the tenth thin film transistor is electrically connected with the gate of the eighth thin film transistor, the gate and the second end of the tenth thin film transistor are electrically connected with the first end of the ninth thin film transistor, the gate of the ninth thin film transistor is electrically connected with the output end of the pull-up control module, and the second end of the ninth thin film transistor is electrically connected with the low-level signal line.
The GOA circuit of claim 4, wherein the pull-up module comprises a second thin film transistor and a third thin film transistor, wherein a first terminal of the second thin film transistor is electrically connected to the pull-up control module, a gate of the second thin film transistor receives a high level, a second terminal of the second thin film transistor is electrically connected to the first node, a gate of the third thin film transistor is electrically connected to the first node, a first terminal of the third thin film transistor receives the second clock signal, and a second terminal of the third thin film transistor is configured to output the scan signal.
The GOA circuit of claim 1, wherein the clock signals comprise a first clock signal, a second clock signal, and a third clock signal, wherein a high time period of the second clock signal is immediately adjacent to a high time period of the first clock signal and two high time periods are adjacent, a high time period of the third clock signal is immediately adjacent to a high time period of the second clock signal and two high time periods are adjacent, the pull-up module receives the first clock signal, the second clock signal, and the pull-down control module receives the third clock signal.
The GOA circuit of claim 6, wherein the high level time periods of at least the first, second and third clock signals are alternately cycled in sequence during a time period.
The GOA circuit of claim 6, wherein the pull-down control module further comprises sixth-ninth TFTs and a third capacitor, wherein the first terminal of the sixth TFT, the first terminal of the eighth TFT and the gate thereof receive a third clock signal, the second terminal of the sixth TFT is electrically connected to the second node, the first terminal of the seventh TFT is electrically connected to the second node, the gate thereof is electrically connected to the output terminal of the pull-up control module, the second terminal of the seventh TFT is electrically connected to a low-level signal line, the second terminal of the eighth TFT is electrically connected to the gate thereof, the first terminal of the ninth TFT and an electrode of the third capacitor, respectively, the gate thereof is electrically connected to the output terminal of the pull-up control module, and the second terminal of the ninth TFT is electrically connected to the low-level signal line, the other electrode of the third capacitor is electrically connected with a low-level signal line.
The GOA circuit of claim 1, wherein the clock signals comprise a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, wherein a high time period of the second clock signal is immediately adjacent to a high time period of the first clock signal and two high time periods are adjacent, a high time period of the third clock signal is immediately adjacent to a high time period of the second clock signal and two high time periods are adjacent, a high time period of the fourth clock signal is immediately adjacent to a high time period of the third clock signal and two high time periods are adjacent, the pull-up module receives the first clock signal and the second clock signal, and the pull-down control module receives the third clock signal and the fourth clock signal.
The GOA circuit of claim 9, wherein high levels of at least the first, second, third, and fourth clock signals are alternately cycled in sequence during a time period.
The GOA circuit of claim 9, wherein the pull-down control module further comprises sixth-ninth thin film transistors, wherein the first end of the sixth thin film transistor, the first end of the eighth thin film transistor and the gate receive a fourth clock signal, the second end of the sixth thin film transistor is electrically connected with the second node, the first end of the seventh thin film transistor is electrically connected with the second node, the gate of the seventh thin film transistor is electrically connected with the output end of the pull-up control module, the second end of the seventh thin film transistor is electrically connected with a low-level signal line, the second end of the eighth thin film transistor is respectively and electrically connected with the grid electrode of the sixth thin film transistor and the first end of the ninth thin film transistor, and the grid electrode of the ninth thin film transistor is electrically connected with the output end of the pull-up control module, and the second end of the ninth thin film transistor is electrically connected with the low-level signal wire.
The GOA circuit of claim 11, wherein the pull-down control module further comprises an eleventh thin film transistor having a first terminal electrically connected to the second node, a gate receiving the third clock signal, and a second terminal electrically connected to a low signal line.
The GOA circuit of any one of claims 8, 11 and 12, wherein the pull-up module comprises a second thin film transistor, a third thin film transistor and a second capacitor, a first terminal of the second thin film transistor is electrically connected to the pull-up control module, a gate of the second thin film transistor receives the first clock signal, a second terminal of the second thin film transistor is electrically connected to the first node, a gate of the third thin film transistor is electrically connected to the first node, a first terminal of the third thin film transistor receives the second clock signal, a second terminal of the third thin film transistor is configured to output the scan signal, one electrode of the second capacitor is electrically connected to the first node, and another electrode of the second capacitor is electrically connected to the second terminal of the third thin film transistor.
The GOA circuit of claim 13, wherein the pull-down control module further comprises a tenth tft, a first terminal of the tenth tft being electrically connected to the output terminal of the pull-up control module, a gate of the tenth tft receiving the third clock signal, and a second terminal of the tenth tft receiving a low signal.
The GOA circuit of any one of claims 1-12, wherein the pull-up control module comprises a first thin film transistor, a first end of the first thin film transistor receives a high signal, a gate of the first thin film transistor receives a previous scan signal, and a second end of the first thin film transistor is electrically connected to the pull-up module and the pull-down control module, respectively.
The GOA circuit of any one of claims 1-12, wherein the pull-down module comprises a fourth tft and a first capacitor, the fourth tft having a first terminal electrically connected to the pull-up module, a gate electrically connected to the second node, a second terminal electrically connected to a low-level signal line, one electrode electrically connected to the second node, and another electrode electrically connected to the low-level signal line.
An array substrate comprising the GOA circuit of any one of claims 1-16.
A display device comprising the array substrate according to claim 17.