CN105976781A - Goa circuit - Google Patents
Goa circuit Download PDFInfo
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- CN105976781A CN105976781A CN201610556476.2A CN201610556476A CN105976781A CN 105976781 A CN105976781 A CN 105976781A CN 201610556476 A CN201610556476 A CN 201610556476A CN 105976781 A CN105976781 A CN 105976781A
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- film transistor
- thin film
- tft
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
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- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention provides a GOA circuit. According to the GOA circuit, a third thin film transistor is additionally arranged between a second node and a forward and reverse scanning control module, a grid of the third thin film transistor is under the control of the forward and reverse scanning control module, a source electrode is connected with constant-voltage high potential, and a drain electrode is electrically connected with the second node through a normally-open fourth thin film transistor, such that potential of the second node can be prevented from drop in a touch control scanning period and the stability of the GOA circuit is improved. Besides, a source electrode of a seventh thin film transistor is connected with (M+2)-th clock signals and a grid is electrically connected with a drain electrode of a sixth thin film transistor, such that the repeatedly starting frequency of the seventh thin film transistor is reduced and threshold voltages of the seventh thin film transistor is prevented from deviation.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of GOA circuit.
Background technology
Liquid crystal display (Liquid Crystal Display, LCD) has that fuselage is thin, power saving, radiationless
Have that fuselage is thin Deng liquid crystal display (Liquid Crystal Display, LCD), power saving, radiationless etc.
Many merits, is widely used.As: LCD TV, mobile phone, personal digital assistant (PDA),
Digital camera, computer screen or notebook computer screen etc., occupy an leading position in flat display field.
GOA (Gate Driver on Array) technology i.e. array base palte row cutting technology, is to utilize thin film brilliant
Body pipe (Thin Film Transistor, TFT) LCD (Liquid Crystal Display) array processing procedure is by gated sweep drive circuit
It is produced on thin-film transistor array base-plate, to realize the type of drive of progressive scan, there is reduction and produce
Cost and the advantage realizing the narrow frame design of panel, used by multiple display.GOA circuit has two
Item basic function: first is that output gated sweep drives signal, drives the gate line in panel, opens aobvious
Show the TFT in district, so that pixel to be charged；Second is shift LD function, when a gated sweep
After driving signal to export, carry out next gated sweep by clock control and drive the output of signal,
And hand on successively.GOA technology can reduce welding (bonding) operation of external IC, has an opportunity
Promote production capacity and reduce product cost, and display panels can be made to be more suitable for making the aobvious of narrow frame
Show product.
Embedded type touch control technology is contact panel and liquid crystal panel to be combined as a whole, and by contact panel merit
Can be embedded in liquid crystal panel so that liquid crystal panel is provided simultaneously with display and the function of perception touch-control input.
Along with developing rapidly of Display Technique, touch-control display panel is accepted by people the most widely and uses,
Touch-control display panel is all employed such as smart mobile phone, panel computer etc..
Existing embedded type touch control technology is broadly divided into two kinds: one is that touch-control circuit is at liquid crystal cell mo(u)ld top half
(On Cell), another kind is that touch-control circuit is at liquid crystal cell inner mold (In Cell).Wherein, In cell type touch-control
Display floater is to utilize existing thin-film transistor liquid crystal display array (Array) processing procedure by touch-control scanner section
The induction electrode (Pad) divided is produced on array base palte and realizes touch controllable function.In cell type touch-control shows
Show that panel needs are when GOA normal circuit operation, it is possible to close all levels in GOA circuit at any one time
The outfan of GOA unit, stops gated sweep and drives signal output, and to carry out touch-control scanning, touch-control is swept
After retouching end, GOA circuit recovers normal again, continues to put out gated sweep and drives signal, scans at touch-control
While drive output output node need to maintain duty current potential.
Summary of the invention
It is an object of the invention to provide a kind of GOA circuit, it is possible to when touch-control scans, maintain second section
The high potential of point, prevents the current potential of the secondary nodal point when touch-control scans from gliding, and promotes stablizing of GOA circuit
Property.
For achieving the above object, the invention provides a kind of GOA circuit, including: the multistage GOA of cascade
Unit, every one-level GOA unit all includes: forward and reverse scan control module, output module, node control
Module and output reset module；
If M and N is positive integer, except first order GOA unit, second level GOA unit, penultimate stage
Outside GOA unit and afterbody GOA unit, in N level GOA unit:
Described forward and reverse scan control module includes: the first film transistor and the second thin film transistor (TFT)；
The grid of described the first film transistor is electrically connected at the outfan of two-stage N-2 level GOA unit, source
Forward scan control signal is accessed in pole, and drain electrode is electrically connected at primary nodal point；Described second thin film transistor (TFT)
Grid is electrically connected at the outfan of lower two-stage N+2 level GOA unit, and source electrode accesses reverse scan and controls letter
Number, drain electrode is electrically connected at primary nodal point；
Described output module includes: the 12nd thin film transistor (TFT)；The grid electricity of described 12nd thin film transistor (TFT)
Property be connected to secondary nodal point, source electrode accesses the M article clock signal, and drain electrode is electrically connected at outfan；
Described node control module includes: the 3rd thin film transistor (TFT), the 4th thin film transistor (TFT), the 5th thin film are brilliant
Body pipe, the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th thin film transistor (TFT), the 9th thin film transistor (TFT),
Tenth thin film transistor (TFT), the 11st thin film transistor (TFT), the first electric capacity, the second electric capacity and the 3rd electric capacity；
The grid of described 3rd thin film transistor (TFT) is electrically connected at primary nodal point, and source electrode accesses constant voltage high potential, drain electrode
It is electrically connected at the 3rd node；The grid of described 4th thin film transistor (TFT) accesses constant voltage high potential, and source electrode is electrical
Being connected to the 3rd node, drain electrode is electrically connected at secondary nodal point；The grid of described 5th thin film transistor (TFT) and source
The most all accessing the M article clock signal, drain electrode is electrically connected at fourth node；Described 6th thin film transistor (TFT)
Grid is electrically connected at fourth node, and source electrode accesses the M+2 article clock signal, and drain electrode is electrically connected at the 7th
The grid of thin film transistor (TFT)；The source electrode of described 7th thin film transistor (TFT) accesses the M+2 article clock signal, drain electrode
It is electrically connected at the 5th node；The grid of described 8th thin film transistor (TFT) is electrically connected at primary nodal point, source electrode
Being electrically connected at fourth node, drain electrode accesses constant voltage electronegative potential；The grid of described 9th thin film transistor (TFT) is electrical
Being connected to primary nodal point, source electrode is electrically connected at the 5th node, and drain electrode accesses constant voltage electronegative potential；Described tenth
The grid of thin film transistor (TFT) is electrically connected at the 5th node, and source electrode is electrically connected at secondary nodal point, and drain electrode accesses
Constant voltage electronegative potential；The grid of described 11st thin film transistor (TFT) is electrically connected at the 5th node, and source electrode electrically connects
Being connected to outfan, drain electrode accesses constant voltage electronegative potential；One end of described first electric capacity is electrically connected at the 3rd node,
The other end accesses constant voltage electronegative potential；One end of described second electric capacity is electrically connected at the 5th node, another termination
Enter constant voltage electronegative potential；One end of described 3rd electric capacity is electrically connected at fourth node, and it is low that the other end accesses constant voltage
Current potential；
Described output resets module and includes: the 13rd thin film transistor (TFT)；The grid of described 13rd thin film transistor (TFT)
Overall situation control signal is accessed in pole, and source electrode is electrically connected at outfan, and drain electrode is electrically connected at constant voltage electronegative potential.
In first order GOA unit and second level GOA unit, the grid of described the first film transistor is equal
Access circuit initial signal.
In afterbody GOA unit and penultimate stage GOA unit, described second thin film transistor (TFT)
Grid all accesses circuit initial signal.
Each thin film transistor (TFT) is N-type TFT.
When panel normally shows, described overall situation control signal is electronegative potential；When panel carries out touch-control scanning,
Described overall situation control signal is high potential.
During described GOA circuit forward scan, described forward scan control signal is high potential, reverse scan
Control signal is electronegative potential；
During described GOA circuit reverse scan, described forward scan control signal is electronegative potential, reverse scan
Control signal is high potential.
Including four clock signals: first, second, third and Article 4 clock signal；As described M
When bar clock signal is Article 3 clock signal, the M+2 article clock signal is Article 1 clock signal；Work as institute
Stating the M article clock signal when being Article 4 clock signal, the M+2 article clock signal is Article 2 clock letter
Number.
Described first, second, third and pulse period of Article 4 clock signal identical, previous bar clock
The trailing edge of signal produces with the rising edge of a rear clock signal simultaneously.
Beneficial effects of the present invention: the invention provides a kind of GOA circuit, described GOA circuit passes through
The 3rd thin film transistor (TFT), described 3rd film crystal is set up between secondary nodal point and forward and reverse scan control module
Tube grid is controlled by forward and reverse scan control module, and source electrode accesses constant voltage high potential, drains via normally opened the
Four thin film transistor (TFT)s are electrically connected with secondary nodal point, it is possible to prevent the current potential of secondary nodal point during touch-control scans
Glide, promote the stability of GOA circuit, access M+2 also by by the source electrode of the 7th thin film transistor (TFT)
Bar clock signal, grid is electrically connected at the drain electrode of the 6th thin film transistor (TFT), to reduce by the 7th thin film transistor (TFT)
The number of times repeatedly opened, prevents the threshold voltage shift of the 7th thin film transistor (TFT).
Accompanying drawing explanation
In order to be able to be further understood that inventive feature and technology contents, refer to below in connection with the present invention
Detailed description and accompanying drawing, but accompanying drawing only provide with reference to and explanation use, not be used for the present invention is limited
System.
In accompanying drawing,
Fig. 1 is the circuit diagram of the GOA circuit of the present invention；
Fig. 2 is the sequential chart during GOA circuit forward scan of the present invention；
Fig. 3 is the circuit diagram of the first order GOA unit of the GOA circuit of the present invention；
Fig. 4 is the circuit diagram of the second level GOA unit of the GOA circuit of the present invention；
Fig. 5 is the circuit diagram of the penultimate stage GOA unit of the GOA circuit of the present invention；
Fig. 6 is the circuit diagram of the afterbody GOA unit of the GOA circuit of the present invention.
Detailed description of the invention
By further illustrating the technological means and effect thereof that the present invention taked, below in conjunction with the present invention's
Preferred embodiment and accompanying drawing thereof are described in detail.
Referring to Fig. 1, the present invention provides a kind of GOA circuit, including: the multistage GOA unit of cascade, often
One-level GOA unit all includes: forward and reverse scan control module 100, output module 200, node control mould
Block 300 and output reset module 400；
If M and N is positive integer, except first order GOA unit, second level GOA unit, penultimate stage
Outside GOA unit and afterbody GOA unit, in N level GOA unit:
Described forward and reverse scan control module 100 includes: the first film transistor T1 and the second thin film are brilliant
Body pipe T2；The grid of described the first film transistor T1 is electrically connected at two-stage N-2 level GOA unit
Outfan G (N-2), source electrode accesses forward scan control signal U2D, and drain electrode is electrically connected at primary nodal point
H(N)；The grid of described second thin film transistor (TFT) T2 is electrically connected at lower two-stage N+2 level GOA unit
Outfan G (N+2), source electrode accesses reverse scan control signal D2U, and drain electrode is electrically connected at primary nodal point
H(N)；
Described output module 200 includes: the 12nd thin film transistor (TFT) T12；Described 12nd thin film transistor (TFT)
The grid of T12 is electrically connected at secondary nodal point Q (N), and source electrode accesses the M article clock signal CK (M), drain electrode
It is electrically connected at outfan G (N)；
Described node control module 300 includes: the 3rd thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4,
Five thin film transistor (TFT) T5, the 6th thin film transistor (TFT) T6, the 7th thin film transistor (TFT) T7, the 8th thin film transistor (TFT)
T8, the 9th thin film transistor (TFT) T9, the tenth thin film transistor (TFT) T10, the 11st thin film transistor (TFT) T11, first
Electric capacity C1, the second electric capacity C2 and the 3rd electric capacity C3；The grid of described 3rd thin film transistor (TFT) T3 is electrical
Being connected to primary nodal point H (N), source electrode accesses constant voltage high potential VGH, and drain electrode is electrically connected at the 3rd node
K(N)；The grid of described 4th thin film transistor (TFT) T4 accesses constant voltage high potential VGH, and source electrode is electrically connected at
3rd node K (N), drain electrode is electrically connected at secondary nodal point Q (N)；The grid of described 5th thin film transistor (TFT) T5
Pole and source electrode all access the M article clock signal CK (M), and drain electrode is electrically connected at fourth node W (N)；Institute
The grid stating the 6th thin film transistor (TFT) (T6) is electrically connected at fourth node W (N), and source electrode accesses M+2
Bar clock signal CK (M+2), drain electrode is electrically connected at the grid of the 7th thin film transistor (TFT) T7；Described 7th
The source electrode of thin film transistor (TFT) T7 accesses the M+2 article clock signal CK (M+2), and drain electrode is electrically connected at Section five
Point P (N)；The grid of described 8th thin film transistor (TFT) T8 is electrically connected at primary nodal point H (N), and source electrode is electrical
Being connected to fourth node W (N), drain electrode accesses constant voltage electronegative potential VGL；Described 9th thin film transistor (TFT) T9's
Grid is electrically connected at primary nodal point H (N), and source electrode is electrically connected at the 5th node P (N), and drain electrode accesses constant voltage
Electronegative potential VGL；The grid of described tenth thin film transistor (TFT) T10 is electrically connected at the 5th node P (N), source electrode
Being electrically connected at secondary nodal point Q (N), drain electrode accesses constant voltage electronegative potential VGL；Described 11st film crystal
The grid of pipe T11 is electrically connected at the 5th node P (N), and source electrode is electrically connected at outfan G (N), and drain electrode connects
Enter constant voltage electronegative potential VGL；One end of described first electric capacity C1 is electrically connected at the 3rd node K (N), another
Terminate into constant voltage electronegative potential VGL；One end of described second electric capacity C2 is electrically connected at the 5th node P (N),
The other end accesses constant voltage electronegative potential VGL；One end of described 3rd electric capacity C3 is electrically connected at fourth node
W (N), the other end accesses constant voltage electronegative potential VGL；
Described output resets module 400 and includes: the 13rd thin film transistor (TFT) T13；Described 13rd film crystal
The grid of pipe T13 accesses overall situation control signal GAS, and source electrode is electrically connected at outfan G (N), and drain electrode is electrically
It is connected to constant voltage electronegative potential VGL.
Specifically, refer to Fig. 3 to Fig. 6, in first order GOA unit and second level GOA unit, institute
The grid stating the first film transistor T1 all accesses circuit initial signal STV, in afterbody GOA unit
With in penultimate stage GOA unit, the grid of described second thin film transistor (TFT) T2 all accesses the initial letter of circuit
Number STV.
Further, referring to Fig. 1, each thin film transistor (TFT) is N-type TFT, wherein,
When panel normally shows, described overall situation control signal Gas is electronegative potential；When panel carries out touch-control scanning,
Described overall situation control signal Gas is high potential.During described GOA circuit forward scan, described forward scan control
Signal U2D processed is high potential, and reverse scan control signal D2U is electronegative potential；During reverse scan, described just
Being electronegative potential to scan control signal U2D, reverse scan control signal D2U is high potential.
It should be noted that refer to Fig. 2, described GOA circuit includes four clock signals altogether: the first,
Second, third and Article 4 clock signal CK (1), CK (2), CK (3), CK (4)；As described M
When bar clock signal CK (M) is Article 3 clock signal CK (3), the M+2 article clock signal CK (M+1) is
Article 1, clock signal CK (1)；When described the M article clock signal CK (M) is Article 4 clock signal CK (4)
Time, the M+2 article clock signal CK (M+2) is Article 2 clock signal CK (2).Described first, second,
3rd and Article 4 clock signal CK (1), CK (2), CK (3), CK (4) pulse period identical, press
According to first, second, third and Article 4 clock signal CK (1), CK (2), CK (3), the row of CK (4)
Row order, the trailing edge of previous bar clock signal produces with the rising edge of a rear clock signal simultaneously, i.e. institute
First pulse signal stating Article 1 clock signal CK (1) first produces, described first clock signal CK (1)
First pulse signal ends while first pulse signal of described Article 2 clock signal CK (2) produce
Raw, described Article 3 clock while first pulse signal ends of described Article 2 clock signal CK (2)
First pulse signal of signal CK (3) produces, first pulse letter of described Article 3 clock signal CK (3)
While number terminating, first pulse signal of described Article 4 clock signal CK (4) produces, described Article 4
While first pulse signal ends of clock signal CK (4) the of described Article 1 clock signal CK (1)
Two pulse signals produce.
Further, the GOA circuit of the present invention uses interleaved mode to be scanned, the first order
The outfan of GOA unit is electrically connected with third level GOA unit, and the outfan of second level GOA unit is electrical
Connecting fourth stage GOA unit, the outfan of third level GOA unit is electrically connected with level V GOA unit,
The outfan of fourth stage GOA unit is electrically connected with the 6th grade of GOA unit, the like.
Please refer to Fig. 1 and Fig. 2, carry out forward with the first embodiment of the GOA circuit of the present invention below
As a example by scanning, the specific works process of the GOA circuit of the present invention is described:
First, the outfan of N-2 level GOA unit provides high potential (at the first order, second level GOA
Unit is circuit initial signal STV and provides high potential), the first film transistor T1 opens, high potential
Primary nodal point H (N) is charged to high potential through the first film transistor T1 by forward scan control signal U2D,
3rd thin film transistor (TFT) T3 opens, and the 4th thin film transistor (TFT) T4 is beaten all the time by the control of constant voltage high potential VGH
Opening, the 3rd node K (N) and secondary nodal point Q (N) is charged to high potential by constant voltage high potential VGH, and the 12nd
Thin film transistor (TFT) T12 opens；Meanwhile, the 8th thin film transistor (TFT) T8 opens, fourth node W (N) quilt
Being pulled low to constant voltage electronegative potential VGL, the 9th thin film transistor (TFT) T9 opens, and the 5th node P (N) is pulled low to perseverance
Force down current potential VGL, the the 6th, the tenth and controlled by the 4th and the 5th node W (N), P (N)
11 thin film transistor (TFT) T6, T10, T11 are turned off；The M article clock signal CK (M) is electronegative potential, the
Five thin film transistor (TFT) T5 close, and outfan G (N) is electronegative potential；
Subsequently, the outfan of N-2 level GOA unit becomes electronegative potential, the M article clock signal CK (M)
Becoming high potential, the 3rd node K (N) and secondary nodal point Q (N) is kept height by the memory action of the first electric capacity C1
Current potential, the 12nd thin film transistor (TFT) T12 controlled by secondary nodal point Q (N) opens, the M article clock signal
The high potential of CK (M) through the 12nd thin film transistor (TFT) T12 outfan G (N) charged to high potential as
Gated sweep drives signal output；Meanwhile, the 5th film crystal that the M article clock signal CK (M) controls
Pipe T5 opens, and fourth node W (N) is charged to high potential, and the 6th thin film transistor (TFT) T6 opens, M+2
Bar clock signal CK (M+2) is electronegative potential, and the 5th node P (N) keeps electronegative potential, the tenth and the 11st
Thin film transistor (TFT) T10, T11 remain turned-off；
Then, the M+2 article clock signal CK (M+2) becomes high potential, and fourth node W (N) is by the 3rd electricity
The memory action holding C3 continues to high potential, and the 7th thin film transistor (TFT) T7 opens, the 5th node P (N) quilt
Charge to high potential, the tenth and the 11st thin film transistor (TFT) T10, T11 open, drag down second section respectively
Point Q (N) and outfan G (N) to constant voltage electronegative potential VGL；
Finally, the M+2 article clock signal CK (M+2) becomes electronegative potential, and the 5th node P (N) is by the second electricity
The memory action holding C2 still keeps high potential, the tenth and the 11st thin film transistor (TFT) T10, T11 continue to beat
Opening, secondary nodal point Q (N) and outfan G (N) keeps electronegative potential.
The work process of reverse scan is similar with forward scan, it is only necessary to by described reverse scan control signal
D2U is set to high potential, and forward scan control signal U2D is set to electronegative potential, and the direction of scanning is by
One-level becomes afterbody to afterbody scanning and scans to the first order, and here is omitted.
In above-mentioned scanning process, when being made without touch-control scanning, the 13rd in GOA unit at different levels
Thin film transistor (TFT) T13 is closed all the time by the control of the overall signal Gas of electronegative potential, GOA unit at different levels according to
Above-mentioned work process shows scanning successively.And when needs carry out touch-control scanning, described overall situation control signal
Gas becomes high potential, and the 13rd thin film transistor (TFT) T13 in GOA unit at different levels opens, and GOA at different levels are mono-
Outfan G (N) in unit all exports constant voltage electronegative potential VGL, and scans before touch-control scanning starts
The current potential of the secondary nodal point Q (N) of one-level GOA unit is maintained high potential by the memory action of the first electric capacity C1,
And will not be glided by the protection of the 3rd thin film transistor (TFT) T3, in order to can continue to after the touch-control end of scan
Show scanning normally.
Additionally, in the present invention, the grid of the 7th thin film transistor (TFT) T7 is electrically connected at the 6th film crystal
The drain electrode of pipe T6, only when the 6th thin film transistor (TFT) T6 opens, the M+2 article clock signal CK (M+2)
The grid of the 7th thin film transistor (TFT) T7 could be accessed, say, that compared to directly by the M+2 bar clock
Signal CK (M+2) accesses the grid of the 7th thin film transistor (TFT) T7 can reduce by the 7th thin film transistor (TFT) T7 repeatedly
The number of times opened, prevents the 7th thin film transistor (TFT) T7 from repeatedly opening and causes threshold voltage shift (Vth shift),
Promote the stability of GOA circuit.
In sum, the invention provides a kind of GOA circuit, described GOA circuit is by secondary nodal point
And set up the 3rd thin film transistor (TFT), described 3rd thin-film transistor gate between forward and reverse scan control module
Being controlled by forward and reverse scan control module, source electrode accesses constant voltage high potential, drains via normally opened 4th thin
Film transistor and secondary nodal point are electrically connected with, it is possible to prevent during touch-control scans under the current potential of secondary nodal point
Sliding, promote the stability of GOA circuit, access the M+2 article also by by the source electrode of the 7th thin film transistor (TFT)
Clock signal, grid is electrically connected at the drain electrode of the 6th thin film transistor (TFT), to reduce by the 7th thin film transistor (TFT)
The number of times repeatedly opened, prevents the threshold voltage shift of the 7th thin film transistor (TFT).
The above, for the person of ordinary skill of the art, can be according to the technical side of the present invention
Other various corresponding changes and deformation are made in case and technology design, and all these change and deformation are all answered
Belong to the protection domain of the claims in the present invention.
Claims (8)
1. a GOA circuit, it is characterised in that including: the multistage GOA unit of cascade, every one-level GOA
Unit all includes: forward and reverse scan control module (100), output module (200), node control module (300),
And output resets module (400)；
If M and N is positive integer, except first order GOA unit, second level GOA unit, penultimate stage
Outside GOA unit and afterbody GOA unit, in N level GOA unit:
Described forward and reverse scan control module (100) including: the first film transistor (T1) and second
Thin film transistor (TFT) (T2)；The grid of described the first film transistor (T1) is electrically connected at two-stage N-2
The outfan (G (N-2)) of level GOA unit, source electrode accesses forward scan control signal (U2D), drain electrode electricity
Property is connected to primary nodal point (H (N))；The grid of described second thin film transistor (TFT) (T2) is electrically connected at down
The outfan (G (N+2)) of two-stage N+2 level GOA unit, source electrode accesses reverse scan control signal
(D2U), drain electrode is electrically connected at primary nodal point (H (N))；
Described output module (200) including: the 12nd thin film transistor (TFT) (T12)；Described 12nd thin film
The grid of transistor (T12) is electrically connected at secondary nodal point (Q (N)), and source electrode accesses the M article clock signal
(CK (M)), drain electrode is electrically connected at outfan (G (N))；
Described node control module (300) including: the 3rd thin film transistor (TFT) (T3), the 4th thin film transistor (TFT)
(T4), the 5th thin film transistor (TFT) (T5), the 6th thin film transistor (TFT) (T6), the 7th thin film transistor (TFT) (T7),
8th thin film transistor (TFT) (T8), the 9th thin film transistor (TFT) (T9), the tenth thin film transistor (TFT) (T10),
11 thin film transistor (TFT)s (T11), the first electric capacity (C1), the second electric capacity (C2) and the 3rd electric capacity (C3)；
The grid of described 3rd thin film transistor (TFT) (T3) is electrically connected at primary nodal point (H (N)), and source electrode accesses perseverance
Pressure high potential (VGH), drain electrode is electrically connected at the 3rd node (K (N))；Described 4th thin film transistor (TFT)
(T4) grid accesses constant voltage high potential (VGH), and source electrode is electrically connected at the 3rd node (K (N)),
Drain electrode is electrically connected at secondary nodal point (Q (N))；The grid of described 5th thin film transistor (TFT) (T5) and source electrode
All accessing the M article clock signal (CK (M)), drain electrode is electrically connected at fourth node (W (N))；Described
The grid of the 6th thin film transistor (TFT) (T6) is electrically connected at fourth node (W (N)), and source electrode accesses M+2
Bar clock signal (CK (M+2)), drain electrode is electrically connected at the grid of the 7th thin film transistor (TFT) (T7)；Institute
The source electrode stating the 7th thin film transistor (TFT) (T7) accesses the M+2 article clock signal (CK (M+2)), drain electrode electricity
Property is connected to the 5th node (P (N))；The grid of described 8th thin film transistor (TFT) (T8) is electrically connected at
One node (H (N)), source electrode is electrically connected at fourth node (W (N)), and drain electrode accesses constant voltage electronegative potential
(VGL)；The grid of described 9th thin film transistor (TFT) (T9) is electrically connected at primary nodal point (H (N)),
Source electrode is electrically connected at the 5th node (P (N)), and drain electrode accesses constant voltage electronegative potential (VGL)；Described tenth thin
The grid of film transistor (T10) is electrically connected at the 5th node (P (N)), and source electrode is electrically connected at second section
Point (Q (N)), drain electrode accesses constant voltage electronegative potential (VGL)；Described 11st thin film transistor (TFT) (T11)
Grid is electrically connected at the 5th node (P (N)), and source electrode is electrically connected at outfan (G (N)), and drain electrode accesses
Constant voltage electronegative potential (VGL)；One end of described first electric capacity (C1) is electrically connected at the 3rd node (K (N)),
The other end accesses constant voltage electronegative potential (VGL)；One end of described second electric capacity (C2) is electrically connected at the 5th
Node (P (N)), the other end accesses constant voltage electronegative potential (VGL)；One end of described 3rd electric capacity (C3)
Being electrically connected at fourth node (W (N)), the other end accesses constant voltage electronegative potential (VGL)；
Described output resets module (400) and including: the 13rd thin film transistor (TFT) (T13)；Described 13rd
The grid of thin film transistor (TFT) (T13) accesses overall situation control signal (GAS), and source electrode is electrically connected at outfan
(G (N)), drain electrode is electrically connected at constant voltage electronegative potential (VGL).
2. GOA circuit as claimed in claim 1, it is characterised in that in first order GOA unit and the
In two grades of GOA unit, the grid of described the first film transistor (T1) all accesses circuit initial signal
(STV)。
3. GOA circuit as claimed in claim 1, it is characterised in that in afterbody GOA unit and
In penultimate stage GOA unit, the grid of described second thin film transistor (TFT) (T2) all accesses circuit and initiates
Signal (STV).
4. GOA circuit as claimed in claim 1, it is characterised in that each thin film transistor (TFT) is N-type
Thin film transistor (TFT).
5. GOA circuit as claimed in claim 4, it is characterised in that when panel normally shows,
Described overall situation control signal (Gas) is electronegative potential；When panel carries out touch-control scanning, the described overall situation controls letter
Number (Gas) is high potential.
6. GOA circuit as claimed in claim 4, it is characterised in that described GOA circuit forward scan
Time, described forward scan control signal (U2D) is high potential, and reverse scan control signal (D2U) is
Electronegative potential；
During described GOA circuit reverse scan, described forward scan control signal (U2D) is electronegative potential, instead
It is high potential to scan control signal (D2U).
7. GOA circuit as claimed in claim 1, it is characterised in that include four articles of clock signals: the
One, second, third and Article 4 clock signal (CK (1), CK (2), CK (3), CK (4))；Work as institute
State the M article clock signal (CK (M)) when being Article 3 clock signal (CK (3)), the M+2 bar clock
Signal (CK (M+1)) is Article 1 clock signal (CK (1))；As described the M article clock signal (CK (M))
During for Article 4 clock signal (CK (4)), when the M+2 article clock signal (CK (M+2)) is Article 2
Clock signal (CK (2)).
8. GOA circuit as claimed in claim 7, it is characterised in that described first, second, third,
And the pulse period of Article 4 clock signal (CK (1), CK (2), CK (3), CK (4)) is identical, previous
The trailing edge of bar clock signal produces with the rising edge of a rear clock signal simultaneously.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610556476.2A CN105976781B (en) | 2016-07-14 | 2016-07-14 | GOA circuits |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610556476.2A CN105976781B (en) | 2016-07-14 | 2016-07-14 | GOA circuits |
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| CN105976781B CN105976781B (en) | 2018-08-14 |
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