CN105976781B - GOA circuits - Google Patents

GOA circuits Download PDF

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Publication number
CN105976781B
CN105976781B CN201610556476.2A CN201610556476A CN105976781B CN 105976781 B CN105976781 B CN 105976781B CN 201610556476 A CN201610556476 A CN 201610556476A CN 105976781 B CN105976781 B CN 105976781B
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CN
China
Prior art keywords
film transistor
tft
thin film
electrically connected
node
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CN201610556476.2A
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Chinese (zh)
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CN105976781A (en
Inventor
肖军城
戴荣磊
尹伟红
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武汉华星光电技术有限公司
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3674Details of drivers for scan electrodes
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13454Drivers integrated on the active matrix substrate

Abstract

The present invention provides a kind of GOA circuits, the GOA circuits between second node and forward and reverse scan control module by adding third thin film transistor (TFT), the third thin-film transistor gate is controlled by forward and reverse scan control module, source electrode accesses constant pressure high potential, drain electrode is electrically connected via the 4th normally opened thin film transistor (TFT) and second node, it can prevent the current potential of the second node during touch-control scans from gliding, promote the stability of GOA circuits, also by the way that the source electrode of the 7th thin film transistor (TFT) is accessed the M+2 articles clock signal, grid is electrically connected at the drain electrode of the 6th thin film transistor (TFT), to reduce the number that the 7th thin film transistor (TFT) is opened repeatedly, prevent the threshold voltage shift of the 7th thin film transistor (TFT).

Description

GOA circuits

Technical field

The present invention relates to display technology field more particularly to a kind of GOA circuits.

Background technology

Liquid crystal display (Liquid Crystal Display, LCD) has the liquid crystals such as thin fuselage, power saving, radiationless Show that device (Liquid Crystal Display, LCD) has many merits such as thin fuselage, power saving, radiationless, has obtained extensive Using.Such as:LCD TV, mobile phone, personal digital assistant (PDA), digital camera, computer screen or notebook-type computer screen Curtain etc., occupies an leading position in flat display field.

GOA (Gate Driver on Array) technology, that is, array substrate row actuation techniques is to utilize thin film transistor (TFT) Gated sweep driving circuit is produced on film crystal by (Thin Film Transistor, TFT) LCD (Liquid Crystal Display) array processing procedure In pipe array substrate, to realize the type of drive of progressive scan, having reduces production cost and realizes panel narrow frame design Advantage is used by a variety of displays.GOA circuits have two basic functions:First is output gated sweep drive signal, is driven Grid line in dynamic panel, opens the TFT in viewing area, to charge to pixel;Second is shift LD function, when one After the completion of the output of gated sweep drive signal, the output of next gated sweep drive signal is carried out by clock control, and according to It is secondary to hand on.GOA technologies can reduce welding (bonding) process of external IC, have an opportunity promoted production capacity and reduce product at This, and liquid crystal display panel can be made to be more suitable for making the display product of narrow frame.

Embedded type touch control technology is touch panel and liquid crystal display panel to be combined as a whole, and touch panel function is embedded into In liquid crystal display panel so that liquid crystal display panel is provided simultaneously with display and perceives the function of touch-control input.With the hair at full speed of display technology Exhibition, touch-control display panel is widely accepted by people and uses, such as smart mobile phone, tablet computer have used touch-control Display panel.

Existing embedded type touch control technology is broadly divided into two kinds:One is touch-control circuits at liquid crystal cell mo(u)ld top half (On Cell), Another kind is touch-control circuit at liquid crystal cell inner mold (In Cell).Wherein, In cell types touch-control display panel is using existing thin The induction electrode (Pad) of touch-control sweep test is produced on array substrate by film transistor LCD (Liquid Crystal Display) array (Array) processing procedure On realize touch function.In cell type touch-control display panels are needed when GOA circuits work normally, being capable of a period of time in office The output end for closing all grades of GOA units in GOA circuits is carved, the output of gated sweep drive signal is stopped, to carry out touch-control scanning, After the touch-control end of scan, GOA circuits restore normal again, continue to output gated sweep drive signal, are driven while touch-control scans The node of dynamic output end output needs to maintain working condition current potential.

Invention content

The purpose of the present invention is to provide a kind of GOA circuits, when touch-control scans, can maintain the height electricity of second node Position, prevents the current potential of the second node when touch-control scans from gliding, and promotes the stability of GOA circuits.

To achieve the above object, the present invention provides a kind of GOA circuits, including:Cascade multistage GOA unit, per level-one GOA unit includes:Forward and reverse scan control module, output module, node control module and output resetting module;

If M and N are positive integer, except first order GOA unit, second level GOA unit, penultimate stage GOA unit and most Outside rear stage GOA unit, in N grades of GOA units:

Forward and reverse scan control module includes:First film transistor and the second thin film transistor (TFT);Described first The grid of thin film transistor (TFT) is electrically connected at the output end of N-2 grades of GOA units, and source electrode accesses forward scan and controls signal, leakage Pole is electrically connected at first node;The grid of second thin film transistor (TFT) is electrically connected at the output of N+2 grades of GOA units End, source electrode access reverse scan and control signal, and drain electrode is electrically connected at first node;

The output module includes:12nd thin film transistor (TFT);The grid of 12nd thin film transistor (TFT) is electrically connected In second node, source electrode accesses the M articles clock signal, and drain electrode is electrically connected at output end;

The node control module includes:Third thin film transistor (TFT), the 4th thin film transistor (TFT), the 5th thin film transistor (TFT), Six thin film transistor (TFT)s, the 7th thin film transistor (TFT), the 8th thin film transistor (TFT), the 9th thin film transistor (TFT), the tenth thin film transistor (TFT), the tenth One thin film transistor (TFT), the first capacitance, the second capacitance and third capacitance;The grid of the third thin film transistor (TFT) is electrically connected In first node, source electrode accesses constant pressure high potential, and drain electrode is electrically connected at third node;The grid of 4th thin film transistor (TFT) Constant pressure high potential is accessed, source electrode is electrically connected at third node, and drain electrode is electrically connected at second node;5th film crystal The grid of pipe accesses the M articles clock signal with source electrode, and drain electrode is electrically connected at fourth node;6th thin film transistor (TFT) Grid is electrically connected at fourth node, and source electrode accesses the M+2 articles clock signal, and drain electrode is electrically connected at the 7th thin film transistor (TFT) Grid;The source electrode of 7th thin film transistor (TFT) accesses the M+2 articles clock signal, and drain electrode is electrically connected at the 5th node;It is described The grid of 8th thin film transistor (TFT) is electrically connected at first node, and source electrode is electrically connected at fourth node, and drain electrode access constant pressure is low Current potential;The grid of 9th thin film transistor (TFT) is electrically connected at first node, and source electrode is electrically connected at the 5th node, and drain electrode connects Enter constant pressure low potential;The grid of tenth thin film transistor (TFT) is electrically connected at the 5th node, and source electrode is electrically connected at the second section Point, drain electrode access constant pressure low potential;The grid of 11st thin film transistor (TFT) is electrically connected at the 5th node, and source electrode electrically connects It is connected to output end, drain electrode access constant pressure low potential;One end of first capacitance is electrically connected at third node, other end access Constant pressure low potential;One end of second capacitance is electrically connected at the 5th node, and the other end accesses constant pressure low potential;The third One end of capacitance is electrically connected at fourth node, and the other end accesses constant pressure low potential;

The output resets module:13rd thin film transistor (TFT);The grid of 13rd thin film transistor (TFT) accesses Overall situation control signal, source electrode are electrically connected at output end, and drain electrode is electrically connected at constant pressure low potential.

In first order GOA unit and second level GOA unit, the grid of the first film transistor accesses circuit and rises Beginning signal.

In afterbody GOA unit and penultimate stage GOA unit, the grid of second thin film transistor (TFT) accesses Circuit initial signal.

Each thin film transistor (TFT) is N-type TFT.

When panel is normally shown, the global control signal is low potential;It is described full when panel carries out touch-control scanning Office's control signal is high potential.

When the GOA circuits forward scan, the forward scan control signal is high potential, and reverse scan control signal is Low potential;

When the GOA circuits reverse scan, the forward scan control signal is low potential, and reverse scan control signal is High potential.

Including four clock signals:First, second, third and Article 4 clock signal;When the M articles clock signal For Article 3 clock signal when, the M+2 articles clock signal is first article of clock signal;When the M articles clock signal is the 4th When clock signal, the M+2 articles clock signal is Article 2 clock signal.

Described first, second, third and Article 4 clock signal pulse period it is identical, under previous clock signal Drop generates simultaneously along the rising edge with latter clock signal.

Beneficial effects of the present invention:The present invention provides a kind of GOA circuits, the GOA circuits by second node and Third thin film transistor (TFT) is added between forward and reverse scan control module, the third thin-film transistor gate is controlled by forward and reverse scanning Molding block controls, and source electrode accesses constant pressure high potential, and drain electrode is electrically connected via the 4th normally opened thin film transistor (TFT) and second node, It can prevent the current potential of the second node during touch-control scans from gliding, promote the stability of GOA circuits, also by by the 7th film The source electrode of transistor accesses the M+2 articles clock signal, and grid is electrically connected at the drain electrode of the 6th thin film transistor (TFT), to reduce the 7th The number that thin film transistor (TFT) is opened repeatedly prevents the threshold voltage shift of the 7th thin film transistor (TFT).

Description of the drawings

For further understanding of the features and technical contents of the present invention, it please refers to below in connection with the detailed of the present invention Illustrate and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.

In attached drawing,

Fig. 1 is the circuit diagram of the GOA circuits of the present invention;

Sequence diagram when Fig. 2 is the GOA circuit forward scans of the present invention;

Fig. 3 is the circuit diagram of the first order GOA unit of the GOA circuits of the present invention;

Fig. 4 is the circuit diagram of the second level GOA unit of the GOA circuits of the present invention;

Fig. 5 is the circuit diagram of the penultimate stage GOA unit of the GOA circuits of the present invention;

Fig. 6 is the circuit diagram of the afterbody GOA unit of the GOA circuits of the present invention.

Specific implementation mode

Further to illustrate the technological means and its effect of the invention taken, below in conjunction with the preferred implementation of the present invention Example and its attached drawing are described in detail.

Referring to Fig. 1, the present invention provides a kind of GOA circuits, including:Cascade multistage GOA unit, per level-one GOA unit Include:Forward and reverse scan control module 100, output module 200, node control module 300 and output resetting module 400;

If M and N are positive integer, except first order GOA unit, second level GOA unit, penultimate stage GOA unit and most Outside rear stage GOA unit, in N grades of GOA units:

Forward and reverse scan control module 100 includes:First film transistor T1 and the second thin film transistor (TFT) T2; The grid of the first film transistor T1 is electrically connected at the output end G (N-2) of N-2 grades of GOA units, and source electrode access is positive Scan control signal U2D, drain electrode are electrically connected at first node H (N);The grid of the second thin film transistor (TFT) T2 is electrically connected In the output end G (N+2) of N+2 grades of GOA units, source electrode accesses reverse scan and controls signal D2U, and drain electrode is electrically connected at first Node H (N);

The output module 200 includes:12nd thin film transistor (TFT) T12;The grid of the 12nd thin film transistor (TFT) T12 It is electrically connected at second node Q (N), source electrode accesses the M articles clock signal CK (M), and drain electrode is electrically connected at output end G (N);

The node control module 300 includes:Third thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4, the 5th film are brilliant Body pipe T5, the 6th thin film transistor (TFT) T6, the 7th thin film transistor (TFT) T7, the 8th thin film transistor (TFT) T8, the 9th thin film transistor (TFT) T9, Ten thin film transistor (TFT) T10, the 11st thin film transistor (TFT) T11, the first capacitance C1, the second capacitance C2 and third capacitance C3;It is described The grid of third thin film transistor (TFT) T3 is electrically connected at first node H (N), and source electrode accesses constant pressure high potential VGH, and drain electrode electrically connects It is connected to third node K (N);The grid of the 4th thin film transistor (TFT) T4 accesses constant pressure high potential VGH, and source electrode is electrically connected at the Three node K (N), drain electrode are electrically connected at second node Q (N);The grid of the 5th thin film transistor (TFT) T5 is accessed with source electrode The M articles clock signal CK (M), drain electrode are electrically connected at fourth node W (N);The grid electricity of 6th thin film transistor (TFT) (T6) Property be connected to fourth node W (N), source electrode accesses the M+2 articles clock signal CK (M+2), and drain electrode is electrically connected at the 7th film crystalline substance The grid of body pipe T7;The source electrode of the 7th thin film transistor (TFT) T7 accesses the M+2 articles clock signal CK (M+2), and drain electrode electrically connects It is connected to the 5th node P (N);The grid of the 8th thin film transistor (TFT) T8 is electrically connected at first node H (N), and source electrode electrically connects It is connected to fourth node W (N), drain electrode access constant pressure low potential VGL;The grid of the 9th thin film transistor (TFT) T9 is electrically connected at One node H (N), source electrode are electrically connected at the 5th node P (N), drain electrode access constant pressure low potential VGL;Tenth film crystal The grid of pipe T10 is electrically connected at the 5th node P (N), and source electrode is electrically connected at second node Q (N), the low electricity of drain electrode access constant pressure Position VGL;The grid of the 11st thin film transistor (TFT) T11 is electrically connected at the 5th node P (N), and source electrode is electrically connected at output Hold G (N), drain electrode access constant pressure low potential VGL;One end of the first capacitance C1 is electrically connected at third node K (N), another It terminates into constant pressure low potential VGL;One end of the second capacitance C2 is electrically connected at the 5th node P (N), and the other end accesses constant pressure Low potential VGL;One end of the third capacitance C3 is electrically connected at fourth node W (N), and the other end accesses constant pressure low potential VGL;

The output resets module 400:13rd thin film transistor (TFT) T13;The 13rd thin film transistor (TFT) T13's The global control signal GAS of grid access, source electrode are electrically connected at output end G (N), and drain electrode is electrically connected at constant pressure low potential VGL.

Specifically, Fig. 3 to Fig. 6 is please referred to, in first order GOA unit and second level GOA unit, the first film is brilliant The grid of body pipe T1 accesses circuit initial signal STV, described in afterbody GOA unit and penultimate stage GOA unit The grid of second thin film transistor (TFT) T2 accesses circuit initial signal STV.

Further, referring to Fig. 1, each thin film transistor (TFT) is N-type TFT, wherein carried out just in panel Often when display, the global control signal Gas is low potential;When panel carries out touch-control scanning, the global control signal Gas is High potential.When the GOA circuits forward scan, the forward scan control signal U2D is high potential, and reverse scan controls signal D2U is low potential;When reverse scan, the forward scan control signal U2D is low potential, and reverse scan control signal D2U is High potential.

It should be noted that referring to Fig. 2, the GOA circuits include four clock signals altogether:The first, second, third, And Article 4 clock signal CK (1), CK (2), CK (3), CK (4);When the M articles clock signal CK (M) is Article 3 clock When (3) signal CK, the M+2 articles clock signal CK (M+1) is first article of clock signal CK (1);As the M articles clock signal CK (M) when being Article 4 clock signal (4) CK, the M+2 articles clock signal CK (M+2) is Article 2 clock signal CK (2).Described One, second, third and Article 4 clock signal CK (1), CK (2), CK (3), the pulse period of CK (4) are identical, according to first, Second, third and Article 4 clock signal CK (1), CK (2), CK (3), CK (4) put in order, previous clock signal Failing edge and the rising edge of latter clock signal generate simultaneously, i.e., first pulse of described first clock signal CK (1) Signal generates first, first pulse signal ends of the first clock signal CK (1) whiles the Article 2 clock letter First pulse signal of number CK (2) generates, while first pulse signal ends of the Article 2 clock signal CK (2) First pulse signal of the Article 3 clock signal CK (3) generates, first arteries and veins of the Article 3 clock signal CK (3) First pulse signal for rushing the Article 4 clock signal CK (4) while signal terminates generates, the Article 4 clock letter Second pulse signal of first clock signal CK (1) described in while first pulse signal ends of number CK (4) generates.

Further, GOA circuits of the invention are scanned using interleaved mode, first order GOA unit it is defeated Outlet is electrically connected third level GOA unit, and the output end of second level GOA unit is electrically connected fourth stage GOA unit, the third level The output end of GOA unit is electrically connected level V GOA unit, and it is mono- that the output end of fourth stage GOA unit is electrically connected the 6th grade of GOA Member, and so on.

Please refer to Fig. 1 and Fig. 2, below by taking the first embodiment of the GOA circuits of the present invention carries out forward scan as an example, Illustrate the specific work process of the GOA circuits of the present invention:

First, it (is circuit in the first order, second level GOA unit that the output end of N-2 grades of GOA units, which provides high potential, Initial signal STV provides high potential), first film transistor T1 is opened, and the forward scan of high potential controls signal U2D through first First node H (N) is charged to high potential by thin film transistor (TFT) T1, and third thin film transistor (TFT) T3 is opened, the 4th thin film transistor (TFT) T4 It is opened always by the control of constant pressure high potential VGH, constant pressure high potential VGH charges to third node K (N) and second node Q (N) High potential, the 12nd thin film transistor (TFT) T12 are opened;At the same time, the 8th thin film transistor (TFT) T8 is opened, and fourth node W (N) is drawn Down to constant pressure low potential VGL, the 9th thin film transistor (TFT) T9 is opened, and the 5th node P (N) is pulled low to constant pressure low potential VGL, by the Four and the 5th node W (N), P (N) control the six, the tenth and the 11st thin film transistor (TFT) T6, T10, T11 be turned off; The M articles clock signal CK (M) is low potential, and the 5th thin film transistor (TFT) T5 is closed, and output end G (N) is low potential;

Then, the output end of N-2 grades of GOA units becomes low potential, and the M articles clock signal CK (M) becomes high potential, the Three node K (N) and second node Q (N) are kept high potential by the memory action of the first capacitance C1, by second node Q (N) controls 12nd thin film transistor (TFT) T12 is opened, and the high potential of the M articles clock signal CK (M) will be exported through the 12nd thin film transistor (TFT) T12 End G (N) charges to high potential and is exported as gated sweep drive signal;Meanwhile the 5th of the M articles clock signal CK (M) control Thin film transistor (TFT) T5 is opened, and fourth node W (N) is charged to high potential, and the 6th thin film transistor (TFT) T6 is opened, the M+2 bars clock Signal CK (M+2) is low potential, and the 5th node P (N) keeps low potential, the tenth and the 11st thin film transistor (TFT) T10, T11 keep It closes;

Then, the M+2 articles clock signal CK (M+2) becomes high potential, and fourth node W (N) is stored by third capacitance C3 Effect continues to high potential, and the 7th thin film transistor (TFT) T7 is opened, and the 5th node P (N) is charged to high potential, and the tenth and the 11 thin film transistor (TFT) T10, T11 are opened, and drag down second node Q (N) and output end G (N) respectively to constant pressure low potential VGL;

Finally, the M+2 articles clock signal CK (M+2) becomes low potential, and the 5th node P (N) is stored by the second capacitance C2 Effect still keeps high potential, the tenth and the 11st thin film transistor (TFT) T10, T11 continue to open, second node Q (N) and output end G (N) low potential is kept.

The course of work of reverse scan is similar with forward scan, it is only necessary to by reverse scan control signal D2U settings For high potential, forward scan control signal U2D is set as low potential, and the direction of scanning is become from the first order to afterbody scanning Afterbody is scanned to the first order, and details are not described herein again.

In above-mentioned scanning process, when touch-control scanning need not be carried out, the 13rd thin film transistor (TFT) in GOA units at different levels T13 is closed always by the control of the overall signal Gas of low potential, and GOA units at different levels show according to the above-mentioned course of work and sweep successively It retouches.And when needing to carry out touch-control scanning, the global control signal Gas becomes high potential, and the in GOA units at different levels the 13rd Thin film transistor (TFT) T13 is opened, and the output end G (N) in GOA units at different levels exports constant pressure low potential VGL, and is scanned in touch-control The current potential that the second node Q (N) of level-one GOA unit is being scanned before starting is maintained high electricity by the memory action of the first capacitance C1 Position, and will not be glided by the protection of third thin film transistor (TFT) T3, it is normal to can continue to carry out after the touch-control end of scan Display scanning.

In addition, in the present invention, the grid of the 7th thin film transistor (TFT) T7 is electrically connected at the leakage of the 6th thin film transistor (TFT) T6 Pole, only when the 6th thin film transistor (TFT) T6 is opened, the M+2 articles clock signal CK (M+2) could access the 7th thin film transistor (TFT) The grid of T7, that is to say, that compared to the grid that the M+2 articles clock signal CK (M+2) is directly accessed to the 7th thin film transistor (TFT) T7 Pole can reduce the number that the 7th thin film transistor (TFT) T7 is opened repeatedly, and preventing the 7th thin film transistor (TFT) T7 from opening repeatedly leads to threshold value Variation (Vth shift) promotes the stability of GOA circuits.

In conclusion the present invention provides a kind of GOA circuits, the GOA circuits are by second node and forward and reverse sweeping It retouches and adds third thin film transistor (TFT) between control module, the third thin-film transistor gate is by forward and reverse scan control module control System, source electrode access constant pressure high potential, and drain electrode is electrically connected via the 4th normally opened thin film transistor (TFT) and second node, can prevent The current potential of second node glides during touch-control scans, and promotes the stability of GOA circuits, also by by the 7th thin film transistor (TFT) Source electrode accesses the M+2 articles clock signal, and grid is electrically connected at the drain electrode of the 6th thin film transistor (TFT), to reduce by the 7th film crystal The number opened repeatedly is managed, the threshold voltage shift of the 7th thin film transistor (TFT) is prevented.

The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology Other various corresponding change and deformations are made in design, and all these change and distortions should all belong to the claims in the present invention Protection domain.

Claims (8)

1. a kind of GOA circuits, which is characterized in that including:Cascade multistage GOA unit, every level-one GOA unit include:It is positive and negative To scan control module (100), output module (200), node control module (300) and output resetting module (400);
If M and N are positive integer, except first order GOA unit, second level GOA unit, penultimate stage GOA unit and last Outside grade GOA unit, in N grades of GOA units:
Forward and reverse scan control module (100) includes:First film transistor (T1) and the second thin film transistor (TFT) (T2);The grid of the first film transistor (T1) is electrically connected at the output end (G (N-2)) of N-2 grades of GOA units, source Forward scan control signal (U2D) is accessed in pole, and drain electrode is electrically connected at first node (H (N));Second thin film transistor (TFT) (T2) grid is electrically connected at the output end (G (N+2)) of N+2 grades of GOA units, and source electrode accesses reverse scan and controls signal (D2U), drain electrode is electrically connected at first node (H (N));
The output module (200) includes:12nd thin film transistor (TFT) (T12);The grid of 12nd thin film transistor (TFT) (T12) Pole is electrically connected at second node (Q (N)), and source electrode accesses the M articles clock signal (CK (M)), and drain electrode is electrically connected at output end (G(N));
The node control module (300) includes:Third thin film transistor (TFT) (T3), the 4th thin film transistor (TFT) (T4), the 5th film Transistor (T5), the 6th thin film transistor (TFT) (T6), the 7th thin film transistor (TFT) (T7), the 8th thin film transistor (TFT) (T8), the 9th film Transistor (T9), the tenth thin film transistor (TFT) (T10), the 11st thin film transistor (TFT) (T11), the first capacitance (C1), the second capacitance (C2) and third capacitance (C3);The grid of the third thin film transistor (TFT) (T3) is electrically connected at first node (H (N)), source Constant pressure high potential (VGH) is accessed in pole, and drain electrode is electrically connected at third node (K (N));The grid of 4th thin film transistor (TFT) (T4) Constant pressure high potential (VGH) is accessed in pole, and source electrode is electrically connected at third node (K (N)), and drain electrode is electrically connected at second node (Q (N));The grid of 5th thin film transistor (TFT) (T5) accesses the M articles clock signal (CK (M)) with source electrode, and drain electrode electrically connects It is connected to fourth node (W (N));The grid of 6th thin film transistor (TFT) (T6) is electrically connected at fourth node (W (N)), source electrode The M+2 articles clock signal (CK (M+2)) is accessed, drain electrode is electrically connected at the grid of the 7th thin film transistor (TFT) (T7);Described 7th The source electrode of thin film transistor (TFT) (T7) accesses the M+2 articles clock signal (CK (M+2)), and drain electrode is electrically connected at the 5th node (P (N));The grid of 8th thin film transistor (TFT) (T8) is electrically connected at first node (H (N)), and source electrode is electrically connected at the 4th Node (W (N)), drain electrode access constant pressure low potential (VGL);The grid of 9th thin film transistor (TFT) (T9) is electrically connected at first Node (H (N)), source electrode are electrically connected at the 5th node (P (N)), drain electrode access constant pressure low potential (VGL);Tenth film The grid of transistor (T10) is electrically connected at the 5th node (P (N)), and source electrode is electrically connected at second node (Q (N)), and drain electrode connects Enter constant pressure low potential (VGL);The grid of 11st thin film transistor (TFT) (T11) is electrically connected at the 5th node (P (N)), source Pole is electrically connected at output end (G (N)), drain electrode access constant pressure low potential (VGL);One end of first capacitance (C1) electrically connects It is connected to third node (K (N)), the other end accesses constant pressure low potential (VGL);One end of second capacitance (C2) is electrically connected at 5th node (P (N)), the other end access constant pressure low potential (VGL);One end of the third capacitance (C3) is electrically connected at the 4th Node (W (N)), the other end access constant pressure low potential (VGL);
The output resets module (400):13rd thin film transistor (TFT) (T13);13rd thin film transistor (TFT) (T13) The global control signal (GAS) of grid access, source electrode is electrically connected at output end (G (N)), and drain electrode is electrically connected at the low electricity of constant pressure Position (VGL).
2. GOA circuits as described in claim 1, which is characterized in that in first order GOA unit and second level GOA unit, institute The grid for stating first film transistor (T1) accesses circuit initial signal (STV).
3. GOA circuits as described in claim 1, which is characterized in that mono- in afterbody GOA unit and penultimate stage GOA In member, the grid of second thin film transistor (TFT) (T2) accesses circuit initial signal (STV).
4. GOA circuits as described in claim 1, which is characterized in that each thin film transistor (TFT) is N-type TFT.
5. GOA circuits as claimed in claim 4, which is characterized in that when panel is normally shown, the global control signal (Gas) it is low potential;When panel carries out touch-control scanning, the global control signal (Gas) is high potential.
6. GOA circuits as claimed in claim 4, which is characterized in that when the GOA circuits forward scan, the forward scan It is high potential to control signal (U2D), and it is low potential that reverse scan, which controls signal (D2U),;
When the GOA circuits reverse scan, the forward scan control signal (U2D) is low potential, and reverse scan controls signal (D2U) it is high potential.
7. GOA circuits as described in claim 1, which is characterized in that including four clock signals:First, second, third and Article 4 clock signal (CK (1), CK (2), CK (3), CK (4));When the M articles clock signal (CK (M)) is Article 3 When clock signal (CK (3)), the M+2 articles clock signal (CK (M+1)) is first article of clock signal (CK (1));When described the M articles When clock signal (CK (M)) is Article 4 clock signal (CK (4)), the M+2 articles clock signal (CK (M+2)) is believed for Article 2 clock Number (CK (2)).
8. GOA circuits as claimed in claim 7, which is characterized in that described first, second, third and Article 4 clock signal The pulse period of (CK (1), CK (2), CK (3), CK (4)) is identical, and the failing edge of previous clock signal is believed with latter clock Number rising edge generate simultaneously.
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CN106571125B (en) * 2016-11-07 2019-12-03 深圳市华星光电技术有限公司 GOA driving circuit and its driving method, liquid crystal display
CN106782389A (en) * 2016-12-30 2017-05-31 武汉华星光电技术有限公司 A kind of array base palte horizontal drive circuit
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US10540937B2 (en) 2017-11-17 2020-01-21 Wuhan China Star Optoelectronics Technology Co., Ltd. GOA circuit
CN107767834A (en) * 2017-11-17 2018-03-06 武汉华星光电技术有限公司 A kind of GOA circuits
CN108010495B (en) * 2017-11-17 2019-12-13 武汉华星光电技术有限公司 GOA circuit
CN108010496B (en) * 2017-11-22 2020-04-14 武汉华星光电技术有限公司 GOA circuit
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US10453415B2 (en) 2017-11-29 2019-10-22 Wuhan China Star Optoelectronics Technology Co., Ltd. GOA circuit and embedded touch display panel
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CN108766380A (en) * 2018-05-30 2018-11-06 武汉华星光电技术有限公司 GOA circuits
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