GB2343068A - A shift register for driving LCD pixel rows - Google Patents

A shift register for driving LCD pixel rows Download PDF

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Publication number
GB2343068A
GB2343068A GB9924976A GB9924976A GB2343068A GB 2343068 A GB2343068 A GB 2343068A GB 9924976 A GB9924976 A GB 9924976A GB 9924976 A GB9924976 A GB 9924976A GB 2343068 A GB2343068 A GB 2343068A
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United Kingdom
Prior art keywords
electrode
control electrode
transistor
control
input
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GB9924976A
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GB2343068B (en
GB9924976D0 (en
Inventor
Sang Young Yoon
Jin Sang Kim
Ju Cheon Yeo
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LG Display Co Ltd
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LG Philips LCD Co Ltd
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Priority claimed from KR1019980044180A external-priority patent/KR100281336B1/en
Priority claimed from KR10-1999-0004372A external-priority patent/KR100438525B1/en
Application filed by LG Philips LCD Co Ltd filed Critical LG Philips LCD Co Ltd
Publication of GB9924976D0 publication Critical patent/GB9924976D0/en
Publication of GB2343068A publication Critical patent/GB2343068A/en
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Publication of GB2343068B publication Critical patent/GB2343068B/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Shift Register Type Memory (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

A scan pulse generator for an LCD comprises a cascade of clocked shift register stages. In each stage, the input signal is applied to a diode-connected transistor T1 which charges the gate of the output pull-up transistor T5 so that when the first clock signal (C1 in the illustrated stage) goes high the output node ROWi goes high. The effect of the bootstrap capacitor CAP1 is stabilised by the capacitor CL1. The output node ROWi is discharged by the pull-down transistor T6 when the second clock signal (C3 in the illustrated stage) goes high. Discharge of the output node ROWi may be assisted by a second pull-down transistor (figure 13) controlled by the output of the next stage. Leakage through each of the transistors T1-T4 may be reduced by implementing these devices with a series combination of two separate devices (figures 16 and 18).

Description

2343068 SHIFI REGISTER This invention relates to a circuit for dri'ving a
display device of active ma-t-nix 1.) type, and more particularly to a shift register for driving pixel rows in a liquid crystal display.
Generally, a conventional liquid crystal display device used in a television or a computer includes a liquid crystal matrix having liquid crystal cells arranged at intersections of data lines with select or gate lines. The select lines are horizontal lines (i.e., row lines) of the liquid crystal matrix, which are sequentially driven with a shift register.
As shown in Fig. 1, the conventional 3)-phase shift register includes n stages 2, to 2. connected in cascade and simultaneously connected, via output lines to 41 to 4', to n row lines ROW1 to ROWn or gate lines, respectively. A scanning pulse SP is inputted to the first stage 21, and output signals g, to &-, of the previous stages are inputted to the 2nd to nth stages 2, to 2,, respectively. Also, n stages 2, to 2. receive two clock signals out of three clock signals C I to C3. Each of the n stages 21 to 2,, drives an associated row line ROWi connected to a pixel train with the two clock signals and the output signals of previous stages or with the two clock signals and the scanning pulse SP.
As shown in Fig. 2, each of the stages 21 to 2,, includes a fifth NMO S transistor T5 for applying a high logic voltage signal to an output line 4j, and a sixth NMOS transistor T6 for applying a low logic voltage signal to the output line 4j. If a high logic level of (i-I)th row line input signal & is applied from the previous stage 2j_j, then first and fourth NMOS transistors T I and T4 are turned on. As seen from Fig. 3, a high logic level of third clock signal C3 is synchronized with the (i- I)th row line input 2 signal gi C -, and applied to a third NMOS transistor T', thereby turning on the third NNMOS transistor T'). The third and fourth NjMOS transistors T') and T4 are a so-called ratioed loaic' which are set to an appropriate ratio of resistance values in such a manner that a voltage at a second node P2 becomes a low level when the third and fourth N.MOS transistors T3) and T4 are simultaneously turned on. Accordingly, when ('-I)th row line input signal & 1 0 C -, is applied, a low logic level voltage emerges at the second node P2. At this time, the second and sixth NMOS transistors T2 and T6 are turned off by a low logic level voltacre from the second node P2. A first node P I is charged into a high logic level voltage by a supply voltage VDD when the first NMOS transistor T I is turned on and the second NMOS transistor T2 is turned off. When the high logic level voltage at the first node P 1 arrives at a threshold voltage thereof, the fifth NMOS transistor T5 is turned off. At this time, since the first clock signal C I remains at a low logic level, a low logic level voltage emerges at the output line 4j.
If the first clock signal C I has a high logic level voltage during a time interval when a voltage at the first node P I remains at a high logic level, then the output line 4i becomes a high logic level by a high logic level voltage of the first clock signal C1 applied via the fifth NMOS transistor T5. Accordingly, a high logic level output signal Vout emerges at the output line 4j. At this time, since the output line 4i and the first node P I are coupled as shown in Fig. 4 with a parasitic capacitance Cgs existing between the gate and the source of the fifth NMOS transistor T5, a voltage at the first node P I is bootstrapped into a high voltage level. Accordingly, the high logic level voltage of the first clock signal C 1 is applied to the output line 4i almost without a loss.
Such a bootstrap system is used to compensate a voltage loss caused by a threshold voltage generated at a circuit including NMOS transistors.
Also, if the first clock signal C I is changed from a high logic level voltage into a low logic level voltage, a voltage Vout at the output line 4i drops into a low logic level voltage because the fifth NMOS transistor T5 is in a turn-off state. Furthermore, since the first and fourth NMOS transistors Ti and T4 are turned off by the (i-I)th row line input signal gi-, having a low logic level voltage in such a manner to be supplied with no voltage, a voltage level at the first node P I also drops slowly. In such a state, if the third clock signal C3 has a high logic level voltage, then the third NMOS transistor T') is turned off to thereby begin charging the second node P2 into a high logic level voltage with the aid of the supply voltage VDD applied via the third N-,,MOS transistor T'), The sixthN-TMOS transistor T6 is turned on by a voltage signal higher than its threshold voltage applied from the second node P2 to discharge a voltage charged on the output line 4i toward a ground voltage VSS. As a result, a voltage at the row line ROWi connected to the output line 4i maintains a low logic level.
In order to operate such a shift register normally, a resistance ratio of the third and fourth NMO S transistors T-3) and T4 serving as a ratioed loaic must be set accurately. In other words, in order to generate a low logic level voltage at the second node P2 when the third clock sicynal C-') having a hich loaic level volta- e and the (i- I)th row line input signal g., are applied simultaneously to the gates of the third and fourth NIMOS transistors T3 and T4, a channel width of the fourth NMOS transistor T4 must be about ten times larger than that of the third NMOS transistor 73. If characteristics of the NMOS transistors T3 and T4 become non-uniform, a current ratio of the third NMOS transistor T-31 to the fourth NMOS transistor T4 varies. In this case, the shift register fails to operate properly.
Further, since a direct current flows continuously at the third and fourth NMOS transistors T3 and T4 when the third and fourth NMOS transistors D and T4 are simultaneously turned on by the third clock signal C3 and the (i-I)th row line input signal &-j, the characteristics of the third and fourth NMOS transistors T3 and T4 are susceptible to deterioration by overcurrent. Also, if the first clock signal CI is changed from a low logic level voltage into a high logic level voltage during an interval when a voltage at the first node P I is in a state of high logic level, then a rising width in a bootstrapped voltage at the first node P I becomes different in accordance with a parasitic capacitance value of the fifth NMOS transistor T5 and a change in the parasitic capacitance at the first node P 1. The voltage rising width at the first node P 1 is as described in the following formula (1):
j VP1 Cox A VOUt30 (1) C L + 4 wherein J Vp I and 2 Vout represent a voltage change amount at the first node P 1 1.7 0 and a voltaae change amount at the output line 4j, respectively, and C, and C 0, represent a parasitic capacitance at the first node P I and a parasitic capacitance of the fifth N-MOS transistor T5, respectively. The parasitic capacitance Cox of the fifth NN.'L'VIOS transistor t5 is equal to a sum of a parasitic capacitance Cgs between the gate and the source thereof and a parasitic capacitance Cds between the drain and the 0ate thereof As seen from the formula (1), since a rising width in a voltage at the first node P I is changed by the capacitance C, at the first node P I and the parasitic capacitance io Cox of the fifth NTMOS transistor t5, it is difficult to set a characteristic of shift register accurately. Moreover, in the shift register of Fig. 2, the output voltage Vout at the output line 4i is distorted because a voltage at the second node P2 also is raised by a parasitic capacitance between the gate and the drain of the sixth NMOS transistor T6 as a voltage at the output line 4i changes into a high logic level.
Fig. 5 is a block diagram showing schematically the configuration of a conventional 4-phase shift register. The shift register of Fig. 5 includes n stages 12, to 12,, which are cascade-connected to each other and connected respectively to n row lines ROWI to ROWn through output lines 14, to 14n- In the shift register, a start pulse SP is input to the first stage 12,. The second to nth stages 12, to 12,' each responds to an output signal a, to &., of a previous stage 12, to 12.
and any two of 4 clock signals Cl to C4 selects the row line ROWi connected to the pixel row. Eachof the stages 12, to 12,, has a same circuit configuration and shifts the start pulse toward output line 14i every period of the horizontal synchronous signal.
Referring to Fig. 6, there is illustrated the circuit configuration of the arbitrary stage 12i shown in Fig. 5. The stage 12i includes a fifth NMOS transistor T5 for applying a high logic voltage signal to the output line 14i and a sixth NMOS transistor T6 for supplying a low logic voltage signal to the output line 14j.
If an output signal gi-, of a previous stage, which is used as the start pulse, goes to a high logic level in the interval of tl as shown in Fig. 7, a first and fourth NMOS transistors T I and T4 are turned-6n. Then, a voltage signal VP I is charged on a first node PI while a voltage signal VP2 on a second node P2 is discharged. Therefore, the fifth'TN-TMOS transistor T5 is turned-on by the voltage VP I on the first node P 1. At this time, since a first clock signal C I applied to the fifth NMMOS transistor T5 has a low logic level, there is developed an output signal Vout having the low logic level on the output line 14,. In the interval of t2 when the output signal gi-I of the previous sta-e is inverted into a low logic level and the first clock signal C I has the high logic level, the first NTMOS transistor TJ is turried-off and the voltage signal VPl on the first node PI is bootstrapped by coupling with a parasitic capacitor Cgs between the gate and source electrodes of the fifth MMOS transistor T5. To this end, the first clock signal Cl having the high logic level is applied to the output line 14i without a leakage.
io Next, if the first clock signal C I is transited into the low logic level in the interval of 0), the output signal Vout on the output line 14, varies into the low logic level because the fifth NMOS transistor T5 maintains the turried-on state. Finally, in the interval of t4 when a third clock signal C') having the high logic level is applied to a third NMOS transistor T-31, the third NTMOS transistor T3 is turned-on to charge a high level voltage VDD on the second node P2, thereby developing the high logic level on the second node P2. The voltage signal VP2 charged on the second node P2 allows the sixth NMOS transistor T6 to be turried-on such that the voltage charged on the output line 14i is discharged to a ground voltage source VSS through the sixth NMOS transistor T6. Also, the voltage signal VP2 charged on the second node P2 enables the second NMOS transistor T2 to be turried-on, thereby discharging the voltage signal VP I charged on the first node PI toward the ground voltage source VSS through the second NMOS transistor T2.
In Fig. 6, the voltage signal VP I on the first node P I is bootstrapped into the very high level in the interval of t2 causing the bootstrapping operation. However, if the absolute threshold voltage I Vth I of the first and second NMOS transistors T I and T2 is low, the voltage signal VP 1 on the first node P 1 is discharged as shown in Fig. 8. This results from that a current signal on the first node P1 is leaked through each of the first and second NMOS transistors T I and T2.
Fig. 8 explains a resultant of a simulation for the prior shift register circuit including transistors of which an absolute threshold voltage I Vth I is low. Also, Fig. 8 shows the waveforms of an output signal Vout of the present stage 12j, the voltage 6 signals VP 1 and VP2 on the first and second nodes P I and P2. Referring to Fig. 8, the voltaae si-nal VPI on the first node PI is distorted by a current signal leaked Z.) through each of the first and second NMOS transistors T I and'T2. Due to this, the output signal Vout charged on the output line 14i is also distorted. As a result, it des a disadvantage that a next stage malfunctions. Also, the voltage signal VP2 provi In ZP on the second node P2 is unstable because of a current signal leaked by the third and fourth NMOS transistors T3 and T4, as shown in Fig. 8. Due to this, the second and sixth NTMOS transistors T2 and T6 also malfunction. Further, since the drain and cate electrodes of the first NMOS transistor T I are connected to each other, the output signal & of the previous stage is applied to the first node PI in the state of dropping P down by the threshold voltage Vth of the first NMOS transistor Th Theoutputsignal Cr of the previous stage is dropped down more in the case that it is defective in the liquid crystal panel. In this case, the output signal g,-I of the previous stage dropped down more and more in accordance with proceeding of the stage toward the post stage.
13 As a result, the shift register circuit does not operate.
Accordingly, it is an object of the present invention to provide a shift register that is adaptive for preventing a change in a circuit characteristic caused by a change in a parasitic capacitance.
A further object of the present invention is to provide a shift register that is adaptive for preventing deterioration in a circuit characteristic caused by overcurrent.
A still further object of the present invention is to provide a shift register that is adaptive for minimizing a voltage'loss caused by the threshold voltage.
A still further object of the present invention is to provide a shift register that is capable of enlarging the range of operating voltage as well as preventing a malfunction.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
7 In order to achieve these and other objects of the invention, a shift register according to one aspect of the present invention includes a plurality of stages which are commonly connected to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator, connected to row lines, and connected, in cascade, with respect to a scanning signal, for charging and discharcring the row lines.
g Each of the plurality of stages included in the shift register according to one 0 ID aspect of the present invention comprises output circuit means including a pull-up transistor and a pull-down transistor, the pull-up transistor having a first input electrode for receiving a first clock signal having a delayed phase in comparison to the scanning signal, a first output electrode connected to the row line, and a first control electrode, the pull-down transistor having a second input electrode connected to the low level voltage source, a second output electrode connected to the row line, and a second control electrode; input circuit means being responsive to the scanning signal for generating a first control signal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the first clock signal for generating a second control signal to be applied to the second control electrode; and means for raising a voltage of the first control signal.
Each of the plurality of stages included in the shift register according to another aspect of the present invention comprises output circuit means including a pull-up transistor and a pull-down transistor, the pull-up transistor having a first input electrode for receiving a first clock signal having a delayed phase in comparison to the scanning signal, a first output electrode connected to the row line, and a first control electrode, the pull-down transistor having a second input electrode connected to the low level voltage source, a second output electrode connected to the row line, and a second control electrode; input circuit means being responsive to the scanning signal for generating a first control signal to -be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the first clock signal for generating a second control signal to be applied to the second control electrode; means for raising a voltage of thefirst control signal; and means for discharging the second control signal during a time interval when the first control signal is enabled.
8 Each of the plurality of stages included in the shift register according to still another aspect of the present invention comprises output circuit means including a pullup transistor and a pull-down transistor, the pullup transistor having a first input electrode for receiving a first clock signal having a delayed phase in comparison to the scanning signal, a first output electrode connected to the row line, and a first control electrode, the pull-down transistor having a second input electrode connected to the low level volta-e source, a second output electrode connected to the row line, and a second control electrode; input circuit means being responsive to the scanning signal for generating a first control signal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the first clock signal for generating a second control signal to be applied to the second control electrode; means for raising a voltage of the first control signal; and means for accelerating a discharging speed at the row line.
Each of the plurality of stages included in the shift register according to still another aspect of the present invention comprises: a pull-up transistor having a conduction path connected between the first clock signal line and the output terminal and a control electrode; a pull-do,?Ym transistor having a conduction path connected between the low level voltage line and the output terminal and a control electrode; first and second transistors having conduction paths connected in series between the input terminal and the control electrode of the pull-up transistor and control electrodes connected commonly to the second clock signal line, respectively, the first and second transistors allowing a voltage to be charged on the control electrode of the pull-up transistor; and third and fourth transistors having conduction paths connected in series between the third clock signal line and the control electrode of the pull-down transistor and control electrodes connected commonly to the third clock signal line, respectively, the third and fourth transistors allowing a voltage to be charged on the control electrode of the pull-down transistor.
Each of the plurality of stages included in the shift register according to still another as ect of the present invention comprises: a pull-up transistor having a p C' conduction path connected between the first clock signal line and the output terminal and a control electrode; a pull-down transistor having a conduction path connected 9 between the low level voltage line and the output terminal and a control electrode; first and second transistors having respectively conduction paths connected in series between the input terminal and the control electrode of the pull-up transistor and control electrodes connected independently to the input terminal and the second clock signal line, the first and second transistors allowing a voltage to be charged on the control electrode of the pull-up transistor; and third and fourth transistors having conduction paths connected in series between the third clock signal line and the control electrode of the pull-down transistor and control electrodes connected commonly to the third clock signal line, respectively, the third and fourth transistors allowing a voltage to be charged on the control electrode of the pull-down transistor.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
For a better understanding of the present invention, embodiments will now be described by way of example, with reference to the accompanying drawings, in which:
Fig. I is a schematic block-diagram showing the configuration of a conventional 3-phase shift register; Fig. 2 is a detailed circuit diagram of each stage in Fig. I Fig. 3 is input/output waveform diagrams of the stage in Fig. 2; Fig. 4 is a detailed circuit diagram of the output part of the stage in Fig. 2; Fig. 5 is a schematic block diagram showing a conventional 4-phase shift register; Fig. 6 is a detailed circuit diagram of an arbitrary stage shown in Fig. 5; Fig. 7 is a waveform diagram of input and output signals in the arbitrary stacre shown in Fig. 6; Fig. 8 is a waveform. diagr4m of an output signal generated in each the stage and voltage signals on the first and second nodes in the simulation of the prior shift register; Fig. 9 is a circuit diagram showing of the confioluration of a shift register stage, 0 ZI -11) 1-7 which is adapted to the shift register in Fig. 5, according to an embodiment of the present invention; Fill). 10 input/output waveform diagrams of the stage in Fig. 9; Filal. 11 is voltaae waveform diagrams showing a variation in voltages at first and second nodes resulting from the presence of the capacitance CL2 in Fig. 9; Fig. 12 is a circuit diagram showing of the configuration of a shift register stage, which is adapted to the shift register in Fig. 5, according to another embodiment of the present invention; Fi l' is a circuit diagram showing of the configuration of a shift register stage, which is adapted to the shift register in Fig. 5, according to still another embodiment of the present invention; Fig. 14 is voltage waveform diagrams showing that a falling time of the output voltage becomes long; Fig. 15 is a block diagram showing schematicafly a configuration of a 4phase shift register according to an emb6diment of the present invention-, Fig. 16 is a circuit diagram showing in detail an embodiment of an arbitrary stage in Fig. 15; Fig. 17 is a waveform diagram of input and output signals in the arbitrary stage shown in Fig. 16; Fig. 18 is a circuit diagram showing in detail another embodiment of an arbitrary stage in Fig. 15-) Fig. 19 is a waveform diagram of an output signal generated in each the stage and voltage signals on the first and second nodes in the simulation of the shift register circuit according to the present invention; and Fig. 20 explains the mobility of major carrier for the threshold voltage of transistor included in each the prior shift register circuit and the shift register circuit according to the present invention.
Refeming to Fig. 9, there is shown a shift register stage, which is adapted to the C, shift reaister in Fig. 5, according to a first embodiment of the present invention. For convenience of explanation, it assumes that the shift reaister sta-e of Fia. 9 is an ith Z.7 Z-7 stage the shift register shown in Fla. 5. As shown in Fla. 9, the shift register stage 12i g 0 0 0 includes a first NIMOS transistor TI connected among a scanning pulse input line 14, a first node P I and a third node P') - a second NTMOS transistor T2 connected among the first node P 1, a second node P2 and a ground voltage line VSSL; a third NNMOS transistor T3) connected between a third clock signal line CLK3 and the second node P2; a fourth NTMOS transistor T4 connected among the second node P2, the third node P3) and the ground voltage line VS SL; a capacitor CAP I connected between the first node P1 and an output fine 14j; a fifth NMOS transistor T5 connected between the first clock signal line CKL I and the output line 14j; and a sixth NMOS transistor T6 connected among the second node P2, the output line 14, and the ground voltage line VSSL.
If a high logic level of (i-I)th row line input signal &-, is applied from the previous stage 12j., to the scanning pulse input line 14j-1, then first and fourth NMOS transistors T I and T4 are turned on. Accordingly, a voltage at the first node P I is changed into a high logic level by the supply voltage VDD applied as the first NMOS transistor TI is turned on, and a voltage at the second node P2 is discharged toward a ground voltage source VSS as the fourth NMOS transistor T4 is turned on. As a result, a low logic level voltage emerges at the second node P2.
As seen from Fig. 10, the third clock signal C3 remains at a low logic level voltage during a time interval when the (i- 1)th row line input signal gi-, has a high logic level voltage. In other words, a high level voltage region of the third clock signal C3 is not overlapped with a high level voltage region of the (i-I)th row line input signal &.,. Accordingly, the third and fourth NMOS transistors T3 and T4 are not turned on simultaneously, so that a voltage at the second 'node P2 is determined independently of a channel width ratio (i.e., resistan.ce ratio) of the third NMOS transistor T3 to the fourth NMOS transistor T4. Accordingly, even when device characteristics of the third and fourth NMOS transistors T3 and T4 are not uniform, a circuit characteristic of the shift register is not changed to such a large extent to make its normal operation 12 impossible. Also, the third and fourth NTMOS transistors T') and T4 are not simultaneously turned on, so that overcurrent does not flow at the third and fourth NMVIOS transistors T3 and T4. As a result, device characteristics of the third and fourth transistors T3 and T4 are not deteriorated and, furthermore, the power consumption is reduced.
If a hiah locic level voltacre appears at the first node P I, then the fifth NTMOS 1.7 17 transistor T5 is turned on. In this state, when the first clock si-nal C I has a hicrh loaic level voltage, the output line 14i begins to reach a high logic level of first clock signal C I via the drain and the source of the fifth NIMO S transistor T5. Accordingly a h g, hig io lo'aic level of output si-nal Vout emerges at the output line 14j. The capacitor CAP I 1P 17 raises a voltage at the first node P I by the voltage level of the first clock signal C I when a high logic level of first clock signal C I is applied to the output line 14j. Since a gate voltage is increased by means of the capacitor CAP I, the fifth NMOS transistor T5 rapidly transfers the high logic.level of first clock signal C I to the output line 14i without any attenuation and with shorter delay. Accordingly, a voltage loss caused by a threshold voltacre of the fifth NMOS transistor T5 is minimized. In tEs embodiment, g the capacitor CAP 1 can be replaced by a parasitic capacitance existing in the fifth NMOS transistor T5.
If the first clock signal C1 changes from a high logic level voltage into a low logic level voltage, then the output signal Vout at the output line 14i also changes from a high logic level voltage into a low logic level voltage. This results from the fifth NMOS transistor T5 being in a turnedon state with the aid of a voltage at the first node P1.
Next, if the third clock signal C3 changes from a low logic level voltage into a high logic level voltage, then the third NMOS transistor T3 is turned on in such a manner that a voltage at the second node P2 has a high logic level. The second NMOS transistor T2 is also turned on with the aid of a high logic level voltage at the second node P2 applied to its gate to thereby discharge a voltage at the first node P I toward the ground voltage source VSS connected to the ground voltage line VSSL. In a similar manner, the sixth NMOS transisto'r T6 also discharges a voltage at the output line 14j, via the ground voltage line VSSL, into the ground voltage source VSS with the aid of a 13 high level volta e at the second node P2 applied to its gate. As a result, both a voltage 9 0 at the first node P 1 and an output signal Vout at the output line 14i have a low logic level voltage. On the other hand, when the first clock signal C I inputted to the drain
of the fifth NTTMOS transistor T5 in such a state that a voltage at the first node P I remains at a high logic level chances from a high logic level voltage into a low logic level voltage, a voltage at the first node PI rises. At this time, a voltage rising width JVp at the first node PI can be established accurately by the capacitor CAP I connected between the first node P I and the output line 14i and a capacitor CL provided between the first node P I and the ground voltage line VSSL. The voltage rising width JVp at the first node P I is as described in the following formula (2):
A.
d VP1 CAP + C"" 14 Vout C Ll + CAP + Cu 15...... (2) wherein Cox represents a parasitic capacitance of the fifth NMOS transistor T5. Preferably, capacitances of the capacitors CAP 1 and CLI are set to about 0. 1 to 10 pF. However, other suitable values may be used. 20 The shift register stage ftirther includes a capacitor CLI connected between the second node P2 and the ground voltage li ne VSSL. The capacitor Crestrains; a voltage variation at the second node P2 when the output signal Vout at the output line 14i changes and a voltage variation at the second node P2 due to a leakage current. Such a restraint of the voltage variation can be seen from voltage waveforms P I and P2 25 at the first and second nodes when the capacitor CLI'S provided and voltage waveforms P I and P2 at the first and second nodes when the capacitor CLI is not provided, as shown in Fig. 11. Referring now to Fig. 12, there is shown each stage of a shift register stage, which is adapted to the shift register in Fig. 5, according to another embodiment of the 30 present invention. The shift register stage 12i will be described with reference to the waveform diagrams in Fig. 10. In Fig. 12, the ith stage 12i includes a first NMOS 14 transistor T I connected between a scanning pulse input line 14, and a first node P I - a second N-MOS transistor T2 connected among the first node P 1, a second node P2 and a ground voltage line VSSL; a third INMOS transistor T31 connected among a supply voltage line VDDL, a third clock signal line CLK3 and the second node P2; a fourth 5 NMOS transistor T4 connected among the first node P 1, the second node P2 and the,ground voltage line VSSL,- a capacitor CAP I connected between the first node P I and an output line 14j; a fifth NMOS transistor T5 connected between the first clock signal 0 line CKL I and the output line 14,; and a sixth NMOS transistor T6 connected among the second node P2, the output line 14, and the ground voltage line VSSL.
If a high logic level of (i-I)th row line input signal gi is applied from the previous stage 12i Z) -, to the scanning pulse input line 14j, then the first N-TMOS transistor T I is turned on to charge a voltage at the first node P I into a high logic level. When the voltage at the first node P1 is charged into a level higher than the threshold voltage, the fourth and fifth NMOS transistors T4 and T5 are turned on. As the fourth NMTOS transistor T4 is turned on, a voltage at the second node P2 is discharged, via the fourth NMOS transistor T4 and the ground voltage line VSSL, toward the ground voltage source VSS. Accordingly, a voltage at the second node P2 is not varied during a time interval when a voltage at the first node P 1 remains at a high logic level (i.e., when the (i- I)th row line input signal &I remains at a high logic level). Further, since a voltage at the second node P2 becomes a low level, the second and sixth NMOS transistors T2 and T6 are turned off. As seen from Fig. 10, the third clock signal C3 remains at a low I evel voltage during a time interval when the (i- I)th row line input signal gi-I has a high logic level voltage, so that a voltage level at the second node P2 is determined independently of a channel width ratio (i.e., resistance ratio) of the third NMOS transistor T') to the fourth NMOS transistor T4. Subsequently, if the first clock signal C I changes from a low logic level voltage into a high logic level voltage, then the output line 14i is charged into a high logic level voltage with the aid of a high logic level of first clock signal C I applied via the drain and the source of the fifth NMOS transistor T5. At this time, the capacitor CAP I bootstraps a voltage at the first node P 1 by a voltage of the first clock signal CI when the high logic level of first clock signal C I is applied to the output line 14',.
Further, if the first clock signal C I transits from a high logic level voltage into a low locic level voltage, the output signal Vout at the output line 14, drops into a low looic level. This results from the fifth N-MOS transistor T5 beinc, in a tumed-on state.
Next, if the third clock signal 0 changes from a low logic level voltage into a high logic level voltage, then the third NMOS transistor T3-) is turned on to charge the second node P2 into a hich locic level voltacye with the aid of a hi-h level of third clock Z= si-nal C'). The second NINMOS transistor T2 also is turned on with the aid of a hich 0 0 lo-ic level voltace at the second node P2 applied to its crate to thereby discharge a voltage at the first node PI toward the ground voltage source VSS connected to the ground voltage line VSSL. In a similar manner, the sixth NTMOS transistor T6 also discharges an output signal Vout at the output line 14j, via the ground voltage line VSSL, into the ground voltage source VSS with the aid of a high logic level voltage at the second node P2 applied to its crate. As a result, both a voltage at the first node P I and an output' signal Vout at the output line 14i have a low logic level.
Referring to Fig. I"), there is shown a shift register stage, which is adapted to the shift register in Fig. 5, according to still another embodiment of the present invention. The shift register stage of Fig. 13 will be described with reference to the waveform diagrams in Fig. 10. In Fig. 13, the ith shift register stage 12i includes a first NMOS transistor T1 connected between a scanning pulse input line 14j., and a first node P 1; a second NTMO S transistor T2 connected among the first node P 1, a second node P2 and a ground voltage line VSSL; a third NMOS transistor T3 connected among a supply voltage line VDDL, a third clock signal line CLK3 and the second node P2; a fourth NMOS transistor T4 connected among the first NMO S transistor T 1, the second node P2 and the ground voltage line VSSL; a capacitor CAP I connected between the first node P I and an output line 14j; a fifth NMOS transistor T5 connected between the first clock signal line CKL I and the output line 14j; a sixth NMOS transistor T6 connected among the second node P2, the output line 14i and the ground voltage line VSSL,- and a seventh NMOS transistor T7 connected between the output line 14i and the ground voltage line VSSL.
If a high level of (i- I)th row' line input signal &-, is applied from the previous stage 12i-l to the scanning pulse input line l4j, then first NMO S transistors T 1 is 16 turned on to charge a voltage at the first node P I into a high logic level. The fourth g -D W-,OS transistor T4 also is turned on with the aid of a high level of row line input signal g,-,, a voltage at the second node P2 is discharged, via the ground voltage line VSSL, toward the ground voltage source VSS. Accordingly, a voltage at the second node P2 is not varied by the fourth NNTMOS transistor T4 during a time interval when a voltage at the first node P I remains at a high level. Such a voltage level at the second node P2 is deternu'ned independently of a channel width ratio (i.e., resistance ratio) of the third NMOS transistor T3 to the fourth NMOS transistor T4 because the third clock signal C'-) has a low logic level voltage in a high logic level voltage region of the (i- l)th 0 0 row line input signal a 0 Also, since a voltage at the second node P2 remains at a low logic level during a time interval from when the fourth NMMOS transistor T4 is turned on until the third transistor T3 is turned on, the second and sixth NMOS transistors T2 and T6 are turned off.
If the first clock signal C I changes from a low logic level voltage into a high logic level voltage, then the output line 14i is charged into a high logic level voltage with the aid of a high logic level of first clock signal C I applied via the drain and the source of the fifth NMOS transistor T5. The capacitor CAP I raises a voltage at the first node P I by a voltage level of the first clock signal C I when a high logic level of first clock signal C I is applied to the output line 14j.
Further, if the first clock signal C I transits from a high logic level voltage into a low logic level voltage, the output signal Vout at the output line 14i changes into a low logic level. This results from the fifth NMOS transistor T5 being in a turned-on state.
In addition, the seventh NMOS transistor T5 is turned on with the aid of a high logic level voltage of feedback signal Vf from the next stage 12jj, thereby discharging the output signal Vout at the output line 14j, via the ground voltage line VSSL, into the ground voltage source VSS rapidly, Accordingly, a long falling time of the output signal Vout is shortened as shown in Fig. 14. The increased falling time of the output signal Vout is caused by a fact that the channel width of the fifth NMOS transistor T5 becomes narrow slowly as a voltage at the first node P I decreases slowly. In other words, since a discharge path provided by the fifth NMOS transistor T5 becomes narrow slowly, a falling time of the output signal Vout is lengthened. A new discharge -17 path from the seventh NIMOS transistor T7 is provided in addition to the discharge path from the fifth NMOS transistor T5, so that the output voltage Vout at the output line 14i is rapidly discharged. As a result, a falling time of the output signal Vout is shortened.
Fig. 15 illustrates a shift register accordinc, to an embodiment of the present invention. The shift register of Fig. 15 includes n stages 22, to 22, cascade-connected to a start pulse input line. The n stages 22, to 22, each is connected to the 3 clock signal lines among 4 phase clock signal lines CKL I to CKL4. Each output line 24, to 24. of the n stage 22, to 22,, shown in Fig. 15 is connected to row lines ROWI to ROWn in an array of picture elements (or pixels). The first to fourth clock signals C I to C4 on the 4 phase clock signal lines CKLI. to CKL4 each has a period corresponding to 4 horizontal scanning intervals and a phase shifted sequentially by one horizontal scanning interval. The second to nth stages 22., to 22,, each receives 3 clock signals having the phases delayed by one horizontal scanning interval relative to the 3 clock signals applied to the previous stage 22, to 22.
0 -,. For example, if the first stage 22, receives the first, third and fourth clock signals CI, C3 and C4, the second stage 22, inputs the second, fourth and first clock signals C2, C4 and CI having the phases delayed from the first, third and fourth clock signals CI, C3 and C4 by one horizontal scanning interval. Similarly, each third to nth stages 223 to 22. receives 3 clock signals having the phases delayed from the 3 clock signals applied to the previous stage 22.2 to22,,., by one horizontal scanning interval. When a start pulse SP is applied to the first stage 221, the first to nth stages shift the start pulse SP to enable sequentially the output lines 24, to 24. of the first to nth stacres 22, to 22, The output signals g, to g, of the first to (n-I)th stages 22, to 22.
-, are then applied to next stages 22, to22" as a start pulse SP. To this end, the n row lines ROWI to ROWn connected to the output lines 24 to 24,, of the n stages 22, to 22,, is sequentially driven. The n stages 22, to 22. are driven in the same manner. For the convenience of description, it will be explained in detail an arbitrary stage 22i receiving the first, third and fourth clock signals C1, C3 and C4, as an example of the n stages 22, to 22 Fig. 16 depicts in detail the configuration of an arbitrary stage 22i included in the shift register shown in Fig. 15. The arbitrary stage 22i of Fig. 16 includes first and 18 second 'TN'MOS transistors TI and T2 connected between an output line 24i of a previous stage 22,., and a first node P I, third and fourth NMOS transistors T3 and T4 connected between a third clock sianal line CY.L_') and a second node P2, and fifth and sixth NNTMOS transistors T5 and T6 connected between the first node P1 and a ground Z.
voltage line VSSL, and seventh and eighth NMOS transistors T7 and T8 connected between the second node P2 and the ground voltage line VSSL. The gates of the first and second NMOS transistors TI and T2 are commonly connected to a fourth clock sianal line CKL4. The oates of the third and fourth NMOS transistors T_') and T4 are 12 0 commonly connected to the third clock signal line CKL3. The fifth and sixth NMOS transistors T5 and T6 have gate electrodes connected commonly to the second node P2, respectively. The seventh and eighth NMOS transistors T7 and T8 each has a gate electrode connected to the output line 24j_j of the previous stage 22j, The arbitrary stage 22i further comprises a ninth NMOS transistor T9 connected between a first clock sional line CYJ, 1, the first node P 1 and an output line 24i and a tenth NMOS transistor TIO connected between the output line 24j, the second node P2 and the ground voltage line VSSL.
The stage 22i as shown in Fig. 16 has a range of operating voltage wider than that of the stage shown in Fig. 6 by decreasing the leakage current. The leakage current is reduced due to the NMOS transistors being connected to the first and second nodes PI and P2 in a multi-gate structure. Also, the gate electrodes of the first and second NMOS transistors TI and T2 are commonly connected to the output line 24j, of the previous stage 22,_j, thereby minimizing the decrease of potential charged on the first node P I in the case that the output signal &-, of the previous stage 22j., becomes to be low. Further, since the gate electrodes of the third and fourth NMOS transistors T3 and T4 is commonly connected to the drain electrode of the third NMOS transistor T3, it eliminates a high level voltage VDD from in the arbitrary stage 22 10 as in Fic. 6. Such a stage 22j., as shown in Fig. 16 will be described with reference to a waveform diagram of Fig. 17, Firstly, during the interval of tl, the output signal gi having a high logic level is applied from the previous stage 22j, to the drain electrode of the first NMOS transistor T I as the start pulse, and the fourth clock signal C4 on the fourth clock signal -19 line CKL4 is supplied to the -ate electrodes of the first and second NMOS transistor TI and T2. All the first clock sianal C1 on the first clock sianal line CKLI and the third clock signal 0 on the third clock signal line CYL3) have the low logic level. In this case, the first and second NNIOS transistors TI and T2 are turned-on by the fourth clock signal C4 having, the high logic level, and the seventh and eighth NMOS transistors T7 and T8 depending on the output signal g,-, of the previous stage 22, are also turned-on. To this end, the first node P1 charges a voltage applied from the output line 24j, of the previous stage 22i gb the first and second NTMOS 0 -, throu transistors TI and T2 to have the high logic level, thereby turning-on the ninth NTMOS transistor T9. At this time, the output voltage signal Vout on the output line 24i goes to the low logic level because the first clock signal C I applied to the drain electrode of the ninth NMOS transistor T9 has the low logic level. Next, at the interval of t2, the output signal gi 0 1 -, of the previous stage 22j_j and the fourth clock signal C4 are inverted into the low logic level, while the first clock signal C1 becomes the high logic level.
The first clock signal C1 having the high logic level is applied to the output line 24i through the ninth NMOS transistor T9 which is turried-on by the high logic level on the first node P1, thereby producing the high logic level on the output line 24,. The voltage signal VP 1 on the first node P I is then bootstrapped to the higher logic level by the coupling effect of a parasitic capacitor between the gate and source electrodes of the ninth NMOS transistor T9. If the first clock signal Cl is transited to the low logic level during the interval of t3, the output voltage signal Vout on the output line 24i has the low logic level since the ninth NMOS transistor T9 is in the turning-on. Then, the voltage signal is dropped down to a middle level due to turning-off of the first and second NMOS transistors TI and T2. Finally, the third clock signal C3 having the high logic level is applied to the drain electrode of the third NMOS transistor T3 and the gate electrodes of the third and fourth NMOS transistors T-3) and T4 during the interval of 0. The second node P2 is then charged by the third clock signal C3 having the high logic level from the third clock signal line CKU through the third and fourth NMOS transistors T3 and T4 to generate a voltage signal VP2 having the high logic level. The tenth NMOS transistor TIO is turried-on by the voltage signal VP2 of the high logic level from the second node P2 such that the output voltage signal Vout on the output line 24, maintains the low logic level. The fifth and sixth NMOS transistors T5 and T6 are also turned-on by the voltage signal VP2 charged at the second node P2, thereby allowing the voltage signal VP1 on the first node PI to be discharged to the ground voltage source VSS through the fifth and sixth NTMOS transistors T5 and T6 and the ground voltage line VSSL.
As described above, each stage of the shift register circuit according to an embodiment of the present invention shifts the start pulse to its output line 24i every horizontal scanning period. To this end, the n output lines 24, to 24i of the shift register circuit is sequentially enabled and furthermore the n row lines ROWI to ROWn included in the array of the picture elements are sequentially driven.
Fig. 18 illustrates in detail a circuit configuration of another embodiment of the arbitrary stag e 22, shown in Fig. 15. The arbitrary stage 22i of Fig. 18 has a similar circuit configuration as the arbitrary stage 22i shown in Fig. 16. One difference is that the oate electrode of the second NMOS transistor T2 is connected to the fourth clock signal line CKL4, and the drain and gate electrodes of the first NMOS transistor T I are commonly connected to the output line of the previous stage 22,_I.
Fig. 19 explains a resultant of a simulation for the shift register circuit according to the embodiments which includes NMOS transistors having the low absolute threshold voltage I VthL In Fig. 19, VP1 and VP2 are waveforms of the voltage signals on the first and second nodes P 1 and P2, and Vout represents the output voltage signal on the output line 24, of the present stage, i.e., the arbitrary stage. Fig. 19 represents that the voltage signals VP1 and VP2 on the first and second nodes PI and P2 are stable. This results from that the currents leaked from the first and second nodes PI and P2 are reduced by means of the NMOS transistors which are connected to the first and second nodes P1 and P2 in the multi-gate structure. To this end, the output voltage signal Vout charged on the output line 24i becomes stable and the shift register circuit can be stabbly driven.
Fig. 20 is a graph comparing the mobility of major carrier for the threshold voltage of transistor in the prior shift circuit and that in the shift register circuit according to the present invention circuit. In Fig. 20, a first voltage range _3)0 represents the range of the operating voltage of the prior shift register circuit and a 21 second voltage range 32 indicates the range of the operating voltage of the shift rem-ster circuit according to the embodiments. The first voltage range 30 occupies the 11 1_ ZP region proceeding from the voltage level of about 2V to the voltage level of about 7V, I I while the second voltage range 32 occupies the re 'on proceeding from the voltage 1., 0 91 0 11 level of about OV to the voltage level of about 6.5V. Consequently, the shift register 0 circuit accordinc, to the embodiments has the ranae of the operating voltage wider than M 17 17 that of the prior shift register circuit by the region corresponding to the voltage level of 1.5V.
As described above, the shift register according to the embodiments drives stages sequentially by utilizing, four clock signals, and allows each stage to be configured irrespective of the size of transistors. Accordingly, in the shift register, a change in a circuit characteristic caused by a variation in a device drift and a threshold voltage, etc. can be minimized. As a result, a current flows only during a transition interval of signal, so that the power consumption is reduced, and also a deterioration in a device characteristic caused by overcurrent is restrained. Furthermore, in the shift register a separate capacitor is provided between the output node and the bootstrap node and a capacitor is provided between the direct current source and the bootstrap node, so that a voltage variation at the bootstrap node can be restrained. As a result, the shift register can be operated stably.
In the shift register according to the embodiments, NMOS transistors are connected to the first and second nodes P 1 and P2 in the multi-gate structure so that the currents leaked from the first and second nodes P I and P2 are reduced. To this end, the shift register is stabbly driven, and furthermore the range of operating voltage is w'der. Also, in the shift register according to the embodiments, the gate electrodes of first and second NMOS transistors T I and T2 are connected to different clock signal lines, respectively, thereby minimizing the decrease of a potential charged on the first node P I although the output signal of the previous stage is dropped down. Further, the shift register according to the present invention can eliminate a line for supplying a high level voltage.
Although the present invention has been explained by the embodiments shown 22 in the drawings described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the 5 appended claims and their equivalents.
23

Claims (37)

  1. Claims:
    I. A shift register having a plurality of stages which are connected to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator, wherein the stages are connected to corresponding row lines and are connected in cascade with respect to a scanning signal for charging and discharging the row lines, each one of the stages comprising:
    output circuit device including a pull-up transistor and a pull-down transistor, said pull-up transistor having a first input electrode responsive to a first clock signal having a delayed phase in comparison to the scanning signal, a first output electrode connected to the row line, and a first control electrode; said pull-down transistor having a second input electrode connected to the low level voltage source, a second output electrode connected to the row line.- and a second control electrode; input circuit device responsive to the scanning signal for generating a first control signal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the first clock signal for generating a second control signal to be applied to the second control electrode; and means for raising a voltage of the first control signal.
  2. 2. The shift register of claim 1, wherein the input circuit device comprises:
    a first transistor having a third input electrode responsive to the scanning signal, a third output electrode connected to the first control 'electrode, and a third control electrode connected to the third input electrode; and a second transistor having a fourth input electrode connected to the low level voltage source, a fourth output electrode connected to the first control electrode, and a fourth control electrode connected to the second control electrode.
    24
  3. 3. The shift register of claim 2, wherein the input circuit device further comprises: a third transistor having a fifth input electrode connected to the h1ah level voltage source, a fifth output electrode connected to the second control electrode, and a fifth control electrode responsive to the second clock signal; and a fourth transistor having a sixth input electrode connected to the low level voltacre source, a sixth output electrode connected to the second control electrode, and g a sixth control electrode responsive to the scanning signal.
    0 1=1
  4. 4. The shift register of claim 1, 2 or 3, wherein the voltage raising means includes a first capacitor connected to the row line and the first control electrode.
  5. 5. The shift register of claim 1, 2, 3 or 4, further comprising:
    a second capacitor connedted between the first control electrode and the low level voltage source; and a third capacitor connected between the second control electrode and the low level voltage source.
  6. 6. A shift register having a plurality of stages which are connected to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator, wherein the stages are connected to corresponding row lines and are connected in cascade with respect to a scanning signal for charging and discharging the row lines, each one of the stages comprising:
    output circuit means including a pull-up transistor and a pull-down transistor, said pull-up transistor having a first input electrode responsive to a first clock signal having a delayed phase in comparison to the scanning signal, a first output electrode connected to the row line, and a first control electrode; said pull-down transistor having a second input electrode connected to the low level voltage source, a second output electrode connected to the row line, and a second control electrode, input circuit means being responsive to the scanning signal for generating a first control si-nal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the first clock signal for 0 11;1 10 generatina a second control signal to be applied to the second control electrode; means for raising a voltaae of the first control signal; and means for discharging the second control signal duning a time interval when the 0 0 first control signal is enabled.
  7. 7. The shift register of claim 6, wherein the input circuit means comprises:
    a first transistor having a third input electrode responsive to the scanning signal, a third output electrode connected to the first control electrode, and a third control electrode connected to the third input electrode; and a second transistor having a fourth input electrode connected to the low level voltage source, a fourth output electrode connected to the first control electrode, and a fourth control electrode connected to the second control electrode.
  8. 8. The shift register of claim 7, wherein the input circuit means further comprises:
    a third transistor having a fifth input electrode connected to the high level voltage source, a fifth output electrode connected to the second control electrode, and a fifth control electrode responsive to the second clock signal.
  9. 9. The shift register of claim 6, 7 or 8, wherein the voltage raising means includes a capacitor connected to the row line and the first control electrode.
  10. 10. The shift register of claim 6, 7, 8 or 9, wherein the discharging means includes a fourth transistor having a sixth input electrode connected to the low level voltage source, a sixth output electrode connected to the second control electrode, and! a sixth control electrode connected to the first control electrode.:! 26
  11. 11. A shift register having a plurality of stages which are connected to a high level voltage source, a low level voltage source and a phase- delayed clock signal generator, wherein the staaes are connected to corresponding row lines, and are connected in cascade with respect to a scanning signal for charging and discharging, the row lines, each one of the stages comprising: output circuit device including a pull-up transistor and a pull-down transistor, sid pull-up transistor having a first input electrode for receiving a first clock signal al I having a delayed phase in comparison to the scanning signal, a first output electrode connected to the row line, and a first control electrode; said pull-down transistor having a second input electrode connected to the low level voltage source, a second output electrode connected to the row line, and a second control electrode-, input circuit device being responsive to the scanning signal for generating a first control signal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the first clock signal for generating a second control signal'to be applied to the second control electrode; means for raising a voltage of the first control signal; and means for accelerating g a discharging speed at the row line.
  12. 12. The shift register of claim 11, wherein the input circuit device comprises:
    a first transistor having a third input electrode responsive the scanning signal, a third output electrode connected to the first control electrode, and a third control electrode connected to the third input electrode; and a second transistor having a fourth input electrode connected to the low level voltage source, a fourth output electrode connected to the first control electrode, and a fourth control electrode connected to the second control electrode.
  13. 13. The shift register of claim 12, wherein the input circuit device further comprises:
    a third transistor having a fifth input electrode connected to the high level voltage source, a fifth output electrode connected to the second control electrode, and a 27 fifth control electrode responsive to the second clock signal; and a fourth transistor having a sixth input electrode connected to the low level voltage source, a sixth output electrode connected to the second control electrode, and a sixth control electrode responsive to the scanning signal.
  14. 14. The shift register of claim 11, 12 or 13, wherein the voltage raisina, means includes a capacitor connected to the row line and the first control electrode.
  15. 15. The shift register of claim 11, 12, 13 or 14, wherein the accelerating means includes a fifth transistor having a seventh input electrode connected to the low level voltage source, a seventh output electrode connected to the row line, and a C seventh control electrode for responding a signal from the output line of the next stage.
  16. 16. A shift register for driving gate lines of liquid crystal display and responsive to a scanning signal, a first voltage source and second voltage source, the shift register comprising:
    a plurality of stages, each stage comprising output circuit device including a pull-up transistor and a pull-down transistor, said puH-up transistor having a first control electrode, a first input electrode coupled to a first clock signal having a delayed phase in comparison to the scanning signal and a first output electrode connected to the gate line; said pull- down transistor having a second control electrode, a second input electrode coupled to the second voltage source and a second output electrode connected to the gate line-, input circuit device responsive to the scanning signal for generating a first control signal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the first clock signal for generating a second control signal. to be applied to the second control electrode; and a voltage controller coupled between the first control electrode and gate line for raising a voltage of the first control signal.
  17. 17. The shift register of claim 16, wherein the input circuit device comprises:
    28 a first transistor having a third input electrode responsive to the scanning signal, a third output electrode connected to the first control electrode, and a third control electrode connected to the third input electrode; and a second transistor having a fourth input electrode connected to the second voltage source, a fourth output electrode connected to the first control electrode, and a fourth control electrode connected to the second control electrode.
  18. 18. The shift register of claim 17, wherein the input circuit device further comprises:
    a third transistor having a fifth input electrode connected to the first voltage source, a fifth output electrode connected to the second control electrode, and a fifth control electrode responsive to the second clock signal; and a fourth transistor having a sixth input electrode connected to the second voltage source, a sixth output electrode connected to the second control electrode, and a sixth control electrode responsive to the scanning signal.
  19. 19. The shift register of claim 16, 17 or 18, wherein the voltage controller includes a first capacitor.
  20. 20. The shift register of claim 16, 17, 18 or 19, further comprising:
    a second capacitor connected between the first control electrode and the second voltage source; and a third capacitor connected between the second control electrode and the second voltage source.
  21. 21. A shift register for driving gate lines of liquid crystal display and responsive to a scanning signal, a first voltage source and second voltage source, the shift register comprising a plurality of stages, each stage comprising output circuit device including a pull-up transistor and a pull-down transistor, said pull-up transistor having a first control electrode, a first input electrode 29 coupled to a first clock signal having a delayed phase in comparison to the scanning signal and a first output electrode connected to the -ate line; said pull- down transistor having a second control electrode, a second input electrode coupled to the second volta-e source and a second output electrode connected to the gate line; input circuit device responsive to the scanning signal for generating a . 17 0 0 first control sional to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the first clock signal for C, generating a second control signal to be applied to the second control electrode; a voltage controller coupled between the first control electrode and gate line for raisin a voltaae of the first control signal; and 9 0 a discharging device responsive to the first control signal to discharge the second control.
  22. 22. The shift register of claim 21, wherein the input circuit device comprises:
    a first transistor having a third input electrode responsive to the scanning signal, a third output electrode connected to the first control electrode, and a third control electrode connected to the third input electrode; and a second transistor having a fourth input electrode connected to the second voltage source, a fourth output electrode connected to the first control electrode, and a fourth control electrode connected to the second control electrode.
  23. 23). The shift register of claim 22, wherein the input circuit device further comprises: a third transistor having a fifth input electrode connected to the first voltage source, a fifth output electrode connected to the second control electrode, and a fifth control electrode responsive to the second clock signal.
  24. 24 The shift register of claim 21, 22 or 23, wherein the voltage controller includes a capacitor.
  25. 25. The shift register of claim 21, 22, 23 or 24, wherein the discharging device includes a fourth transistor having a sixth input electrode connected to the second voltage source, 0 a sixth output electrode connected to the second control electrode, and a sixth control electrode connected to the first control electrode.
  26. 26. A shift register for driving gate lines of liquid crystal display and responsive to a scanning signal, a first voltage source and second voltage source, the shift register comprising:
    a plurality of stages, each stage comprising output circuit device including a pull-up transistor and a pull-down transistor, said pull-up transistor having a first control electrode, a first input electrode coupled to a first clock signal having a delayed phase in comparison to the scanning signal and a first output electrode connected to the gate line; said pull- down transistor having a second control electrode, a second input electrode coupled to the second voltage source and a second output electrode connected to the gate line; input circuit device responsive to the scanning signal for generating a first control signal to be applied to the first control electrode, and responsive to a second clock sianal h ing a delayed phase in comparison to the first clock signal for 0 av generating a second control signal to be applied to the second control electrode-, a voltage controller coupled between the first control electrode and gate line for raising a voltage of the first control signal a first discharging device responsive to the scanning signal to discharge the second control; and a second discharging device coupled the gate line.
  27. 27. The shift register of claim 26, wherein the input circuit device comprises:
    a first transistor having a third input electrode responsive the scanning signal, a third output electrode connected to the first control electrode, and a third control electrode connected to the third input electrode; and a second transistor havincy a fourth input electrode connected to the second voltage source, a fourth output electrode connected to the first control electrode, and a fourth control electrode connected to the second control electrode.
  28. 28. The shift register of claim 27, wherein the input circuit device further comprises: a third transistor having a fifth input electrode connected to the first voltage source, a fifth output electrode connected to the second control electrode, and a fifth control electrode responsive to the second clock sional; and a fourth transistor having a sixth input electrode connected to the second voltage source, a sixth output electrode connected to the second control electrode, and a sixth control electrode responsive to the scanning signal.
    0 0
  29. 29. The shift register of claim 26, 27 or 28, wherein the voltage control includes a capacitor.
  30. 30. The shift register of claim 26, 27, 28 or 29, wherein the second discharging device includes a fifth transistor having a seventh input electrode connected to the second voltage source, a seventh output electrode connected to the gate line, and a seventh control electrode responsive to a signal from the output line of the next stage of the shift register.
  31. 31. A shift register circuit comprising a plurality of cascaded stages connected to a start pulse input line and driving sequentially a plurality of row lines, each of the stages having an input terminal, an output terminal, a low level voltage line and first to third clock signal lines, the input terminal receiving an output signal of a previous stage, the output terminal being connected to a row line, each one of the stages comprising:
    a pull-up transistor having a conduction path connected between the first clock signal line and the output terminal and a control electrode; a pull-down transistor having a conduction path connected between the low level voltage line and the output terminal and a control electrode-, first and second transistors having conduction paths connected in series between the input terminal and the control electrode of the pull-up transistor and control electrodes connected commonly to the second clock signal line, respectively, the first and second transistors allowing a voltage to be charged on the control 32 electrode of the pull-up transistor; and third and fourth transistors having conduction paths connected in series between the third clock signal line and the control electrode of the pull-down transistor and control electrodes connected commonly to the third clock signal line, respectively, the third and fourth transistors allowing a voltage to be charced on the control electrode of 0 ZIP the pull-down transistor.
  32. 32. The shift register of claim 31, wherein each one of the stages further includes:
    fifth and sixth transistors having respectively conduction paths connected in series between the control electrode of the pull-up transistor and the low level voltage line and control electrodes connected commonly to the control electrode of the pulldown transistor, the first and second transistors allowing a voltage charged on the control electrode of the pull-up transistor to be discharged; and seventh and ei-hth transistors having respectively conduction paths connected in series between the control electrode of the pull-down transistor and the input terminal and control electrodes connected commonly to the input terminal, the seventh and eighth transistors allowing a voltage charged on the control electrode of the pull-up transistor to be discharged.
  33. 33. The shift register of claim 31 or 32, wherein the start pulse on the input terminal and a second clock signal on the second clock signal line is simultaneously enabled and a first clock signal on the first clock signal line is enabled in the state that a high logic level is charged on the control electrode of the pull-up transistor charges responding to the start pulse on the input terminal and the second clock signal.
  34. 34. A shift register including a plurality of cascaded stages connected to a 0 start pulse input line and driving sequentially a plurality of row lines, each of the stages having an input terminal, an output terminal, a low level voltage line and first to third clock signal lines, the input terminal receiving an output signal of a previous stage, the output terminal being connected to a row line, each one of the stages comprising:
    33 a pull-up transistor having a conduction path connected between the first clock sional line and the output terminal and a control electrode; a pull-down transistor having a conduction path connected between the low level voltage line and the output terminal and a control electrode; first and second transistors having respectively conduction paths connected in series between the input terminal and the control electrode of the pullup transistor and control electrodes connected independently to the input terminal and the second clock sicrnal line, the first and second transistors allowing a voltage to be charged on the control electrode of the pull-up transistor; and third and fourth transistors having conduction paths connected in series between the third clock signal line and the control electrode of the pull-down transistor and control electrodes connected commonly to the third clock signal line, respectively, the third and fourth transistors allowincy a voltage to be charged on the control electrode of the pull-down transistor.
  35. 35. The shift register of claim 34, wherein each one of the stages further Z.
    includes:
    fifth and sixth transistors having respectively conduction paths connected in series between the control electrode of the pull-up transistor and the low level voltage line and control electrodes connected commonly to the control electrode of the pull down transistor, the first and second transistors allowing a voltage charged on the control electiode of the pull-up transistor to be discharged-, and seventh and eighth transistors having respectively conduction paths connected in series between the control electrode of the pull-down transistor and the input terminal and control electrodes connected commonly to the input terminal, the seventh and eighth transistors allowing a voltage charged on the control electrode of the pull-up transistor to be discharged.
  36. 36. The shift register of claim 34 or 35, wherein the start pulse on the input terminal and a second clock signal on the second clock signal line is simultaneously.
    enabled and a first clock signal on the first clock signal line is enabled in the state that 34 a high logic level is charged on the control electrode of the pull-up transistor charges 0 responding to the start pulse on the input terminal and the second clock signal. 5
  37. 37. A shift recuster substantially as hereinbefore described with reference to Cr and/or substantially as illustrated in any one of or any combination of Figs. 9 to 20.
GB9924976A 1998-10-21 1999-10-21 Shift register Expired - Lifetime GB2343068B (en)

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KR1019980044180A KR100281336B1 (en) 1998-10-21 1998-10-21 Shift register circuit
KR10-1999-0004372A KR100438525B1 (en) 1999-02-09 1999-02-09 Shift Register Circuit

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GB2343068B (en) 2000-12-13
GB9924976D0 (en) 1999-12-22
FR2787913A1 (en) 2000-06-30
JP2000155550A (en) 2000-06-06
DE19950860B4 (en) 2009-08-27
FR2787913B1 (en) 2004-08-27
JP4181710B2 (en) 2008-11-19

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