JPH0887897A - Shift register and scan register - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a shift-register and a scan-register, by which excess stress is not applied to a switch-transistor, by applying bias while exceeding one clock period for a vertical interval period. SOLUTION: In a shift-register 100, stages n-1, (n), n+1 and n+2 are cascade- connected mutually. An output signal from a certain specific stage is coupled with an input to the stage continuing to an immediately succeeding section in the chain. A signal OUTn-1 . appears at the input terminal 12 of the stage (n). The signal OUTn-1 at a high level is bonded with a terminal 18a through a transistor 18 operated as a switch, and a control signal P1 appears. The high-level signal P1 is stored temporarily in capacitance between electrodes and a capacitor CB. The signal P1 appearing in the gate of an output transistor 16 brings the transistor 16 to a conductive state. Since bias is applied while exceeding one clock at a vertical interval, however, no stress is applied.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention is generally
More specifically, the present invention relates to a shift register stage that can be used as a select line scanner for liquid crystal displays.

The description of the present specification is based on US patent application Ser. No. 08 / 288,793 (1), which is the basis of priority of the present application.
(August 12, 994 application), and the description of the specification of the US patent application constitutes a part of the present specification by referring to the number of the US patent application. I shall.

[0003]

2. Description of the Related Art Liquid crystal televisions and computers
Displays (LCDs) are known in the art. This type of display is described, for example, in US Pat.
Nos. 2,346 and 4,766,430 (GG Gillette et al., Granted on May 3, 1988 and August 23, 1988, respectively)
It is described in. Displays of the type described in these patents consist of a matrix of liquid crystal cells arranged at the crossovers of data lines and select lines. The selection lines are sequentially selected by the selection line scanner to output the horizontal lines of the display. The data lines apply luminance (grayscale) signals to the columns of the liquid crystal cells when the select lines are sequentially selected.

Since the drive circuit drives the selected line scanner, and the selected line scanner selects the horizontal line to be displayed, the drive circuit is manufactured directly on the same substrate as the liquid crystal cell, and at the same time when the liquid crystal cell is manufactured. Preferably. Also, because a television or computer display requires a large number of data lines and select lines, and the narrowed pixel pitch limits the space available when laying out the drive circuitry, It is desirable to keep the circuit as simple as possible.

FIG. 1 shows US Pat. No. 5,222,082 (D.Plus,
FIG. 6 shows an example of a known scan register described in the patent granted on Jun. 22, 1993), which scan register is integrated with a liquid crystal display device.
This register is driven by multi-phase clocking signals C1, C2, C3 and each different clock phase is applied to each different scan register stage 11.

FIG. 2 shows one of the scan register stages.
It is a detailed view showing one. This scan register stage has an input section that includes transistors 18 and 19,
It consists of an intermediate section containing transistors 20 and 21 and an output section containing transistors 16 and 17.

The output section is a push-pull amplifier.
(push-pull amplifier), and the clock operation power supply is connected to the power supply connection line 14. The output is taken from the connection between transistors 16 and 17.

The input section is a switching amplifier (swi
It is configured as a tched amplifier), shows a predetermined potential during the clock phase period, and is applied to the power supply terminal of the output section. The input stage output signal P1 is coupled to drive the output transistor 16. Specifically, the output P1 appears following the input signal applied to the gate electrode of the transistor 18. The output of the input section goes high when the clock phase applied to terminal 14 goes high and a high level appears at output terminal 13. The high level appearing at node P1 remains high at node P1 until clock phase C3 appears and the input signal goes low. Therefore, the gate of the output transistor 16 goes high when the clock C1 goes high, providing a charging path to the output 13. When clock C1 goes low,
A path is provided to discharge the output node 13.

The middle section is configured as a clocked inverting amplifier and operates by receiving an input signal. The output of the intermediate stage is the pull-down transistor (pull down t
ransistor) 17 gate electrode. The intermediate stage is pull-up transistor 20 and pull-down
The transistor 21 is included. Since the conductance of transistor 21 is greater than that of transistor 20, when both transistors 20 and 21 are conducting at the same time, the output potential at node P2 remains low.
Therefore, if the clock applied to transistor 20 is high and the input signal is then high, then output transistor 17 remains non-conductive. However, since this stage is applied as a scan register, the frequency of appearance of input signal pulses is relatively low. As a result, node P2 is typically charged high during each clock pulse of clock phase C3, and output transistor 17 is typically conducting.

[0010]

Transistors 18 and 2
A relatively positive bias voltage of about 16 volts is applied to the 0 drain. Therefore, node P2 is typically biased at about 16 volts. As a result, excess stress is applied to the gate electrodes of the transistors 19 and 17, which causes the respective threshold voltages to increase significantly over time. As the threshold voltage of transistor 19 increases, the ability to discharge node P1 decreases, thus increasing the time required to turn off transistor 16. As a result, some of the clock C1 voltage may leak to the output node 13, which not only undesirably affects subsequent register stages, but also causes the pixel row of the LCD to be incorrectly addressed. .

In view of the above, it is desirable that the shift
To reduce the excess stress applied to the gate electrodes of the transistors in the register by reducing the total number of transistors used in each stage of the shift register to, for example, four.

[0012]

A shift register embodying the present invention comprises a circuit for generating a phase-shifted clock signal and a plurality of cascaded stages.
Certain of the cascaded stages include an output transistor that outputs an output pulse from the output of the stage in response to a first clock signal of the clock signals. This particular stage includes an input switching circuit which responds to an output pulse appearing on the output side of the next stage of the cascaded stages when a clock signal whose phase is shifted with respect to the first clock signal appears. The control signal output from the input switching circuit is stored in the capacitance.
This capacitance is coupled to the control electrode of the output transistor. This control signal causes the output transistor to generate the output pulse of the particular stage when the first clock signal appears. The clamping transistor, whose conduction path is connected to the control electrode of the output transistor, appears on the output side of a particular stage of the cascaded stage when a clock signal whose phase is shifted with respect to the first clock signal appears. Respond to the output pulse. The clamping transistor clamps the control signal to a level that inhibits the output transistor from producing an output pulse when the next following pulse of the first clock signal appears. After the signal is clamped, the clamping
The transistor produces an impedance at the control electrode of the output transistor. This impedance is substantially higher than when the signal was clamped.

[0013]

FIG. 3 is an example of the present invention and shows an example of stage n of shift register 100 of FIG. Similar symbols and numerals in FIGS. 3 and 4 indicate similar items or functions.

In the shift register 100 of FIG. 4,
The stages n-1, n, n + 1 and n + 2 are cascaded with each other. The output signal of a particular stage is coupled to the input of the immediately following stage in its chain. For example, the output pulse OUT _n-1 of the preceding stage n-1 in the chain of the register 100.
Is coupled to the input terminal 12 of stage n of FIG.
In the example shown, the stages are n-1, n, n + 1 and n.
Although only four +2 are shown, the total number of stages n in the chain of registers is actually higher. Clock generator 101 of FIG. 4 outputs a three-phase clock signal, that is, clock signals C1, C2 and C3 having the waveforms shown in FIG. Similar symbols and numerals in FIGS. 3-5 indicate similar items or functions.

The pulse of the signal OUT _{n-1 in} FIG. 5 is output when the pulse of the clock signal C3 is applied to the stage n-1. The signal OUT _{n-1 in} FIG. 3 appears at the input terminal 12 of stage n. Signal OUT at HIGH level
_n-1 is coupled to the terminal 18a via the transistor 18 acting as a switch, where the control signal P1 appears. The HIGH level signal P1 is temporarily stored in the interelectrode capacitance (not shown) and the capacitor CB.
The signal P1 appearing at the gate of the output transistor 16 in FIG.
Makes the output transistor 16 conductive. When the clock signal C1 shown in FIG. 5 appears, the signal C1 appearing at the terminal 14 of FIG. , That is, the transistor 1 which is coupled to the terminal 18a and is in the conductive state
Turn 6 on. As a result, the output pulse signal OUT
_n appears at the drain terminal 13. The signal OUT is applied to the input terminal of the subsequent stage n + 1 in FIG. Stage n
+1 operates similarly to stage n except that it uses the clock signal C2 instead of the clock signal C1 of stage n to turn on the corresponding transistor.
When the clock signal C1 goes low, which is inactive, the transistor 16 remains on until the signal P1 goes low. Signal OUT goes low by discharging through transistor 16 when clock signal C1 goes low. Since the transistor 17 connected to the terminal 13 operates as a pull-down resistor, the signal OUT _n becomes inactive LOW level again.

Transistor 25 has its drain-source conduction path coupled between terminal 18a and a reference potential point that only turns off pull-up transistor 16 when transistor 25 is conductive. The gate of the transistor 25 is coupled to the output terminal of the next stages n + 2 in the chain of Figure 4, the output signal OUT n + ₂
Controlled by.

The pulse of the signal OUT _{n + 2 in} FIG. 5 appears at the same time as the clock signal C3. When the pulse of the signal OUT _{n + 2} appears, the transistor 25 of FIG. 3 discharges the interelectrode capacitance CP from the terminal 18a. Signal OU of FIG.
The leading edge LE (n + 2) of the pulse of T _{n + 2} is the clock signal C
It appears before the leading edge C1 (LE) of the pulse following the one. Thus, transistor 25 of FIG. 3 clamps the signal appearing at terminal 18a to a level and inhibits transistor 16 from generating an additional pulse of signal OUT _n when the pulse immediately following clock signal C1 appears. .

The pulse appearing at each output terminal of the register 100 of FIG. 4, eg the pulse of the signal OUT _{n + 2} of FIG.
Appears only once during a 16.6 millisecond vertical interval.
Therefore, the switch transistor 1 of stage n of FIG.
None of 8, 16, and 25 are biased and conduct for more than one clock period in each vertical interval period. This has the advantage that none of the switch transistors are stressed frequently. Transistor 17, which is the only non-switched transistor biased to be continuous conducting, includes switching transistors 18, 25 and 16
Since the gate voltage is kept at a potential relatively smaller than the gate voltage in the conductive state, no large stress is applied. Therefore, the transistor 17 operates continuously as a pull-down transistor.

According to one example of the invention, the impedance of terminal 18a is high during most of the vertical interval. The reason why the impedance of the terminal 18a is low is that
Only when the transistor 18 or 25 is conducting. This configuration has the advantage that only four transistors are used in the entire register stage.

When the gate electrode and the drain electrode of the transistor 18 are connected, the transistor 18 operates as a diode. Therefore, the transistor 18 is replaced with a diode. Diode-coupled transistor 1
Reference numeral 8 charges the inter-electrode capacitance appearing at the terminal 18a to the input pulse amplitude (subtracted by the threshold value) to make the transistor 16 conductive.

As mentioned above, the transistor 25 then discharges the charge on the terminal 18a. Since the diode-coupled transistor 18 conducts in one direction, there is an advantage that the potential of the terminal 18a can be boosted to a higher potential when the clock signal C1 applied to the power supply terminal 14 of the output transistor 16 becomes high. The gate-drain and gate-source capacitances of pull-up transistor 16 couple most of the voltage of clock signal C1 appearing at terminals 14 and 13 to terminal 18a, including capacitance CB, so that transistor 16 Will turn on immediately.

Output pulses OUT _{n-1 to} OUT _{n + 3 of} FIG.
Overlap as shown. The amount of overlap depends on how much the clock phases overlap. Therefore, the desired output pulse overlap can be adjusted for a particular application by adjusting the clock phase overlap.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional shift register composed of a plurality of cascaded stages.

2 is a system diagram showing a known shift register stage that can be used in the shift register of FIG.

FIG. 3 is a system diagram showing a shift register adopting the present invention.

FIG. 4 is a system diagram showing a shift register including a plurality of stages shown in FIG. 3 connected in cascade.

5 is a shift diagram of FIG. 4 using the stage shown in FIG.
It is a figure which shows the relative timing of the output signal which appears in each node of a register, and each clock signal.

[Explanation of symbols]

 12 input terminal 13 drain terminal 14 power supply terminal 16 output transistor 17 non-switch transistor 18 switch transistor 18a terminal 25 switch transistor 100 shift register C1 clock signal C2 clock signal C3 clock signal

 ─────────────────────────────────────────────────── ————————————————————————————————— Inventor Sherman Weissbrod United States 08558 Skillman Sycamore Lane, NJ 80

Claims (12)

[Claims] 1. A shift register comprising means for generating a plurality of phase-shifted clock signals and a plurality of cascaded stages, wherein a specific one of the cascaded stages is the first of the clock signals. An output transistor that generates an output pulse on the output side of the specific stage in response to a clock signal, and a clock signal whose phase is shifted with respect to the first clock signal appears and is applied, Input switching means for generating a control signal stored in a capacitance coupled to a control electrode of the output transistor in the particular stage in response to an output pulse appearing at the output of the second stage,
When the control signal is the first clock signal,
Input switching means for conditioning the output transistor to generate the output pulse of the particular stage; and a conduction path coupled to the control electrode of the output transistor, the phase being relative to the first clock signal. When a pulse following the first clock signal appears in response to an output pulse appearing at its control electrode at the output of the third stage of the cascaded stages when the shifted clock signal appears, said A clamping transistor for clamping the control signal in the particular stage to a level that inhibits the output transistor from producing an output pulse, the control signal being clamped after the control signal is clamped. Generate a substantially higher impedance than the control electrode of the output transistor A shift register including a clamping transistor. 2. The shift register according to claim 1, wherein the capacitance is formed between electrodes of the output transistor. 3. The shift register of claim 1, further comprising a pull-down transistor coupled to the output of the particular stage, the output transistor having a pull-up operation. 4. The shift register according to claim 3, wherein the pull-down transistor is non-switching. 5. The shift register according to claim 4, wherein the switching means includes one of a transistor and a diode. 6. The shift register according to claim 1, wherein the total number of switching elements in the stage is not more than three. 7. The shift register of claim 1, wherein the clamping transistor is responsive to output pulses of the third stage downstream of the particular stage. 8. A scan register comprising a plurality of register stages cascaded with sources of different phase clock signals, wherein successive phase clock signals are periodically coupled to successive register stages. , Each input stage has an input terminal coupled to the output terminal of the adjacent preceding register stage and an output terminal coupled to the input terminal of the adjacent subsequent register stage, and a supply coupled to each clock signal. Has a terminal,
A source coupled to the source terminal having a series connection of a transistor and an impedance coupled across the supply terminal, the register stage output terminal formed by the interconnection of the transistor and the impedance, and having an input connection at the control electrode of the transistor; A follower amplifier, an output coupled to an input connection of the source follower amplifier and an input coupled to the input terminal, the transistor, the control electrode of the transistor and a potential sufficient to render the transistor non-conductive. An active device for unidirectionally conducting a current with another transistor having a main conduction path coupled between the other transistor and the next transistor stage in the cascade. Having an input stage having a control electrode connected to the output terminal of the Scan register. 9. The impedance is a further transistor having a main conduction path and a control electrode coupled between the interconnection point and the supply terminal, the control electrode being the main conductor of the further transistor. 9. The scan register according to claim 8, wherein the impedance appearing in the passage is coupled to the transistor at a potential having a value relatively higher than the impedance appearing when the transistor conducts. . 10. The one-way conducting device is a further transistor having a control electrode coupled to the input terminal and a main conduction path coupled to the control electrode of the transistor. The scan register according to claim 8. 11. The scan register of claim 8, wherein the one-way conducting device is a diode. 12. The further transistor is coupled to an output terminal of a subsequent stage, the subsequent stage, wherein the clock signal applied to the source follower amplifier exhibits a sufficient potential. 9. The scan register according to claim 8, wherein when the follower amplifier is ready to output an output signal, the input stage is in a state of exhibiting high impedance.