JP2006023498A - Liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display which can suppress deterioration in uniformity and increase in power consumption. <P>SOLUTION: A control circuit 1 is formed which receives an HCK signal outputted from a level converting circuit 30 and an HCKX signal and outputs a Hck signal, Hckx signal, signal (1), signal (2), signal (3) and signal (4). A shift register 2 is formed which selectively receives the Hck signal, Hckx signal, signal (1), signal (2), signal (3) and signal (4) in a horizontal scan circuit 3, to sequentially generate horizontal switching drive pulse signals. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a liquid crystal display device. Specifically, by providing a deviation between the falling timing of the first horizontal switch driving pulse signal that determines the potential of the data line and the rising timing of the second horizontal switch driving pulse signal that is the moment of occurrence of noise in the video signal, The present invention relates to a liquid crystal display device which attempts to suppress uniformity degradation.

  In recent years, with the spread of equipment with a liquid crystal display device typified by a liquid crystal projector or the like, the performance and functionality of the liquid crystal display device have been advanced. In particular, the progress of an active matrix liquid crystal display device employing a thin film transistor (hereinafter simply referred to as “TFT”) having polycrystalline silicon as an active layer is remarkable (see, for example, Patent Document 1).

Hereinafter, a conventional active matrix liquid crystal display device will be described with reference to the drawings.
FIG. 4 is a diagram for explaining a circuit configuration of a conventional active matrix type liquid crystal display device. As shown in FIG. 4, a plurality of gate lines X ₁ , X ₂ , X ₃ arranged in parallel in the X-axis direction. , And a plurality of data lines Y ₁ , Y ₂ , Y ₃ ... Arranged in parallel to the Y-axis direction. For example, a thin film transistor (TFT) is provided at the intersection of each gate line and the data line. ) And the like, and a liquid crystal cell composed of a liquid crystal sandwiched between a pixel electrode and a counter electrode COM facing each other corresponding to each of the active elements, and the active elements T ₁₁ , T ₁₂ , T ₂₁ , T _22. L ₁₁ , L ₁₂ , L ₂₁ , L ₂₂ ... Are formed. The gate electrode of each TFT is connected to the gate line, the source electrode is connected to the data line, and the drain electrode is connected to the pixel electrode of the corresponding liquid crystal cell.

Each data line is connected to a common video line 101 via a corresponding horizontal switch S ₁ , S ₂ , S ₃ ..., And a video signal is supplied from the video line. Furthermore, the gate electrode of the switching transistor constituting each horizontal switch is connected to the horizontal scanning circuit 102. This horizontal scanning circuit boosts the signal inputted from the outside and sends the signal to the horizontal scanning circuit and the vertical scanning circuit. A horizontal switch drive pulse signal is sequentially applied to the gate electrode of the switching transistor in synchronization with the horizontal clock signal input from the level conversion circuit 103 to be output. Each gate line is connected to the vertical scanning circuit 104.

  In the circuit configured as described above, when the vertical scanning circuit is driven, the gate lines are excited line-sequentially, and a TFT is selected for each row. At this time, when the horizontal scanning circuit is driven and the switching transistors are operated in a line sequential manner, the video signal supplied to the video line is sequentially sampled on each data line. The sampled video signals are sequentially written into the corresponding liquid crystal cells via the TFTs selected for each row, and the sampling data of the video signals are written into the individual liquid crystal cells in a dot sequence.

  By the way, as shown in FIG. 5, the horizontal scanning circuit is composed of a shift register S / R 105 having D-type flip-flops connected in multiple stages, and the horizontal switch drive pulse signal output from the previous shift register is shown. The shift register is configured to sequentially output the horizontal switch drive pulse signal at a timing such that the horizontal switch drive pulse signal output from the next-stage shift register rises in synchronization with the fall.

  Specifically, as shown in FIG. 6, the shift register unit 105 includes a first P channel MOS transistor 121, a second P channel MOS transistor 122, a first N channel MOS transistor 123, and a second N channel. A first circuit 120 in which MOS transistors 124 are connected in series, a third P-channel MOS transistor 131, a fourth P-channel MOS transistor 132, a third N-channel MOS transistor 133, and a fourth N-channel MOS transistor 134 Are connected in series, and the first P channel MOS transistor and the second N channel MOS transistor have the common gate terminal as the input terminal of the first circuit, and the second P channel MOS transistor. And the first N-chan The connection point of the first MOS transistor is the output terminal of the first circuit, the common gate terminal of the third P-channel MOS transistor and the fourth N-channel MOS transistor is the input terminal of the second circuit, and the fourth P A connection point between the channel MOS transistor and the third N-channel MOS transistor is used as an output terminal of the second circuit.

  Here, in the N (N: natural number) stage shift register unit, when N = 1, that is, in the case of the first stage shift register unit, the reference signal is input to the input terminal of the first circuit. In the case of N ≧ 2, that is, in the case of shift register units in the second and subsequent stages, the output signal of the previous shift register unit is input to the input terminal of the first circuit. In addition, a signal obtained by inverting the output signal of the first circuit by the inverter 140 is input to the input terminal of the second circuit. A signal output from the level conversion circuit (hereinafter referred to as an HCK signal) is input to the gate terminals of the first N-channel MOS transistor and the fourth P-channel MOS transistor, and the second P-channel MOS transistor and The gate terminal of the third N-channel MOS transistor is configured to receive a signal obtained by inverting the above-described HCK signal output from the level conversion circuit (hereinafter referred to as an HCKX signal). A signal obtained by inverting the output signal of the circuit or the second circuit by an inverter is output as an output signal of the shift register unit.

  In the N + 1 stage shift register unit, the output signal of the previous stage shift register unit is input to the input terminal of the first circuit, and the output signal of the first circuit is the inverter to the input terminal of the second circuit. Thus, a signal subjected to inversion processing is input. The HCKX signal is input to the gate terminals of the first N-channel MOS transistor and the fourth P-channel MOS transistor, and the HCK signal is input to the gate terminals of the second P-channel MOS transistor and the third N-channel MOS transistor. And a signal obtained by inverting the output signal of the first circuit or the second circuit by an inverter is output as an output signal of the shift register unit.

  In both the N-th and N + 1-th shift register units, a ground potential is supplied to one end of the second N-channel MOS transistor and the fourth N-channel MOS transistor, and the first P-channel MOS transistor and the third N-channel MOS transistor A power supply potential is supplied to one end of the P-channel MOS transistor.

When the HCK signal indicated by HCK in FIG. 7, the HCKX signal indicated by HCKX in FIG. 7, and the reference signal A are taken into the shift register configured as described above, reference symbols a ₁ , a ₂ , a _3. The horizontal switch drive pulse signals indicated by-are sequentially output, but each horizontal switch drive pulse signal has variations.
Furthermore, when a horizontal switch drive pulse signal is applied to a corresponding horizontal switch, the video signal supplied from the video line is sampled to each data line through the conductive horizontal switch. Since there is a predetermined capacitance component, charging / discharging of the data line occurs according to the horizontal switch drive pulse signal, and the video signal supplied from the video line indicated by Vsig in FIG. 7 is shown in FIG. As described above, noise is generated at the rise of each horizontal switch drive pulse signal, and the noise level also varies due to variations in transistor characteristics and the like.
In this way, if the video signal generates noise at the rising edge of each horizontal switch drive pulse signal, the first horizontal switch is generated at the moment when the noise of the video signal is generated by starting the subsequent horizontal switch drive pulse signal. When the drive pulse signal falls, the potential of the data line is determined. Due to the influence of noise variation in the video signal, variation in the horizontal switch drive pulse signal, etc., the determined potential of the data line varies, resulting in a display image. There was a problem of causing uniformity degradation such as vertical stripes.

In view of the problems as described above, a circuit as shown in FIG. 8 for controlling the horizontal switch driving pulse signal at a timing not affected by the noise of the video signal has been proposed.
That is, a circuit is proposed in which a signal output from the level conversion circuit is input to the control circuit 106, and a signal controlled by the control circuit is input to the horizontal scanning circuit.

  Here, the control circuit connects the signal output from the level conversion circuit and the signal output from the level conversion circuit through the even number of inverters 107 to the NAND element 108 and further outputs the output. It is configured to connect to the Buffer 109.

The operation of the horizontal scanning circuit configured as described above will be described with reference to FIG. 9 showing a timing chart of each pulse.
When the HCK signal indicated by HCK in FIG. 9 is input to the control circuit, the signal indicated by dck in FIG. 9 that has passed through an even number of inverters and delayed from the HCK signal is NAND-processed and inverted by the output buffer. Processing is performed, and a signal indicated by DCK in FIG. 9 (hereinafter referred to as a DCK signal) is output.
Here, the DCK signal controlled by the control circuit is a pulse whose pulse rising timing is delayed from that of the HCK signal.

Further, when the HCKX signal indicated by HCKX in FIG. 9 is input to the control circuit, the NAND processing of the signal indicated by dckx in FIG. Is performed by the output buffer, and a signal indicated by DCKX in FIG. 9 (hereinafter referred to as a DCKX signal) is output.
Here, the DCKX signal controlled by the control circuit is a pulse whose pulse rising timing is delayed from that of the HCKX signal.

From the DCK signal obtained as described above and the horizontal switch drive pulse signals a ₁ , a ₃ , a ₅ ... Output from the shift register, the horizontal switch drive pulse signals a ₁ , a ₃ , a _5. .., The control signals e ₁ , e ₃ , e ₅ ... With delayed pulse rise timing can be obtained, and similarly, the DCKX signal and the horizontal switch drive pulse signals a ₂ , a ₄ output from the shift register are obtained. , A ₆ ..., Control signals e ₂ , e ₄ , e ₆ ... With delayed pulse rise timing compared to the horizontal switch drive pulse signals a ₂ , a ₄ , a _6. Can do.

The video signal is sampled by the control signals e ₁ , e ₂ , e ₃ ... Obtained as described above, and compared with the timing when the preceding horizontal switch drive pulse signal that determines the potential of the data line falls. Thus, the rise timing of the subsequent horizontal switch drive pulse signal, which is the moment when the noise of the video signal is generated, is delayed to solve the problem of uniformity degradation that has been a problem in the past.

Japanese Patent Laid-Open No. 2002-140028

However, the DCK signal is shared by the shift registers that output the horizontal switch drive pulse signals a ₁ , a ₃ , a ₅ ..., And the DCKX signal is shared by the horizontal switch drive pulse signals a ₂ , a ₄ , a _6. The DCK signal and the DCKX signal have a high frequency as high as the HCK signal and the HCKX signal, and the NAND element provided in the control circuit for controlling the control signal. There is a problem that the power consumption of the horizontal scanning circuit is increased because the size of the output buffer for performing the inversion processing of the output signal must be increased.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a liquid crystal display device capable of suppressing deterioration in uniformity and suppressing increase in power consumption. It is.

  In order to achieve the above object, a liquid crystal display device according to the present invention includes a data line, a horizontal scanning circuit connected to the data line via a horizontal switch, and supplying a pulse for selecting the data line line-sequentially. In the formed liquid crystal display device, a first clock and a second clock having opposite phases are taken in, and at least a first control pulse having a rising timing delayed from the first clock, the first control pulse, A second control pulse having a reverse phase, a third control pulse having a rising timing delayed at least with respect to the second clock and a rising timing delayed with respect to the first control pulse, and the third control pulse; A control circuit for generating a fourth control pulse having a reverse phase, and the horizontal scanning circuit includes the first clock and the second clock. A horizontal switch drive pulse signal for selectively taking in each transfer stage and driving the horizontal switch from the output unit. Are sequentially generated.

  Here, the control circuit generates the first control pulse, the second control pulse, the third control pulse, and the fourth control pulse, and the shift register generates the first clock, the second clock, and the first control pulse. The first horizontal switch drive pulse is generated by selectively taking in the pulse, the second control pulse, the third control pulse, and the fourth control pulse for each transfer stage and sequentially generating the horizontal switch drive pulse signal from the output unit. It is possible to provide a difference between the timing at which the signal falls and the timing at which the subsequent horizontal switch drive pulse signal rises.

  The liquid crystal display device according to the present invention is a liquid crystal display device in which a data line and a horizontal scanning circuit for supplying a pulse for selecting the data line sequentially are formed. A first clock having a rising timing delayed from at least the third clock, a fourth clock having a phase opposite to that of the third clock, and a fourth clock having a phase opposite to the third clock. Pulse, a second control pulse having a phase opposite to that of the first control pulse, and a third control in which the rising timing is delayed with respect to at least the second clock and the rising timing is delayed with respect to the first control pulse. A control circuit that generates a pulse and a fourth control pulse having a phase opposite to that of the third control pulse, and the horizontal scanning circuit includes the third control pulse. A lock, a fourth clock, a first control pulse, a second control pulse, a third control pulse, and a fourth control pulse are selectively fetched for each transfer stage, and a horizontal drive that drives the horizontal switch from an output unit. A shift register for sequentially generating switch drive pulse signals;

  Here, the control circuit generates the third clock, the fourth clock, the first control pulse, the second control pulse, the third control pulse, and the fourth control pulse, and the shift register generates the third clock. , The fourth clock, the first control pulse, the second control pulse, the third control pulse, and the fourth control pulse are selectively fetched for each transfer stage, and the horizontal switch drive pulse signal is sequentially generated from the output unit. By doing so, it is possible to provide a difference between the timing at which the preceding horizontal switch drive pulse signal falls and the timing at which the subsequent horizontal switch drive pulse signal rises.

  In the liquid crystal display device to which the present invention is applied, the subsequent horizontal switch drive pulse signal, which is the moment of occurrence of noise in the video signal, compared to the timing when the previous horizontal switch drive pulse signal that determines the potential of the data line falls. A deviation can be provided in the rise timing of the signal, and the problem of uniformity degradation can be solved.

  In addition, in order to provide a difference between the timing at which the preceding horizontal switch drive pulse signal falls and the timing at which the subsequent horizontal switch drive pulse signal rises, it is only necessary to provide a control circuit for generating a delay pulse, and to provide a control circuit for each shift register unit. Therefore, it is possible to suppress an increase in power consumption of the horizontal scanning circuit.

  Further, in order to provide a difference between the timing of the fall of the first horizontal switch drive pulse signal and the timing of the rise of the subsequent horizontal switch drive pulse signal, a control circuit that generates a delay pulse is provided, and a control circuit is provided for each shift register unit. Etc., the required area of the horizontal scanning circuit can be reduced, the panel size can be reduced, the manufacturing cost can be reduced due to the increase in profits, and the liquid crystal display device can be reduced in size. be able to.

Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
FIG. 1 is a schematic diagram for explaining a circuit configuration of an example of an active matrix liquid crystal display device to which the present invention is applied. The liquid crystal display device shown here uses a signal output from a level conversion circuit 30 as a control circuit 1. The signal controlled by the control circuit is inputted to the horizontal scanning circuit 3 composed of a shift register 2 or the like in which D-type flip-flop circuits are connected in multiple stages.

Here, the control circuit includes a first control circuit 4, a second control circuit 5, a third control circuit 6, and a fourth control circuit 7, and the first control circuit is connected via an inverter 31 and an output buffer 8. The second control circuit is connected to the second wiring 10 via an inverter and an output buffer.
Further, the third control circuit is configured to input the signal output from the level conversion circuit and the signal passed through the even number of inverters to the NAND element 11, and the output terminal of the NAND element receives the inverter and the output buffer. And the output terminal of the NAND element is also connected to the fourth wiring 13 via the output buffer. Further, the fourth control circuit is configured to input the signal output from the level conversion circuit and the signal passed through the even number of inverters to the NAND element, and the output terminal of the NAND element is connected to the inverter and the output buffer. The output terminal of the NAND element is also connected to the sixth wiring 15 via the output buffer.

  As shown in FIG. 2, each shift register unit constituting the shift register includes a first P-channel MOS transistor 16, a second P-channel MOS transistor 17, a first N-channel MOS transistor 18 and a second P-channel MOS transistor 18. A first circuit 20 in which N-channel MOS transistors 19 are connected in series, a third P-channel MOS transistor 21, a fourth P-channel MOS transistor 22, a third N-channel MOS transistor 23, and a fourth N-channel The second circuit 25 is formed by sequentially connecting MOS transistors 24 in series. The common gate terminal of the first P-channel MOS transistor and the second N-channel MOS transistor is used as the input terminal of the first circuit, and the second P Channel MOS transistor and first N channel The connection point of the OS transistor is the output terminal of the first circuit, the common gate terminal of the third P-channel MOS transistor and the fourth N-channel MOS transistor is the input terminal of the second circuit, and the fourth P-channel A connection point between the MOS transistor and the third N-channel MOS transistor is used as an output terminal of the second circuit.

  Here, in the n (n: natural number) stage shift register unit, when n = 1, that is, in the case of the first stage shift register unit, the reference signal is input to the input terminal of the first circuit, and n In the case of ≧ 2, that is, in the case of the second and subsequent stage shift register units, the output signal of the previous stage shift register unit is inputted to the input terminal of the first circuit. Further, the input terminal of the second circuit is configured to receive a signal obtained by inverting the output signal of the first circuit by an inverter. The first wiring is connected to the gate terminal of the fourth P-channel MOS transistor, the second wiring is connected to the gate terminal of the second P-channel MOS transistor, and the third wiring is the third N-channel. The fourth wiring is connected to the gate terminal of the first N-channel MOS transistor. The fourth wiring is connected to the gate terminal of the MOS transistor.

  In the n + 1 stage shift register unit, the output signal of the previous stage shift register unit is input to the input terminal of the first circuit, and the output signal of the first circuit is input to the input terminal of the second circuit. A signal that is inverted by an inverter is input, the first wiring is connected to the gate terminal of the second P-channel MOS transistor, and the second wiring is the fourth P-channel MOS transistor. The fifth wiring is connected to the gate terminal of the third N-channel MOS transistor, and the sixth wiring is connected to the gate terminal of the first N-channel MOS transistor.

  In both the n-th and n + 1-th shift register units, a ground potential is supplied to one end of the second N-channel MOS transistor and the fourth N-channel MOS transistor, and the first P-channel MOS transistor and the third N-channel MOS transistor A power supply potential is supplied to one end of the P-channel MOS and the transistor.

  The operation of the liquid crystal display device configured as described above will be described with reference to FIG. 3 showing a timing chart of each pulse.

Now, when the HCK signal indicated by HCK in FIG. 3 enters the control circuit, a signal indicated by Hck in FIG. 3 (hereinafter referred to as Hck signal) delayed from the HCK signal by the first control circuit is generated, An Hck signal is output to the first wiring.
Further, when the HCKX signal indicated by the symbol HCKX in FIG. 3 enters the control circuit, a signal indicated by the symbol Hckx in FIG. 3 delayed from the HCKX signal by the second control circuit (hereinafter referred to as the Hckx signal) is generated. The Hckx signal is output to the second wiring.

When the HCK signal enters the control circuit, a signal indicated by the symbol hck in FIG. 3 (hereinafter referred to as the hck signal) that has passed through an even number of inverters and delayed from the HCK signal by the third control circuit and the HCK signal After the NAND process is performed, the signal passes through the inverter and the output buffer, a signal indicated by reference numeral (1) in FIG. 3 (hereinafter referred to as (1) signal) is generated, and the (1) signal is output to the third wiring. Is done.
Further, NAND processing of the hck signal and the HCK signal is performed by the third control circuit, and then the signal passes through the inverter to generate a signal indicated by reference numeral (2) in FIG. 3 (hereinafter referred to as (2) signal). The (2) signal is output to the fourth wiring.

Further, when the HCKX signal enters the control circuit, a signal indicated by the symbol hckx in FIG. 3 (hereinafter referred to as the hckx signal) and the HCKX signal, which is delayed from the HCKX signal through the even number of inverters by the fourth control circuit, After NAND processing is performed, the signal passes through the inverter and the output buffer to generate a signal indicated by reference numeral (3) in FIG. 3 (hereinafter referred to as (3) signal), and the (3) signal is output to the fifth wiring. Is done.
Further, after NAND processing of the hckx signal and the HCKX signal is performed by the fourth control circuit, the signal passes through the inverter, and a signal indicated by reference numeral (4) in FIG. 3 (hereinafter referred to as (4) signal) is generated. The (4) signal is output to the sixth wiring.

When the Hck signal, Hckx signal, (1) signal, (2) signal, (3) signal, (4) signal and the reference signal indicated by symbol A in FIG. , Horizontal switch drive pulse signals indicated by symbols e ₁ , e ₂ , e ₃ ... In FIG.

  In this embodiment, the shift register takes in the Hck signal, Hckx signal, (1) signal, (2) signal, (3) signal, (4) signal and the reference signal, and outputs a horizontal switch drive pulse signal. However, it is sufficient if a difference can be provided between the timing at which the preceding horizontal switch driving pulse signal falls and the timing at which the subsequent horizontal switch driving pulse signal rises, and the Hck signal and the Hckx signal are not necessarily provided. , (1) signal, (2) signal, (3) signal, (4) signal and reference signal need not be taken in by the shift register, for example, HCK signal, HCKX signal, (1) signal, (2) signal, (3) The signal, (4) signal, and the reference signal may be configured to be captured by the shift register.

  Further, in this embodiment, the timing at which the preceding horizontal switch driving pulse signal falls is delayed by delaying the timing at which the preceding horizontal switch driving pulse signal falls compared to the timing at which the subsequent horizontal switch driving pulse signal rises. The timing of the rise of the subsequent horizontal switch drive pulse signal is offset, but the timing of the fall of the previous horizontal switch drive pulse signal is necessarily delayed compared to the timing of the rise of the subsequent horizontal switch drive pulse signal. For example, by adjusting the fall timing of the reference signal, the rise timing of the subsequent horizontal switch drive pulse signal is delayed compared to the fall timing of the previous horizontal switch drive pulse signal. By Rukoto, it may be provided with a shift.

  In the liquid crystal display device to which the present invention is applied, by sampling the video signal with the horizontal switch drive pulse signal obtained as described above, the timing of the rise of the subsequent horizontal switch drive pulse signal in which the noise of the video signal is generated, and In comparison, the timing at which the preceding horizontal switch drive pulse signal for determining the potential of the data line falls can be delayed to solve the problem of uniformity degradation.

  Further, when delaying the falling timing of the preceding horizontal switch driving pulse signal as compared with the rising timing of the subsequent horizontal switch driving pulse signal, only the control circuit and the wiring for generating the delay pulse are arranged in the horizontal scanning circuit. Thus, since it is not necessary to arrange a control circuit or the like for each shift register unit, an increase in power consumption of the horizontal scanning circuit can be suppressed.

  Furthermore, in order to delay the timing at which the preceding horizontal switch drive pulse signal falls compared to the timing at which the subsequent horizontal switch drive pulse signal rises, only the control circuit and the wiring for generating the delay pulse are arranged in the horizontal scanning circuit. Since there is no need to arrange a control circuit or the like for each shift register, the area of the required horizontal scanning circuit can be reduced, the panel size can be reduced, and the manufacturing cost can be reduced due to the increase in profit. The liquid crystal display device can be downsized.

It is a schematic diagram for demonstrating the circuit structure of the active-matrix liquid crystal display device to which this invention is applied. It is a schematic diagram for demonstrating the shift register of the active matrix type liquid crystal display device to which this invention is applied. 6 is a timing chart of each pulse for explaining the operation of the active matrix liquid crystal display device to which the present invention is applied. It is a schematic diagram (1) for demonstrating the circuit structure of the conventional active matrix type liquid crystal display device. FIG. 5 is a schematic diagram for explaining a horizontal scanning circuit of the active matrix liquid crystal display device shown in FIG. 4. FIG. 5 is a schematic diagram for explaining a shift register of the active matrix liquid crystal display device shown in FIG. 4. It is a figure for demonstrating the noise of a video signal. It is a schematic diagram (2) for demonstrating the circuit structure of the conventional active matrix type liquid crystal display device. 9 is a timing chart of each pulse for explaining the operation of the active matrix type liquid crystal display device shown in FIG. 8.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Control circuit 2 Shift register 3 Horizontal scanning circuit 4 1st control circuit 5 2nd control circuit 6 3rd control circuit 7 4th control circuit 8 Output Buffer
DESCRIPTION OF SYMBOLS 9 1st wiring 10 2nd wiring 11 NAND element 12 3rd wiring 13 4th wiring 14 5th wiring 15 6th wiring 16 1st P channel MOS transistor 17 2nd P channel MOS transistor 18 First N-channel MOS transistor 19 Second N-channel MOS transistor 20 First circuit 21 Third P-channel MOS transistor 22 Fourth P-channel MOS transistor 23 Third N-channel MOS transistor 24 Fourth N-channel MOS transistor 25 Second circuit 30 Level conversion circuit 31 Inverter

Claims (4)

In a liquid crystal display device in which a data line and a horizontal scanning circuit connected to the data line via a horizontal switch and supplying a pulse for selecting the data line line-sequentially are formed,
A first control pulse that takes in a first clock and a second clock that are out of phase with each other and that has at least a rising timing delayed from the first clock, and a second control pulse that is out of phase with the first control pulse A third control pulse whose rise timing is delayed at least with respect to the second clock and whose rise timing is delayed with respect to the first control pulse, and a fourth control pulse having a phase opposite to that of the third control pulse. And a control circuit for generating
The horizontal scanning circuit selectively captures the first clock, the second clock, the first control pulse, the second control pulse, the third control pulse, and the fourth control pulse for each transfer stage, A liquid crystal display device comprising: a shift register that sequentially generates a horizontal switch drive pulse signal for driving the horizontal switch from an output unit. The shift register rises in synchronization with a predetermined rising timing of the first control pulse and also falls in synchronization with a predetermined falling timing of the second clock, or the third control 2. The liquid crystal display device according to claim 1, wherein a horizontal switch drive pulse that rises in synchronization with a predetermined rising timing of the pulse and falls in synchronization with a predetermined falling timing of the first clock is generated. . In a liquid crystal display device in which a data line and a horizontal scanning circuit connected to the data line via a horizontal switch and supplying a pulse for selecting the data line line-sequentially are formed,
A first clock and a second clock that are out of phase with each other, and a third clock that is delayed from the first clock, a fourth clock that is out of phase with the third clock, and at least the first clock A first control pulse whose rising timing is delayed from the second control pulse, a second control pulse having a phase opposite to that of the first control pulse, at least the rising timing is delayed from the second clock, and the first control pulse A control circuit for generating a third control pulse with a rising timing delayed from the third control pulse and a fourth control pulse having a phase opposite to that of the third control pulse,
The horizontal scanning circuit selectively takes in the third clock, the fourth clock, the first control pulse, the second control pulse, the third control pulse, and the fourth control pulse for each transfer stage, A liquid crystal display device comprising: a shift register that sequentially generates a horizontal switch drive pulse signal for driving the horizontal switch from an output unit. The shift register rises in synchronization with a predetermined rise timing of the first control pulse and falls in synchronization with a predetermined fall timing of the fourth clock, or the third control 4. The liquid crystal display device according to claim 3, wherein a horizontal switch drive pulse that rises in synchronization with a predetermined rising timing of the pulse and falls in synchronization with a predetermined falling timing of the third clock is generated. .

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