JP2005166139A - Shift register, method and circuit for driving the same, electrooptic device, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent erroneous transfer by the comparatively small number of circuit elements and to reduce power consumption in a shift register. <P>SOLUTION: In the shift register which generates a transfer pulse in order, each of transfer unit circuits at odd-numbered stages is provided with an odd-numbered stage first switching element which are closed in the active period of a first clock signal, a buffer for odd-numbered stage latch generating the transfer pulse, and an odd-numbered stage second switching element which are closed in the active period of a third clock signal to feedback output and input of the buffer for the odd-numbered stage latch. Each of transfer unit circuits at even-numbered stages is provided with an even-numbered stage first switching element which are closed in the active period of a second clock signal, a buffer for even-numbered stage latch generating the transfer pulse, and an even-numbered stage second switching element which are closed in the active period of the third clock signal to feedback output and input of the buffer for the even-numbered stage latch. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a shift register, a driving method thereof, a driving circuit including the shift register, an electro-optical device such as a liquid crystal device including the driving circuit, and a liquid crystal projector including the electro-optical device. The present invention relates to the technical field of electronic equipment.

  This type of shift register sequentially generates transfer pulses in a plurality of stages each including a transfer unit circuit. For example, according to the first shift register disclosed in Patent Document 1 below, each transfer unit circuit is configured using two complementary transistors, and according to the second shift register disclosed in Patent Document 2 below. Each transfer unit circuit is configured using a single-channel transistor. According to the first or second shift register, two types of signals, a clock signal for starting the transfer operation and a clock signal for latching, are input to the transfer unit circuit at each stage at successive timings. A transfer pulse is generated in response to the signal. Note that, in addition to the two types of clock signals described above, a clock signal that defines a discharge period and the like is further input to each stage of the second shift register.

Japanese Patent Laid-Open No. 11-202295 JP-A-8-84310

  However, according to the first or second shift register, the number of circuit elements for configuring each transfer unit circuit increases and the number of input terminals for the clock signal also increases, so that the layout area also increases. The electro-optical panel tends to have a large number of image display areas in order to perform high-quality image display, and accordingly, the pixel pitch becomes narrow. For this reason, when a driving circuit configured using the first or second shift register is incorporated in the electro-optical panel, the number of wiring inputs to the clock system increases, and a large number of pixels are provided in the image display area of the electro-optical panel. It can be difficult to achieve.

  Further, in the first or second shift register, if the input timings of the two types of clock signals with respect to each transfer unit circuit are shifted, there is a risk of causing malfunction due to racing. That is, since the two types of clock signals are continuously input, if the input timing is shifted in each transfer unit circuit, the transfer pulse of the previous stage passes through the transfer unit circuit and enters the transfer unit circuit of the next stage. Will cause so-called racing.

  Further, according to the second shift register, since each transfer unit circuit is configured by a single channel transistor, a through current is generated, and power consumption during operation increases.

  The present invention has been made in view of the above problems, and a shift register capable of preventing erroneous transfer and reducing power consumption with a relatively small number of circuit elements, a driving method thereof, and the shift register. It is an object of the present invention to provide a drive circuit including the electro-optical device including the drive circuit and an electronic apparatus including the electro-optical device.

  In order to solve the above problems, the shift register of the present invention is a shift register that sequentially generates transfer pulses in a plurality of stages of transfer unit circuits, and each of the plurality of stages of odd-numbered transfer unit circuits is a first register. The odd-numbered stage first switching element that is closed during the active period of the clock signal and passes the transfer pulse or start pulse from the previous stage, and the transfer pulse or start pulse is input through the odd-numbered stage first switching element. And an odd-stage latch buffer for generating a transfer pulse to be transferred to and output to the next stage, and an odd-stage to apply feedback to the input / output of the odd-stage latch buffer during the active period of the third clock signal A second switching element, and each of the even numbered transfer unit circuits of the plurality of stages is defined as the first clock signal. An even-numbered first switching element that is closed during the active period of the second clock signal having a different active period and passes the transfer pulse from the previous stage, and the transfer pulse is input via the even-numbered first switching element And the even-stage latch buffer that generates a transfer pulse that is transferred to the next stage and output, and is closed during the active period of the third clock signal to provide feedback to the input and output of the even-stage latch buffer. And the third clock signal is a logical sum signal of the first and second clock signals and is delayed by a predetermined amount with respect to the first and second clock signals. Clock signal.

  In the shift register of the present invention, the first clock signal, the second clock signal, the third clock signal, and the start pulse are input from the outside during driving. In the plurality of stages of the shift register, the first clock signal is sequentially input to the odd-numbered first switching elements, and the second clock signal is sequentially input to the even-numbered first switching elements. The operation period of the odd-numbered first switching elements is defined by the active period of the first clock signal, and the operation period of the even-numbered first switching elements is defined by the active period of the second clock signal. In the odd-numbered transfer unit circuit, the transfer operation is started by the odd-numbered first switching element in response to the input of the first clock signal, and in the even-numbered transfer unit circuit, the even-numbered transfer unit circuit in response to the input of the second clock signal. The transfer operation is started by one switching element. The first clock signal and the second clock signal are sequentially transferred in a plurality of transfer unit circuits, and the operation period of the odd-numbered or even-numbered first switching element in each transfer unit circuit is The signals are different in phase so as not to overlap.

  The third clock signal is a signal delayed by a predetermined amount with respect to the first clock signal and the second clock signal, and the operation period of the odd-numbered or even-numbered second switching element is defined by the active period of the third clock signal. Is done. By making the third clock signal a clock signal generated based on the logical sum signal of the first clock signal and the second clock signal, the delay amount of the third clock signal with respect to the first clock signal and the second clock signal Can be adjusted.

  In the operation of the shift register of the present invention, first, a transfer operation is started in the first-stage transfer unit circuit. More specifically, when the first clock signal is input, that is, when the active period of the first clock signal is started, the odd-numbered stage first switching element is closed, and the odd-numbered stage first switching element is passed through the odd-numbered stage first switching element. Thus, the start pulse is taken into the first-stage transfer unit circuit and the transfer operation is started.

  The fetched start pulse is input to the odd-stage latch buffer. Then, the first transfer pulse is generated by the odd-stage latch buffer based on the input start pulse.

  Subsequently, in the first-stage transfer unit circuit, the third clock signal is input to the odd-numbered second switching element with a predetermined amount of delay from the input of the first clock signal described above. When the third clock signal is input, that is, when the active period of the third clock signal is started, the odd-numbered second switching element is closed, and the first transfer pulse output from the odd-numbered latch buffer. Is fed back from the output side of the odd-stage latch buffer to the input side. As a result, the odd-numbered second switching and odd-numbered latching buffer functions as a latch circuit, and the output side and input side of the odd-numbered latching buffer are maintained at a predetermined voltage.

  Thereafter, the transfer operation is started in the second-stage transfer unit circuit. In the second-stage transfer unit circuit, the even-numbered stage first switching element is closed in response to the input of the second clock signal, that is, the start of the active period of the second clock signal. The first transfer pulse is taken into the second-stage transfer unit circuit. Then, the second transfer pulse is generated by the even-stage latch buffer in the same manner as the odd-stage latch buffer in the first-stage transfer unit circuit.

  Subsequently, in the second-stage transfer unit circuit, when the third clock signal is input with a predetermined delay from the input of the second clock signal described above and the even-numbered second switching element is closed, the even-numbered stage Since the second switching element operates in the same manner as the odd-numbered second switching element in the first-stage transfer unit circuit, a latch circuit is formed in the second-stage transfer unit circuit.

  Thereafter, the same operation as the second stage is performed in each stage from the third stage to the final stage, and as a result, transfer pulses are sequentially generated.

  As described above, according to the shift register of the present invention, the transfer operation is sequentially started in a plurality of stages according to the first clock signal and the second clock signal. In each transfer unit circuit, a start pulse or a transfer pulse from the previous stage is taken to generate a transfer pulse, and then latching is started.

  Here, the odd-numbered or even-numbered first switching element and the odd-numbered or even-numbered second switching element may be configured using transistors having different conductivity types, or the same conductivity-type transistors may be used. You may comprise. If the odd-numbered or even-numbered first switching element and the odd-numbered or even-numbered second switching element are configured using transistors having different conductivity types, the transfer unit circuit does not need to increase the number of circuit elements. Since it is possible to suppress generation of a through current during operation, power consumption of the shift register can be reduced. In this case, the driving voltage of the shift register, the first to third clock signals, and the voltage of the start pulse can be made the same.

  Therefore, according to the shift register of the present invention, each transfer unit circuit can be configured by a relatively small number of circuit elements, and malfunctions such as racing can be prevented.

  Therefore, compared with the case of manufacturing a shift register having a large number of circuit elements as described above, the yield in manufacturing the shift register of the present invention can be improved. Further, since the shift register of the present invention does not have a large layout area, for example, it is very advantageous when incorporated in a drive circuit of an electro-optical panel configured with a narrow pixel pitch in the image display region.

  In one aspect of the shift register of the present invention, the predetermined amount is larger than the delay amount of the transfer operation in each of the odd-stage and even-stage latch buffers.

  According to this aspect, in each transfer unit circuit, it is possible to start latching after taking a start pulse or a transfer pulse from the previous stage and generating a transfer pulse. Therefore, in this aspect, it is possible to prevent malfunction due to racing more reliably.

  In one aspect of the shift register of the present invention, the odd-numbered or even-numbered first and second switching elements are each configured using transistors having different conductivity types.

  According to this aspect, even if the voltages of the first to third clock signals and the start pulse are the same as the drive voltage of the shift register, the odd-numbered or even-numbered first and second stages in each transfer unit circuit. The potential at the connection point of the switching element is not fixed at the intermediate potential. That is, since no through current is generated, it is possible to reduce power consumption without increasing the number of circuit elements.

  In the aspect in which the odd-numbered or even-numbered first and second switching elements are configured using transistors of different conductivity types, the odd-numbered or even-numbered first switching element and the second switching element are enhancement-type transistors. You may comprise using.

  If comprised in this way, it will become possible to manufacture the odd-numbered stage or even-numbered stage 1st and 2nd switching element, without increasing a dope process. Further, even if the first to third clock signals and the start pulse voltage are the same as the drive voltage of the shift register, the connection of the first and second switching elements in the odd-numbered or even-numbered stages in each transfer unit circuit. The potential at the point is not fixed at an intermediate potential.

  In another aspect of the shift register of the present invention, the voltages of the first, second and third clock signals and the start pulse are the same as the power supply voltage input to the shift register.

  According to this aspect, the shift register can be driven by a small number of power supplies. For example, the shift register can be driven by a single power source.

  In another aspect of the shift register of the present invention, the odd-numbered or even-numbered first and second switching elements are configured using transistors having the same conductivity type.

  According to this aspect, the first to third clock signals and the voltage value of the start pulse are adjusted with respect to the operating voltage of the odd-numbered or even-numbered first and second switching elements, thereby passing through in the same manner as described above. The current can be suppressed. More specifically, according to the threshold voltage values of the odd-numbered or even-numbered first and second switching elements, whether the voltage values of the four types of signals are relatively low with respect to the operating voltage. Or adjust it higher. Therefore, current consumption can be reduced without increasing the number of circuit elements.

  In another aspect of the shift register of the present invention, the odd-numbered or even-numbered first and second switching elements are each configured using a thin film transistor (hereinafter referred to as “TFT” as appropriate).

  According to this aspect, since the odd-numbered or even-numbered first and second switching elements are individually driven sequentially, the threshold voltage value of the TFT constituting the odd-numbered or even-numbered first and second switching elements Even if the mobility value varies between the transfer unit circuits of the shift register, malfunction can be prevented.

  In another aspect of the shift register of the present invention, each of the odd-numbered-stage and even-numbered-stage latching buffers has two inverter circuits connected in series, and the start pulse or the transfer among the two inverter circuits. One of the pulse input sides is an inverter circuit having a threshold voltage higher than the threshold voltage of the corresponding odd-stage or even-stage first switching element.

  According to this aspect, the threshold voltage of the one inverter circuit in the odd-stage and even-stage latch buffers is adjusted by increasing the threshold voltage of the corresponding odd-stage or even-stage first switching element. . Therefore, it is possible to prevent the odd-numbered stage and even-numbered stage latch buffers from malfunctioning due to the occurrence of a through current in the odd-numbered stage and even-numbered stage first switching elements.

  According to another aspect of the shift register of the present invention, the shift register further includes transfer direction setting means for selectively setting the order in which the transfer pulses are sequentially output with respect to the plurality of stages arranged in the forward direction or the reverse direction.

  According to this aspect, the shift register of the present invention can be driven in both forward and reverse directions. Further, in both cases of driving in the forward direction or in the reverse direction, it is possible to prevent malfunction.

  In another aspect of the shift register of the present invention, the odd-numbered stage first switching element and the odd-numbered stage latching buffer and the even-numbered stage first switching element and the even-numbered stage latching buffer, A holding capacitor for holding the voltage of the input transfer pulse is further provided.

  In this aspect, when the odd-numbered and even-numbered first switching elements and the odd-numbered and even-numbered second switching elements in each transfer unit circuit are in the open state, the input side of the odd-numbered and even-numbered latch buffers is held by the holding capacitor. It becomes possible to hold at a predetermined voltage. As a result, the transfer pulse can be maintained at a predetermined voltage and output from each transfer unit circuit even while feedback of the odd-numbered and even-numbered second switching elements is stopped.

  In order to solve the above problems, the drive circuit of the present invention generates the first and second clock signals and the first and second clock signals as well as the shift register of the present invention described above (including various aspects thereof). A clock signal generation circuit that generates the third clock signal by logically summing and delaying two clock signals, and sequentially outputting the transfer pulses as drive signals directly from the shift register or through other circuits. Is done.

  In the driving circuit of the present invention, the first and second clock signals are generated by the clock signal generation circuit so as to have different phases. In this way, by generating the first and second clock signals, the operation periods of the odd-numbered and even-numbered first switching elements in each transfer unit circuit of the shift register of the present invention are controlled so as not to overlap each other. .

  The third clock signal may be generated after being logically summed with the first and second clock signals, or may be generated by being logically summed after being delayed. In the clock signal generation circuit, the delay amount of the third clock signal with respect to the first and second clock signals is adjusted. Thus, in the shift register of the present invention, each transfer unit circuit can start latching after taking a start pulse or a transfer pulse from the previous stage and generating a transfer pulse. Here, if the delay amount of the third clock signal with respect to the first and second clock signals is increased, the time during which the through current is generated in each transfer unit circuit becomes longer. Therefore, it is preferable that the third clock signal is generated in the clock signal generation circuit according to the performance of the odd-numbered or even-numbered first and second switching elements so that the generation of the through current is suppressed.

  Therefore, according to the drive circuit of the present invention, for example, when the drive circuit is incorporated in the electro-optical panel, the first to the first input to the shift register of the present invention by the clock signal generation circuit without using a new interface. It becomes possible to generate a 3-clock signal.

  It should be noted that waveform control is performed on the transfer pulse output from each transfer unit circuit by outputting the transfer pulse as a drive signal through another circuit, more specifically, for example, an enable means, a buffer circuit, and a level shifter. Can be performed.

  In one aspect of the drive circuit according to the present invention, the other circuit applies the transfer pulse to the transfer pulse so that periods of the drive signal output do not overlap with each other on the time axis based on the third clock signal. Enable means for performing waveform control is included.

  According to this aspect, based on the third clock signal for starting the latch in each transfer unit circuit of the shift register of the present invention, waveform control is performed on each transfer pulse by the enable means. Thus, the period during which each drive signal is output is controlled, and the drive signal can be sequentially output from the drive circuit of the present invention based on the latch start timing in each transfer unit circuit. In other words, the signal for the enable means and the third clock signal can be shared, which is advantageous.

  In order to solve the above problems, an electro-optical device according to the present invention includes the above-described drive circuit according to the present invention (including various aspects thereof) and an electro-optical panel that is driven based on the sequentially output drive signals. Prepare.

  In the electro-optical device of the present invention, it is possible to operate the drive circuit normally without using a new interface or inputting a new signal for driving the drive circuit of the present invention from the outside. Become.

  As described above, since the shift register of the present invention does not have a large layout area, it is possible to realize a large number of pixels in the image display region of the electro-optical panel, and to perform high-quality image display.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention.

  Since the electronic apparatus of the present invention includes the above-described electro-optical device of the present invention, a projection display device, a television, a mobile phone, an electronic notebook, a word processor, a view capable of performing high-quality image display. Various electronic devices such as a finder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. In addition, as the electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper, an electron emission device (Field Emission Display and Conduction Electron-Emitter Display), and the like can be realized.

  In order to solve the above-described problem, the shift register driving method of the present invention is a shift register driving method for driving a shift register that sequentially generates transfer pulses in a plurality of stages of transfer unit circuits. (I) the odd-numbered stage switching element is closed during the active period of the first clock signal to pass the transfer pulse or start pulse from the previous stage, and A transfer pulse to be transferred to and output from the next stage is generated by an odd-stage latch buffer to which the transfer pulse or start pulse is input via the first switching element, and (iii) the odd-stage second switching element is A step of applying feedback to the input / output of the odd-stage latch buffer by closing the active state of the 3-clock signal; (I) the even-numbered stage first switching element is closed during the active period of the second clock signal having an active period different from that of the first clock signal. And (ii) a transfer pulse that is transferred to the next stage and output by the even-stage latch buffer to which the transfer pulse is input via the even-numbered first switching element. (Iii) providing a feedback to the input / output of the even-stage latch buffer by closing the even-stage second switching element during an active period of the third clock signal, and the third clock signal Is a logical sum signal of the first and second clock signals and delayed by a predetermined amount with respect to the first and second clock signals.

  According to the shift register driving method of the present invention, each transfer unit circuit can be configured with a small number of circuit elements, as well as the above-described shift register of the present invention, and malfunction such as racing can be prevented. It becomes possible.

  Such an operation and other advantages of the present invention will become apparent from the embodiments described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the electro-optical device of the present invention is applied to a TFT active matrix driving type liquid crystal device.

<1: Configuration of liquid crystal device>
First, the overall configuration of the electro-optical device according to the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the overall configuration of the liquid crystal device according to the present embodiment.

  As shown in FIG. 1, the liquid crystal device 1 includes, as main parts, a liquid crystal panel 100 and a timing generator 400 as an example of an “electro-optical panel” according to the present invention, and a scanning line as an example of a “drive circuit” according to the present invention. A driving circuit 130 and a data line driving circuit 150 are provided.

  In the liquid crystal panel 100, an element substrate in which a TFT 116, a pixel electrode, and the like are formed as a switching element for pixel switching in the image display region 110, and a counter substrate in which a counter electrode and the like are formed are opposed to each other with their electrode formation surfaces facing each other. It is configured by sticking with a certain gap and sandwiching liquid crystal in this gap.

  The timing generator 400 is configured to output various timing signals used in each unit in accordance with a vertical synchronization signal HSYNC, a horizontal synchronization signal VSYNC, and a dot clock DCK supplied from a host device (not shown). More specifically, based on the vertical synchronization signal HSYNC, the horizontal synchronization signal VSYNC, and the dot clock DCK, the Y clock signal YCK, the Y enable signal / YEN, and the Y start pulse DY1, and the X clock signal XCK, the X enable signal / XEN and X start pulse DX1 are generated.

  The scanning line driving circuit 130 and the data line driving circuit 150 are provided in the liquid crystal panel 100, for example. In this case, the scanning line driving circuit 130 and the data line driving circuit 150 are preferably formed in the peripheral region of the element substrate of the liquid crystal panel 100 together with the TFT 116 and the like related to each pixel formed in the image display region 110. Alternatively, the scanning line driving circuit 130 and the data line driving circuit 150 may be at least partially configured as an external IC and may be retrofitted to the peripheral region.

  The liquid crystal panel 100 further includes data lines 114 and scanning lines 112 wired vertically and horizontally in an image display area 110 occupying the center of the element substrate, and is arranged in a matrix in each pixel corresponding to the intersections thereof. A pixel electrode 118 and a TFT 116 for controlling the switching of the pixel electrode 118 are provided. In this embodiment, the total number of scanning lines 112 is assumed to be m (where m is a natural number of 2 or more), and the total number of data lines 114 is assumed to be n (where n is a natural number of 2 or more). To do.

  Here, the image signal DATA is supplied to the data line driving circuit 150 from an image signal processing circuit (not shown in FIG. 1) via the image signal supply line L1. The image signal DATA is generated based on input image data input from the outside in an image signal processing circuit. In this example, in order to simplify the description, the image signal DATA represents monochrome gradation, but the present invention is not limited to this, and the image signal is an R signal corresponding to each color of RGB. , G signal, and B signal. In this case, three image signal supply lines may be provided.

  The data line driving circuit 150 applies the image signal DATA supplied from the image signal supply line L1 to each data line 114 as image signals X1, X2, X3, X4,. Each group is supplied to a plurality of adjacent data lines 114. In FIG. 1, if attention is paid to the configuration of one pixel portion surrounded by a dotted line, an image signal Xi (where i = 1, 2, 3,...) Is applied to the source electrode of the TFT 116 from the data line driving circuit 150. , N) is electrically connected, while the gate electrode of the TFT 116 is electrically connected to a scanning line 112 to which a scanning signal to be described later is supplied and the drain of the TFT 116. A pixel electrode 118 is connected to the electrode. Each pixel portion includes a pixel electrode 118, a common electrode formed on the counter substrate, and a liquid crystal sandwiched between the two electrodes. As a result, each intersection of the scanning line 112 and the data line 114 is formed. Correspondingly, they are arranged in a matrix.

  The pixel electrode 118 writes the image signals X1, X2, X3, X4,..., Xn supplied from the data line 114 at a predetermined timing by closing the TFT 116 as a switching element for a certain period. A predetermined level of image signals X1, X2, X3, X4,..., Xn written in the liquid crystal as an example of the electro-optical material via the pixel electrode 118 is transferred between the counter electrode formed on the counter substrate. Hold for a certain period. The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to an image signal is emitted from the electro-optical panel as a whole.

  Here, in order to prevent the held image signal from leaking, a storage capacitor 119 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 118 and the counter electrode. For example, since the voltage of the pixel electrode 118 is held by the storage capacitor 119 for a time that is three orders of magnitude longer than the time when the source voltage is applied, the holding characteristics are improved, resulting in a high contrast ratio. Become.

<2: Scanning line driving circuit>
Next, the scanning line driving circuit 130 will be described with reference to FIGS. 2 to 6 in addition to FIG.

  First, the configuration of the scanning line driving circuit 130 will be described with reference to FIGS. 2 to 4 in addition to FIG. FIG. 2 is a block diagram showing a configuration of the scanning line driving circuit 130. FIG. 3 is a circuit diagram showing the circuit configuration of the Y-side clock signal generation circuit, and FIG. 4 is a circuit diagram showing the circuit configuration of the Y-side shift register, Y-side enable means, and Y-side buffer circuit.

  In FIG. 1, the scanning line driving circuit 130 includes a Y-side clock signal generation circuit 131, a Y-side shift register 133, a Y-side enable unit 135, and a Y-side buffer circuit 137 as main parts.

  2 and 3, the Y-side clock signal generation circuit 131 includes a Y-side first clock signal generation circuit UA1, a Y-side second clock signal generation circuit UA2, and a Y-side third clock signal generation circuit UA3. . As shown in FIG. 3, preferably, the Y-side first clock signal generation circuit UA1 and the Y-side second clock signal generation circuit UA2 have the same circuit configuration. Paying attention to the Y-side first clock signal generation circuit UA1, the Y-side first clock signal generation circuit UA1 includes an Y-side first clock signal generation unit 33a including an inverter 31a and a NAND circuit 32a, and two And a buffer circuit 35a composed of an inverter. The Y-side second clock signal generation circuit UA2 includes a Y-side second clock signal generation unit 33b including an inverter 31b and a NAND circuit 32b, and a buffer circuit 35b.

  Based on the Y clock signal YCK and the Y enable signal / YEN supplied from the timing generator 400, the Y side first clock signal generation circuit UA1 and the Y side second clock signal generation circuit UA2 A Y-side second clock signal YCK12 is generated.

  In FIG. 3, the Y-side third clock signal generation circuit UA3 is a buffer circuit composed of a NOR circuit 37 that logically sums the Y-side first clock signal YCK11 and the Y-side second clock signal YCK12, and two inverters. 38 is provided as a delay unit for generating the Y-side third clock signal YEN1.

  2 and 4, the Y-side first clock signal YCK11, the Y-side second clock signal YCK12, and the Y-side third clock signal YEN1 generated by the Y-side clock signal generation circuit 131 are supplied to the Y-side shift register 133. Entered. The Y-side shift register 133 is supplied with a Y start pulse DY1 from the timing generator 400.

The Y-side shift register 133 includes (m + 1) stages corresponding to m scanning lines 112, and each stage includes a transfer unit circuit UBk (where k = 1, 2, 3,..., (M + 1). )) Is included. In FIG. 4, the transfer unit circuit UBk includes a first switching element TFW1 configured using a p-channel MOS (Metal-Oxide-Semiconductor) TFT, a second switching element TBK1 configured using an n-channel MOSTFT, and 2 The latching buffer LBF1 including two inverters INV11 and INV12 is included.

  In the present embodiment, the threshold voltage of one inverter INV11 in the latching buffer LBF1 is preferably higher than the threshold voltage of the first switching element TFW1. The first switching element TFW1 and the second switching element TBK1 are preferably configured using enhancement type transistors.

  In the Y-side shift register 133, the Y-side first clock signal YCK11 is sequentially input to the odd-numbered first switching element TFW1, and the Y-side second clock signal YCK12 is sequentially input to the even-numbered first switching element TFW1. The Y-side third clock signal YEN1 is input to the second switching element TBK1 of each stage. When the Y start pulse DY1 is input to the Y side shift register 133 in the (m + 1) stage of the Y side shift register 133, the Y side first clock signal YCK11, the Y side second clock signal YCK12, and the Y side third register Y-side transfer pulses YP1, YP2,..., YPm + 1 are sequentially generated at a timing based on the clock signal YEN1.

  In FIG. 2, the scanning signal generation unit 138 including the Y-side enable unit 135 and the Y-side buffer circuit 137 includes unit circuits UC 1, m circuits corresponding to (m + 1) stages of the Y-side shift register 133. UC2, ..., UCm are included. 2 and 4, each unit circuit UCj (where j = 1, 2, 3,..., M) includes a waveform shaping circuit including NAND circuits NAND10 and NAND11, and two inverters INV13. And a buffer circuit including INV14 is provided. The Y-side enable means 135 includes a waveform shaping circuit included in each stage unit circuit UCj, and the Y-side buffer circuit 137 includes a buffer circuit included in each stage unit circuit UCj.

  In m stages of the scanning signal generation unit 138, waveform control and the like are performed on the Y-side transfer pulses YP1, YP2, YP3,..., YPm, YPm + 1 sequentially output from the Y-side shift register 133, and then Y Scan signals Y 1, Y 2,..., Ym are sequentially output to the scan lines 112 as side drive signals.

  Next, the operation of the scanning line driving circuit 130 will be described with reference to FIGS. 5 and 6 in addition to FIGS. FIG. 5 shows a timing chart for explaining generation of the Y-side first to third clock signals YCK11, YCK12, and YEN1, and FIG. 6 shows Y-side transfer pulses YP1, YP2,. , And generation of scanning signals Y1, Y2,..., Ym are shown in a timing chart.

  In the present embodiment, in the scanning line driving circuit 130, the Y-side clock signal generation circuit 131 and the Y-side shift register 133 are driven by a power supply voltage determined by the low potential Vss and the high potential Vdd.

  First, the operation of the Y-side clock signal generation circuit 131 in the scanning line driving circuit 130 will be described. In operation, as shown in FIG. 3, the Y clock signal YCK is supplied to the NAND circuit 32a of the Y side first clock signal generation unit 33a in the Y side first clock signal generation circuit UA1. The Y clock signal YCK is supplied to the Y side second clock signal generation circuit UA2 via the inverter 31a of the Y side first clock signal generation unit 33a.

  The Y enable signal / YEN is supplied to the NAND circuit 32b and the Y side first clock signal generation circuit UA1 through the inverter 31b of the Y side second clock signal generation unit 33b in the Y side second clock signal generation circuit UA2. The

  In the Y-side first clock signal generation circuit UA1, the NAND circuit 32a of the Y-side first clock signal generation unit 33a is supplied via the Y clock signal YCK and the inverter 31b of the second clock signal generation unit 33b. Perform logical operation on signal / YEN. The output signal of the NAND circuit 32a is input to the buffer circuit 35a in the Y-side first clock signal generation circuit UA1, and the Y-side first clock signal YCK11 is output from the buffer circuit 35a.

  Further, in the Y-side second clock signal generation circuit UA2, the NAND circuit 32b of the Y-side second clock signal generation unit 33b supplies the output signal of the inverter 31b and the inverter 31a of the Y-side first clock signal generation unit 33a. After the logical operation using the Y clock signal YCK is performed, the Y-side second clock signal YCK12 is output via the buffer circuit 35b.

  In FIG. 5, the active period of the Y-side first clock signal YCK11 and the Y-side second clock signal YCK12 shown as “operation” is delayed by Td31 with respect to the Y enable signal / YEN. Here, in the Y-side shift register 133, the operation period of the odd-stage first switching element TFW1 is defined by the active period of the Y-side first clock signal YCK11, and the operation period of the even-stage first switching element TFW1 is the Y-side second. It is defined by the active period of the clock signal YCK12. The transfer operation is started by the odd-numbered first switching element TFW1 according to the input of the Y-side first clock signal YCK11, and the transfer operation is started by the even-numbered first switching element TFW1 according to the input of the Y-side second clock signal YCK12. Each starts. The Y-side first clock signal YCK11 and the Y-side second clock signal YCK12 are sequentially transferred in the (m + 1) stage of the Y-side shift register 133, and the first switching element TFW1 in each stage. The signals are different in phase so that the operation periods of the two do not overlap.

  In FIG. 3, in the Y-side third clock signal generation circuit UA3, the delay unit 38 outputs a logical sum signal of the Y-side first clock signal YCK11 and the Y-side second clock signal YCK12 output from the NOR circuit 37. The Y-side third clock signal YEN1 is generated with a delay by a fixed amount.

  In FIG. 5, the active period of the Y-side third clock signal YEN1 indicated as “operation” is delayed by Td32 defined by, for example, time t31 and time t32 with respect to the active period of the Y-side first clock signal YCK11. To do. Alternatively, the active period of the Y-side third clock signal YEN1 is delayed by, for example, Td32 defined by the time t33 and the time t34 with respect to the active period of the Y-side second clock signal YCK12.

  The active period of the Y-side third clock signal YEN1 defines the operation period of the odd-stage or even-stage second switching element TBK1 in the Y-side shift register 133. The delay amount Td32 described above is larger than the delay amount of the transfer operation in each of the odd-stage and even-stage latch buffer LBF1. Further, when the delay amount Td32 is increased, the time during which a through current as described later is generated in each stage of the Y-side shift register 133 becomes longer. Therefore, the Y-side third clock signal YEN1 is generated according to the performance of the odd-numbered or even-numbered first and second switching elements TFW1 and TBK1 so that the generation of such a through current is suppressed. preferable.

  Next, the operation of the Y side shift register 133 will be described. In FIG. 6, first, the Y start pulse DY1 becomes a high level. Thereafter, when the Y-side first clock signal YCK11 changes from the high level to the low level at time t21, the active period is started, and in FIG. 4, the transfer operation is started in the first-stage transfer unit circuit UB1. More specifically, in the first-stage transfer unit circuit UB1, the first switching element TFW1 is closed at time t21, and the Y start pulse DY1 is transmitted via the first switching element TFW1. The transfer operation is started by being taken into the transfer unit circuit UB1. Therefore, at time t21, the potential of the node A1 on the output terminal side of the first switching element TFW1 becomes high level.

  The Y start pulse DY1 captured in the first-stage transfer unit circuit UB1 is input to the latch buffer LBF1, and the first Y-side transfer pulse YP1 is generated by the latch buffer LBF1.

  In FIG. 6, at time t22, the Y-side third clock signal YEN1 transitions from the low level to the high level with a delay of Td2 from the Y-side first clock signal YCK11, and the active period of the Y-side third clock signal YEN1 Is started. Then, in FIG. 4, in the first-stage transfer unit circuit UB1, the second switching element TBK1 is closed, and the first Y-side transfer pulse YP1 output from the latch buffer LBF1 is supplied to the latch buffer LBF1. Feedback from the output side to the input side.

  Note that the Y-side first to third clock signals YCK11, YCK12, and YEN1, and the Y start pulse DY1 are voltages defined by the low potential Vss and the high potential Vdd. Therefore, the node A1 on the input side of the latch buffer LBF1 is maintained at a voltage between the low potential Vss and the high potential Vdd by the feedback of the latch buffer LBF1 as described above.

  Thereafter, when the Y-side third clock signal YEN1 transitions from the high level to the low level at time t23, the second switching element TBK1 is opened, and the feedback by the second switching element TBK1 ends.

  Thereafter, at time t24, when the Y-side second clock signal YCK12 changes from the high level to the low level and the active period is started, the transfer operation is started in the second-stage transfer unit circuit UB2. In the second-stage transfer unit circuit UB2, the first switching element TFW1 is closed at time t24, and the first Y-side transfer pulse YP1 is transferred to the second-stage transfer unit via the first switching element TFW1. It is captured in the circuit UB2. Therefore, at time t24, the potential of the node B1 on the output terminal side of the first switching element TFW1 in the second-stage transfer unit circuit UB2 becomes high level. Then, similarly to the first-stage transfer unit circuit UB1, the second Y-side transfer pulse YP2 is generated by the latch buffer LBF1.

  Subsequently, at time t25, when the active period of the Y-side third clock signal YEN1 starts later than the active period of the Y-side second clock signal YCK12, the second-stage and first-stage transfer unit circuits UB1 and The second switching element TBK1 of UB2 is closed. As in the first stage, feedback is performed by the second switching element TBK1 in the second-stage transfer unit circuit UB2. Therefore, the voltage at the node A1 and the node B1 is maintained at a voltage between the low potential Vss and the high potential Vdd.

  Thereafter, when the Y-side third clock signal YEN1 transitions from the high level to the low level at time t26, the above-described feedback in the first-stage and second-stage transfer unit circuits UB1 and UB2 ends.

  In each stage from the third stage to the final stage, the same operation as in the second stage is performed, and as a result, Y-side transfer pulses YP1, YP2,..., YPm + 1 are sequentially generated.

  Here, when the active period of the Y-side first clock signal YCK11 is started at time t27, the first switching element TFW1 is again closed in the first-stage transfer unit circuit UB1, and the potential of the node A1 is Transition from high level to low level. Since the first switching element TFW1 is driven by the same voltage as the voltage of the Y start pulse DY1, a through current corresponding to the threshold voltage Vthp2 of the first switching element TFW1 is generated at the node A1 at time t27.

  As described above, since the threshold voltage of INV11 located on the input side of the latch buffer LBF1 is higher than the threshold voltage of the first switching element TFW1, the malfunction of the latch buffer LBF1 due to the occurrence of a through current is prevented. Is done.

  Subsequently, when the active period of the Y-side third clock signal YEN1 is started at time t28, the second switching element TBK1 is closed in the first-stage transfer unit circuit UB1. As a result, since the transmission gate circuit is formed by the first switching element TFW1 and the second switching element TBK1, the potential of the node A1 becomes a low level, that is, a level equivalent to the low potential Vss, and the generation of the through current is suppressed. Is possible.

  As described above, in the Y-side shift register 133 in the scanning line driving circuit 130, the transfer operation is sequentially started in (m + 1) stages according to the Y-side first clock signal YCK11 and the Y-side second clock signal YCK12. In each transfer unit circuit UBk, the Y start pulse DY1 or the Y side transfer pulse YPk-1 from the previous stage is taken to generate the Y side transfer pulse k, and then latching is started.

  Therefore, in the Y-side shift register 133, each transfer unit circuit UBk can be configured with a relatively small number of circuit elements, and malfunctions such as racing can be prevented. In addition, since it is possible to suppress the generation of a through current during operation without increasing the number of circuit elements, the power consumption of the Y-side shift register 133 can be reduced. Therefore, it is possible to improve the yield at the time of manufacturing the Y-side shift register 133 as compared with the case of manufacturing a shift register having a large number of circuit elements as described above.

  Further, the first switching element TFW1 and the second switching element TBK1 in each transfer unit circuit UBk are individually driven sequentially. Therefore, even if the threshold voltage value and mobility value of the TFTs constituting the first and second switching elements TFW1 and TBK1 vary between the transfer unit circuits UBk, it is possible to prevent malfunction. . In addition, the first switching element TFW1 and the second switching element TBK1 are configured using enhancement type transistors, so that the first and second switching elements TFW1 and TBK1 can be manufactured without increasing the doping process. Become.

  In addition, since the Y-side first to third clock signals YCK11, YCK12, and YEN1 are generated by the Y-side clock signal generation circuit 131, a new signal can be input from the outside without using a new interface. In addition, the Y-side shift register 133 can be driven.

  Further, in the waveform shaping circuit of the first-stage unit circuit UC1 of the scanning signal generation unit 138, the second Y-side transfer pulse after the feedback ends in the first-stage transfer unit circuit UB1 at time t24. When YP2 is generated, the potential of the node D1 on the output side of the NAND circuit NAND10 arranged on the input side changes from the high level to the low level. Thereafter, when the active period of the Y-side third clock signal YEN1 starts at time t25, the output signal of the NAND circuit NAND11 arranged on the output side of the first-stage waveform shaping circuit includes the inverters INV13 and INV14. It passes through the buffer circuit and is output as the scanning signal Y1. Accordingly, at time t25, the potential of the scanning signal Y1 changes from the low level to the high level.

  Therefore, the scanning signal Y1 is output from the first-stage unit circuit UC1 during the generation period of the second Y-side transfer pulse YP2 and during the active period of the Y-side third clock signal YEN1. Then, in the unit circuit UCj of each stage from the second stage to the last stage, the same operation as the first stage is performed.

  As described above, in each unit circuit UCj, the output period of each scanning signal Yj is controlled based on the active period of the Y-side third clock signal YEN1, and the scanning signals Y1, Y2,.・ Ym will be output sequentially.

  If a level shifter is used as a buffer circuit in the unit circuit UCj at each stage, the operating voltage of the scanning line driving circuit 130 can be lowered, and the power consumption of the scanning line driving circuit 130 is reduced. It becomes possible to do.

<3: Data line driving circuit>
Next, the data line driving circuit 150 will be described. In FIG. 1, the data line driving circuit 150 includes, as main parts, an X side clock signal generation circuit 151, an X side shift register 153, an X side enable means 155, a primary latch circuit 157, a secondary latch circuit 158, and a D−. A converter 159 is included.

  In the data line driving circuit 150, the X-side clock signal generation circuit 151 is configured similarly to the Y-side clock signal generation circuit 131. Similarly to the Y-side clock signal generation circuit 131, the X-side clock signal generation circuit 151 is based on the X clock signal XCK and the X enable signal / XEN supplied from the timing generator 400, and the X-side first clock signal XCK11. And X side second clock signal XCK12 is generated, and the X side third clock signal XEN1 is generated by delaying the logical sum signal of the X side first clock signal XCK11 and X side second clock signal XCK12.

  The X side shift register 153 is configured similarly to the Y side shift register 133. The X-side first clock signal XCK11, the X-side second clock signal XCK12, and the X-side third clock signal XEN1 are input to the X-side shift register 153. Further, the X start pulse DX1 is supplied from the timing generator 400 to the X side shift register 153.

  The X side shift register 153 includes (n + 1) stages corresponding to the n data lines 114. In the (n + 1) stage of the X side shift register 153, when the X start pulse DX1 is input to the X side shift register 153, the X side first clock signal XCK11, the X side second clock signal XCK12, and the X side third X-side transfer pulses XP1, XP2,..., XPn + 1 are sequentially generated at a timing based on the clock signal XEN1.

  Further, the X-side enable means 155 includes a waveform shaping circuit similar to the unit circuit UCj of the scanning signal generation unit 138 in n stages corresponding to the (n + 1) stages of the X-side shift register 153. At the n stage of the X side enable means 155, waveform control is performed on the X side transfer pulses XP1, XP2,..., XPn + 1 sequentially output from the X side shift register 153 based on the X side third clock signal XEN1. After being performed, sampling signals SP1, SP2,..., SPn are sequentially output.

  The primary latch circuit 157 latches the image signal DATA supplied to the image signal supply line L1 based on the sampling signals SP1, SP2,..., SPn, and subsequently the timing signal output from the timing generator 400. Based on LTX, the output signal of the primary latch circuit 157 is latched by the secondary latch circuit 158. Then, the output signal of the secondary latch circuit 158 converted into an analog signal by the DA converter 159 is output as the image signals X1, X2, X3, X4,.

  Therefore, according to the configuration of the scanning line driving circuit 130 and the data line driving circuit 150 as described above, since the layout area does not increase, it is possible to realize a large number of pixels in the image display region 110 in the liquid crystal panel 100. High-quality image display can be performed.

<4: Modification>
Hereinafter, a modified example of the scanning line driving circuit 130 of the first embodiment described above will be described. Since the data line driving circuit 150 includes the same configuration as the scanning line driving circuit 130 as described above, the configuration of the scanning line driving circuit 130 described below may be applied to the same configuration.

<4-1: First Modification>
First, a first modification will be described with reference to FIGS. FIG. 7 is a circuit diagram illustrating a circuit configuration of a Y-side clock signal generation circuit according to the first modification, and FIG. 8 is a circuit diagram illustrating a circuit configuration of a Y-side shift register according to the first modification. FIG. 9 shows a timing chart for explaining generation of the Y-side first to third clock signals YCK21, YCK22, and / YEN2 according to the first modification, and FIG. 10 shows the first modification. , YPm + 1, and generation of scanning signals Y1, Y2,..., Ym are shown in a timing chart.

  In the Y-side clock signal generation circuit 131a shown in FIG. 7, the Y-side first clock signal generation circuit UA11 receives the output signal of the buffer circuit 35a in addition to the Y-side first clock signal generation unit 33a and the buffer circuit 35a. An inverter 36a for inverting is further provided. In addition, the Y-side second clock signal generation circuit UA12 is further provided with an inverter 36b, similarly to the Y-side first clock signal generation circuit UA11.

  Therefore, the Y-side first clock signal YCK21 and the Y-side second clock signal YCK22 shown in FIG. 9 are signals obtained by inverting the Y-side first clock signal YCK11 and the Y-side second clock signal YCK12 shown in FIG. The active periods of the Y-side first clock signal YCK21 and the Y-side second clock signal YCK22 are delayed by Td61 with respect to the Y enable signal / YEN. Further, the Y-side first clock signal YCK21 and the Y-side second clock signal YCK22 are signals having different phases, like the Y-side first clock signal YCK11 and the Y-side second clock signal YCK12 shown in FIG. .

  In FIG. 7, the Y-side third clock signal generation circuit UA13 has the same circuit configuration as the Y-side third clock signal generation circuit UA3 shown in FIG. The Y-side third clock signal / YEN2 shown in FIG. 9 is a signal obtained by inverting the Y-side third clock signal YEN1 shown in FIG. 5, and the Y-side first clock signal YCK21 and the Y-side second clock signal YCK22 are inverted. Each is delayed by Td62 defined by time t61 and time t62, or time t63 and time t64.

  In FIG. 8, the transfer unit circuit UB1k of the Y side shift register 133 includes a first switching element TFW2 configured using an n-channel MOSTFT and a second switching element TBK2 configured using a p-channel MOSTFT. It has become. The latch buffer LBF2 of each transfer unit circuit UB1k includes two inverters INV21 and INV22, and the threshold voltage of the inverter INV21 arranged on the input side is higher than the threshold voltage of the first switching element TFW2.

  In FIG. 10, when the Y start pulse DY 2 changes from the low level to the high level, the Y start pulse DY 2 is input to the Y side shift register 133. If attention is paid to the first to third stages of the Y-side shift register 133, the potentials of the nodes A2 to C2 at the timing based on the Y-side first clock signal YCK21 and the Y-side second clock signal YCK22 are as follows. Transition from low level to high level sequentially.

  For example, at time t51, a through current corresponding to the threshold voltage Vthn5 of the first switching element TFW2 is generated at the node A2. As described above, since the threshold voltage of INV21 located on the input side of latch buffer LBF2 is higher than the threshold voltage of first switching element TFW2, malfunction of latch buffer LBF2 due to the occurrence of a through current is prevented. Is done.

  Subsequently, at time t52, when the active period of the Y-side third clock signal / YEN2 starts with a delay of Td5 from the active period of the Y-side first clock signal 21, the second switching element TBK2 enters the closed state. Since the transmission gate circuit is formed by the first switching element TFW2 and the second switching element TBK2, the potential of the node A2 becomes a high level, that is, a level equivalent to the high potential Vdd, and the generation of the through current can be suppressed. .

  In the (m + 1) stage of the Y-side shift register 133, the Y-side transfer pulse YP1, at the timing based on the Y-side first clock signal YCK21, the Y-side second clock signal YCK22, and the Y-side third clock signal / YEN2, YP2,..., YPm + 1 are sequentially generated, and waveform control is performed on the Y side transfer pulses YP1, YP2, YP3,..., YPm, YPm + 1, and then scanning is performed as a Y side drive signal. Signals Y 1, Y 2,..., Ym are sequentially output to the scanning line 112.

  Therefore, also in the first modification, each transfer unit circuit UB1k can be configured with a relatively small number of circuit elements in the Y-side shift register 133, and malfunctions such as racing can be prevented, and power consumption can be reduced. Can be reduced. Further, the Y-side shift register 133 can be driven without using a new interface or without inputting a new signal from the outside.

<4-2; Second Modification>
Next, a second modification will be described with reference to FIG. FIG. 11 is a circuit diagram showing a circuit configuration of a Y-side shift register according to the second modification.

  In FIG. 11, the transfer unit circuit UBk of the Y-side shift register 133 has a Y start pulse DY1 or a Y-side transfer pulse YPj input to the transfer unit circuit UBk between the first switching element TFW1 and the latch buffer LBF1. Is further provided with a storage capacitor CND1.

  In FIG. 6, for example, in the first-stage transfer unit circuit UB1, the second switching element TBK1 is opened from time t23 to time t25. However, the potential of the node A1 is set by the storage capacitor installed at the node A1. It becomes possible to maintain the voltage between the low potential Vss and the high potential Vdd.

<4-3; Third Modification>
Next, a third modification will be described with reference to FIGS. FIG. 12 is a circuit diagram showing one circuit configuration of the Y-side shift register according to the third modification, and FIG. 13 is a circuit diagram showing another circuit configuration of the Y-side shift register according to the third modification. is there.

  In FIG. 12, the transfer unit circuit UB3k of the Y-side shift register 133 has a configuration including a first switching element TFW7 and a second switching element TBK7 each configured by using a p-channel MOSTFT. In this case, the voltages of the Y-side first to third clock signals YCK71, YCK72 and YCK73 and the Y start pulse DY7 are lowered with respect to the operating voltages of the first and second switching elements TFW7 and TBK7 in each transfer unit circuit UB3k. As a result, the through current at the node A7, the node B7, or the node C7 can be suppressed. In FIG. 12, each unit circuit UCj of the scanning signal generation unit 138 performs waveform control based on the Y enable signal / YEN 7 output from the timing generator 400.

  Alternatively, as shown in FIG. 13, the transfer unit circuit UB4k of the Y-side shift register 133 may include a first switching element TFW8 and a second switching element TBK8 each configured by using an n-channel MOSTFT. In this case, the voltages of the Y-side first to third clock signals YCK81, YCK82 and YCK83 and the Y start pulse DY8 are increased with respect to the operating voltages of the first and second switching elements TFW8 and TBK8 in each transfer unit circuit UB4k. This makes it possible to suppress the through current at the node A8, the node B8, or the node C8. Also in FIG. 13, each unit circuit UCj of the scanning signal generation unit 138 performs waveform control based on the Y enable signal / YEN8 output from the timing generator 400.

  According to the third modification, it is necessary to use a new power supply to adjust the voltage of each signal input to the Y-side shift register 133 as described above. In contrast, according to the first embodiment, the scanning line driving circuit 130 including the Y-side clock signal generation circuit 131 and the Y-side shift register 133 is driven without using a new power supply as already described. Is possible.

  Further, in the first embodiment, the Y-side first to third clock signals YCK11, YCK12, and YEN1 and the voltage of the Y start pulse DY1 are used as the operations of the first and second switching elements TFW1 and TBK1 in each transfer unit circuit UBk. The voltage may be lowered with respect to the voltage. FIG. 14 shows the waveform of each signal shown in the timing chart of FIG. 6 in this case. In FIG. 14, at time t27, the first switching element TFW1 is closed, and the potential at the node A1 changes from high level to low level. At this time, since the potential of the contact A1 becomes the low potential Vss, the generation of the through current is suppressed.

<4-4; Fourth Modification>
A fourth modification of the electro-optical device according to the invention will be described. In the fourth modification example, the order in which the Y-side transfer pulse YPk is sequentially output is selected with respect to the (m + 1) stage arrangement of the Y-side shift register 133 with respect to the Y-side shift register 133 in the scanning line driving circuit 130. And a transfer direction setting means for setting the forward direction or the reverse direction.

  FIG. 15 shows the circuit configuration of the transfer direction setting means. In FIG. 15, the transfer direction setting means 716 includes (m + 2) forward switching elements SWR and (m + 2) backward switching elements SWL corresponding to the (m + 1) stage of the Y side shift register 133. Each of the forward switching element SWR and the reverse switching element SWL is configured by using, for example, a p-channel MOS TFT.

  During forward operation, the transfer direction setting means 716 is supplied with the first control signal DIR and the second control signal / DIR from the timing generator 400, and (m + 2) forward switching elements SWR are selected. When the forward Y start pulse DYR supplied from the timing generator 400 is input to the transfer direction setting unit 716, the transfer direction setting unit 716 moves in the direction from the first stage to the (m + 1) th stage of the Y-side shift register 133. , Y side transfer pulses YP1, YP2, YP3,..., YPm, YPm + 1 are sequentially generated. In the forward direction, the (m + 1) -th Y-side transfer pulse YPm + 1 generated by the (m + 1) -th stage transfer unit circuit UBm + 1 is output as the inspection signal TPR via the corresponding forward-direction switching element SWRm + 2. You may make it do.

  Also, during reverse operation, as in the forward direction, (m + 2) reverse switching elements SWL in the transfer direction setting means 716 are selected, and the reverse Y start pulse DYL output from the timing generator 400 is input. Then, Y-side transfer pulses YP1, YP2, YP3,..., YPm, YPm + 1 are sequentially generated in the direction from the (m + 1) -th stage of the Y-side shift register 133 to the first stage. In the reverse direction, the (m + 1) th Y-side transfer pulse YPm + 1 generated by the first-stage transfer unit circuit UB1 is output as the inspection signal TPL via the corresponding reverse switching element SWL1. It may be.

  Therefore, according to the fourth modification, the Y-side shift register 133 can be driven in both the forward and reverse directions. Further, in both cases of driving in the forward direction or in the reverse direction, it is possible to prevent malfunction.

<5: Overall configuration of liquid crystal device>
The overall configuration of the liquid crystal device 1 configured as described above will be described with reference to FIGS. 16 and 17. FIG. 16 is a plan view of the TFT array substrate 10 as viewed from the side of the counter substrate 20 together with the components formed thereon, and FIG. 17 is a cross-sectional view taken along the line HH ′ of FIG. .

  In the liquid crystal device shown in FIGS. 16 and 17, the TFT array substrate 10 and the counter substrate 20 are disposed to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are provided with a sealing material 52 provided in a seal region located around the image display region 110. Are bonded to each other.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like for bonding the two substrates, and is applied on the TFT array substrate 10 in the manufacturing process and then cured by ultraviolet irradiation, heating, or the like. It is. Further, in the sealing material 52, a gap material such as glass fiber or glass beads for dispersing the distance (inter-substrate gap) between the TFT array substrate 10 and the counter substrate 20 to a predetermined value is dispersed.

  A light-shielding frame light-shielding film 53 that defines the frame area of the image display region 110 is provided on the counter substrate 20 side in parallel with the inside of the seal region where the seal material 52 is disposed. However, part or all of the frame light shielding film 53 may be provided as a built-in light shielding film on the TFT array substrate 10 side.

  Of the peripheral regions located around the image display region 110, the data line driving circuit 150 and the external circuit connection terminal 102 are arranged on one side of the TFT array substrate 10 in the region located outside the seal region where the sealing material 52 is disposed. It is provided along. The scanning line driving circuit 130 is provided along two sides adjacent to the one side so as to be covered with the frame light shielding film 53. Further, in order to connect the two scanning line driving circuits 130 provided on both sides of the image display area 110 in this way, the TFT array substrate 10 is covered with the frame light shielding film 53 along the remaining side. A plurality of wirings 105 are provided.

  In addition, vertical conduction members 106 that function as vertical conduction terminals between the two substrates are disposed at the four corners of the counter substrate 20. On the other hand, the TFT array substrate 10 is provided with vertical conduction terminals in a region facing these corner portions. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  In FIG. 17, on the TFT array substrate 10, an alignment film is formed on the pixel electrode 118 after the pixel switching TFT, the scanning line, the data line, and the like are formed. On the other hand, on the counter substrate 20, in addition to the counter electrode 21, a lattice-shaped or striped light-shielding film 23 and an alignment film are formed on the uppermost layer portion. Further, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films. Further, a polarizing plate (not shown) corresponding to the orientation direction is provided on the back side of each facing surface of the TFT array substrate 10 and the counter substrate 20.

  In addition to the data line driving circuit 150, the scanning line driving circuit 130, etc., the image signal on the image signal line is sampled and supplied to the data line on the TFT array substrate 10 shown in FIGS. Sampling circuit, precharge circuit for supplying a precharge signal of a predetermined voltage level to a plurality of data lines in advance of the image signal, for inspecting the quality, defects, etc. of the electro-optical panel during production or at the time of shipment An inspection circuit or the like may be formed.

<6; Electronic equipment>
Next, the case where the liquid crystal device 1 described above is applied to various electronic devices will be described.

<6-1: Projector>
First, a projector using the liquid crystal device 1 as a light valve will be described. FIG. 18 is a plan view showing a configuration example of the projector. As shown in this figure, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal panel 100 described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R, 1110B.

  Note that since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

<6-2: Mobile computer>
Next, an example in which this liquid crystal panel is applied to a mobile personal computer will be described. FIG. 19 is a perspective view showing the configuration of this personal computer. In the figure, a computer 1200 includes a main body 1204 having a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal panel 1005 described above.

<6-3; Mobile phone>
Further, an example in which this liquid crystal panel is applied to a mobile phone will be described. FIG. 20 is a perspective view showing the configuration of this mobile phone. In the figure, a cellular phone 1300 includes a reflective liquid crystal panel 1005 together with a plurality of operation buttons 1302. In the reflective liquid crystal panel 1005, a front light is provided on the front surface thereof as necessary.

  In addition to the electronic devices described with reference to FIGS. 18 to 20, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Examples include a station, a videophone, a POS terminal, a device equipped with a touch panel, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  The present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the gist or concept of the invention that can be read from the claims and the entire specification. A driving method, a driving circuit including the shift register, an electro-optical device and an electronic apparatus including the driving circuit are also included in the technical scope of the present invention.

It is a block diagram which shows the whole structure of a liquid crystal device. It is a block diagram which shows the structure of a scanning line drive circuit. It is a circuit diagram which shows the circuit structure of a Y side clock signal generation circuit. It is a circuit diagram which shows the circuit structure of a Y side shift register, a Y side enable means, and a Y side buffer circuit. It is a figure which shows the timing chart for demonstrating operation | movement of the Y side clock signal generation circuit. 6 is a timing chart for explaining operations of a Y side shift register, a Y side enable means, and a Y side buffer circuit. It is a circuit diagram which shows the circuit structure of the Y side clock signal generation circuit which concerns on a 1st modification. It is a circuit diagram which shows the circuit structure of the Y side shift register which concerns on a 1st modification. 12 is a timing chart for explaining the operation of the Y-side clock signal generation circuit according to the first modification. It is a timing chart for demonstrating operation | movement of the Y side shift register, Y side enable means, and Y side buffer circuit which concern on a 1st modification. It is a circuit diagram which shows the circuit structure of the Y side shift register which concerns on a 2nd modification. It is a circuit diagram which shows one circuit structure of the Y side shift register which concerns on a 3rd modification. It is a circuit diagram which shows the other circuit structure of the Y side shift register which concerns on a 3rd modification. It is a timing chart for demonstrating operation | movement of the Y side shift register which concerns on a 3rd modification. It is a circuit diagram which shows the circuit structure of a transfer direction setting means. It is a top view which shows the whole structure of an electro-optical apparatus. It is H-H 'sectional drawing of FIG. It is a top view which shows the structure of the projector which is an example of the electronic device to which a liquid crystal device is applied. It is a perspective view which shows the structure of the personal computer which is an example of the electronic device to which the liquid crystal device is applied. It is a perspective view which shows the structure of the mobile telephone which is an example of the electronic device to which a liquid crystal device is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal device 100 ... Liquid crystal panel 130 ... Scanning line drive circuit 131 ... Y side clock signal generation circuit 133 ... Y side shift register 150 ... Data line drive circuit 151 ... X side clock signal generation circuit 153 ... X side shift register YCK11 ... Y side first clock signal YCK12 ... Y side second clock signal YEN1 ... Y side third clock signal UB1, UB2, ..., UBm + 1 ... transfer unit circuit TFW1 ... first switching element TBK1 ... second switching element LBF1 ... latch Buffer

Claims (15)

A shift register that sequentially generates transfer pulses in a plurality of transfer unit circuits,
The odd-numbered transfer unit circuits in the odd-numbered stages among the plurality of stages are closed in the active period of the first clock signal, and the odd-numbered first switching elements that pass the transfer pulse or start pulse from the previous stage, and the odd-numbered stages An odd-stage latch buffer that generates a transfer pulse that is input to the transfer pulse or the start pulse through the first switching element and that is transferred to the next stage and output; and a closed state in the active period of the third clock signal. And an odd-numbered second switching element for applying feedback to the input / output of the odd-numbered latch buffer,
The even-numbered transfer unit circuits of the plurality of stages are even numbers that are closed during the active period of the second clock signal having an active period different from that of the first clock signal and pass the transfer pulse from the previous stage. A first-stage switching element, an even-stage latching buffer for generating a transfer pulse to which the transfer pulse is input and transferred to the next stage via the even-stage first switching element, and the third clock An even-numbered second switching element that is closed during an active period of the signal and applies feedback to the input / output of the even-numbered latch buffer;
The third clock signal is a logical sum signal of the first and second clock signals, and is a clock signal delayed by a predetermined amount with respect to the first and second clock signals. Shift register.   2. The shift register according to claim 1, wherein the predetermined amount is larger than a delay amount of a transfer operation in each of the odd-stage and even-stage latch buffers. 3. The shift register according to claim 1, wherein the odd-numbered or even-numbered first and second switching elements are configured using transistors of different conductivity types. 4. The shift register according to claim 3, wherein each of the odd-numbered or even-numbered first and second switching elements is configured by using an enhancement type transistor.   5. The voltage of the first, second and third clock signals and the start pulse are the same as the power supply voltage input to the shift register, respectively. The shift register described. 3. The shift register according to claim 1, wherein the odd-numbered or even-numbered first and second switching elements are configured using transistors having the same conductivity type. 7. The shift register according to claim 1, wherein the odd-numbered stage or even-numbered stage first and second switching elements are each configured using a thin film transistor.   Each of the odd-stage and even-stage latch buffers has two inverter circuits connected in series, and one of the two inverter circuits to which the start pulse or the transfer pulse is input corresponds. The shift register according to claim 1, wherein the shift register is an inverter circuit having a threshold voltage higher than a threshold voltage of the odd-stage or even-stage first switching element.   The transfer direction setting means for selectively setting the order in which the transfer pulses are sequentially output with respect to the plurality of stages to the forward direction or the reverse direction is further provided. The shift register described in the paragraph.   To hold the voltage of the input transfer pulse between the odd-numbered stage first switching element and the odd-numbered-stage latching buffer and between the even-numbered stage first switching element and the even-numbered-stage latching buffer. The shift register according to claim 1, further comprising: a storage capacitor. A shift register according to any one of claims 1 to 10,
A clock signal generating circuit that generates the first and second clock signals and generates the third clock signal by logically summing and delaying the first and second clock signals;
The drive circuit, wherein the transfer pulse is sequentially output as a drive signal directly from the shift register or through another circuit.   The other circuit includes an enable unit that performs waveform control on the transfer pulse based on the third clock signal so that periods in which the drive signals are output do not overlap each other on a time axis. The drive circuit according to claim 11, wherein the drive circuit is characterized in that:   13. An electro-optical device comprising: the drive circuit according to claim 11; and an electro-optical panel driven based on the sequentially output drive signals.   An electronic apparatus comprising the electro-optical device according to claim 13. A shift register driving method for driving a shift register that sequentially generates transfer pulses in a plurality of transfer unit circuits,
In each of the odd-stage transfer unit circuits of the plurality of stages, (i) by closing the odd-stage switching element during the active period of the first clock signal, the transfer pulse or start pulse from the previous stage is passed, (ii) an odd-stage latch buffer to which the transfer pulse or start pulse is input via the odd-stage first switching element generates a transfer pulse that is transferred to the next stage and output; (iii) the odd-number stage Applying a feedback to the input / output of the odd-stage latch buffer by closing the second switching element during an active period of the third clock signal;
(I) The even-numbered first switching element is closed in the active period of the second clock signal having an active period different from that of the first clock signal in each of the even-numbered transfer unit circuits of the plurality of stages. Then, the transfer pulse from the previous stage is passed, and (ii) the transfer pulse that is transferred to the next stage and output by the even-stage latch buffer to which the transfer pulse is input via the even-numbered first switching element. And (iii) applying feedback to the input / output of the even-stage latching buffer by closing the even-stage second switching element during the active period of the third clock signal, and
The third clock signal is a logical sum signal of the first and second clock signals, and is a clock signal delayed by a predetermined amount with respect to the first and second clock signals. Driving method of shift register.

Images