JP2010127955A - Electrooptical apparatus and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To display high quality images in an electrooptical apparatus such as a liquid crystal display. <P>SOLUTION: The electrooptical apparatus includes: a pixel region (10a) composed of a plurality of pixels on a substrate (10); an image signal output means (101) having an output circuit (523) for outputting image signals to the pixel region; a phase difference correction means (200) for correcting a phase difference between a clock signal (CLX) for synchronizing timing outputting the image signals and an inverse clock signal (CLXB) for inverting the phase of the clock signal in the image signal output means; first power source potential supply means (401, 402) for supplying power source potential to the output circuit; and second power source potential supply means (403, 404) for supplying power source potential to the phase difference correction means. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  In this type of electro-optical device, for example, display electrodes such as pixel electrodes, and circuit units such as a data line driving circuit and a scanning line driving circuit for driving the electrodes are provided on a substrate. The data line driving circuit is supplied with a clock signal which is the basis of the driving operation and an inverted clock signal whose phase is inverted. At this time, since it is desirable that the phase of the clock signal and the inverted clock signal is exactly the inverted phase, a phase difference correction circuit that corrects the phase of both clock signals to the inverted phase is further provided on the substrate. Provided (see Patent Documents 1 and 2).

Japanese Patent No. 3536657 Japanese Patent No. 3841072

  However, in the above-described technique, the power supply noise generated in the phase difference correction circuit may affect the buffer circuit or the like in the data line driving circuit, and for example, there may be a band-like unevenness in the displayed image. is there. That is, the above-described technique has a technical problem in that although the phase difference between the clock signal and the inverted clock signal can be corrected, there is a possibility that the image quality may be deteriorated.

  SUMMARY An advantage of some aspects of the invention is that it provides an electro-optical device and an electronic apparatus capable of displaying a high-quality image.

  In order to solve the above-described problems, an electro-optical device according to an aspect of the present invention includes a pixel area including a plurality of pixels on an substrate, an image signal output unit that outputs an image signal to the pixel area, and the image signal. In the output means, a phase difference correction means for correcting a phase difference between a clock signal for synchronizing the output timing of the image signal and an inverted clock signal obtained by inverting the phase of the clock signal, and supplying a power supply potential to the output circuit First power supply potential supply means, and second power supply potential supply means for supplying a power supply potential to the phase difference correction means.

  According to the electro-optical device of the present invention, during the operation, an image signal is supplied to a pixel region formed of a plurality of pixels formed on the substrate. As a result, an electro-optical material such as liquid crystal disposed opposite to the substrate via the alignment film is controlled, and an image is displayed in the pixel region.

  The image signal is supplied to the image signal output means on the substrate through, for example, an external circuit connection terminal, and is output to the pixel region from an output circuit such as a buffer circuit provided in the image signal output means. At this time, the timing of outputting the image signal from the image signal output means is synchronized using the clock signal and the inverted clock signal obtained by inverting the phase of the clock signal. That is, the image signal output means is driven based on the clock signal and the inverted clock signal.

  In order to stably operate the image signal output means, it is preferable that the phase of the inverted clock signal is obtained by accurately inverting the phase of the clock signal. However, there may be a deviation (that is, a phase difference) between the clock signal and the inverted clock signal due to, for example, the influence of the transmission path. Such a phase difference is corrected by the phase difference correction means. In other words, the phase difference correction unit performs adjustment so that the clock signal and the inverted clock signal approach the inverted phases of each other.

  Particularly in the present invention, the power supply potential is supplied to the output circuit in the image signal output means by the first power supply potential output means. On the other hand, the power supply potential is supplied to the phase difference correction means by the second power supply potential supply means. That is, the power supply potential is supplied from the different power supply potential supply means to the output circuit and the phase difference correction means.

  If the power supply potential is supplied from the same power supply potential supply means to the output circuit and the phase difference correction means, the power supply potential changes with the operation of the phase difference correction means, and as a result, the same power supply potential is obtained. May affect the output circuit to which the current is supplied. Specifically, for example, the power supply potential may rise and fall according to charging and discharging of the phase difference correction unit, and noise may be added to the image signal output from the output circuit.

  However, in the present invention, as described above, the output circuit and the phase difference correction means are supplied with power supply potentials from different power supply potential supply means. Therefore, even if the power supply potential changes with the operation of the phase difference correction means. The power supply potential supplied to the output circuit is not affected. That is, even if the power supply potential supplied from the second power supply potential supply means to the phase difference correction means changes, the power supply from the first power supply potential supply means different from the second power supply potential supply means is applied to the output circuit. Since the potential is supplied, there is no influence due to the change in the power supply potential. By eliminating the influence of the change in the power supply potential, it is possible to prevent the occurrence of, for example, strip-shaped unevenness in the displayed image.

  As described above, according to the electro-optical device of the present invention, since the power supply potentials of the output circuit and the phase difference correction unit are supplied from different power supply potential supply units, it is possible to display a high-quality image. is there.

  In one aspect of the electro-optical device of the present invention, the image signal output unit includes another circuit provided in a preceding stage of the output circuit, and the first power supply potential supply unit includes the output circuit. Then, a power supply potential is supplied to the other circuit.

  According to this aspect, the image signal output means is provided with a circuit other than the output circuit in the previous stage of the output circuit. A plurality of other circuits may be provided, and examples include other output circuits and precharge circuits. Further, the term “previous stage” here means that it is provided before the output circuit in the transmission path of the image signal. That is, the image signal is transmitted to the output circuit after passing through another circuit in the image signal output means.

  In this embodiment, in particular, the power supply potential is supplied from the first power supply potential supply means to the other circuits in addition to the output circuit. That is, the output circuit and other circuits and the phase difference correction means are supplied with power supply potentials from different power supply potential supply means. In this case, it is possible to prevent the influence due to the change in the power supply potential accompanying the operation of the phase difference correction means from affecting other circuits, so that it is possible to more reliably prevent the image quality from being deteriorated.

  In another aspect of the electro-optical device of the present invention, the electro-optical device further includes a plurality of scanning lines and data lines provided so as to correspond to the plurality of pixels, and the output circuit is electrically connected to the data lines. Yes.

  According to this aspect, a plurality of scanning lines and data lines are provided on the substrate so as to correspond to a plurality of pixels, and a scanning signal is supplied to each pixel via the scanning lines, and the data lines By supplying an image signal to each pixel via the, an image is displayed in the pixel area. An output circuit is electrically connected to the data line, and an image signal output from the output circuit is supplied to each pixel via the data line.

  In this aspect, as described above, an image is displayed by so-called active matrix driving. However, the output circuit that outputs an image signal to the data line is affected by the change in the power supply potential accompanying the operation of the phase difference correction unit. Can be prevented. Therefore, it is possible to reliably prevent the image quality from being deteriorated and display a high-quality image.

  In the aspect including the plurality of scanning lines and data lines, the scanning signal output unit that outputs a scanning signal to the scanning line is further provided, and the first power supply potential supply unit includes the scanning signal in addition to the output circuit. You may comprise so that a power supply potential may be supplied to an output means.

  With this configuration, the power supply potential is supplied from the first power supply potential supply means to the scanning signal output means for outputting the scanning signal to the scanning line. That is, the power supply potential is supplied from the same power supply potential supply means to the output circuit and the scanning signal output means. As a result, the power supply potential is supplied from the different power supply potential supply means to the output circuit, the scanning signal correction means, and the phase difference correction means.

  In this case, since the power supply potential is supplied from the same power supply potential supply means to the output circuit and the scanning signal output means, it is not necessary to provide another power supply potential supply means for the scanning signal output means. Thereby, it is possible to prevent the circuit configuration, wiring layout, and the like from becoming complicated.

  Alternatively, in an aspect including a plurality of scanning lines and data lines, the scanning line output means for outputting a scanning signal to the scanning lines is further provided, and the second power supply potential supply means includes the scanning in addition to the phase difference correction means. You may comprise so that a power supply potential may be supplied to a signal output means.

  With this configuration, the power supply potential is supplied from the second power supply potential supply means to the scanning signal output means for outputting the scanning signal to the scanning line. That is, the power supply potential is supplied from the same power supply potential supply means to the phase difference correction means and the scanning signal output means. As a result, the power supply potential is supplied from different power supply potential supply means to the output circuit, the phase difference correction means, and the scanning signal output means.

  In this case, since the power supply potential is supplied from the same power supply potential supply means to the phase difference correction means and the scanning signal output means, it is not necessary to provide another power supply potential supply means for the scanning signal output means. Thereby, it is possible to prevent the circuit configuration, wiring layout, and the like from becoming complicated. Further, even if the power supply potential changes with the operation of the phase difference correction means, the scanning signal output means is less affected or not affected at all than the output circuit or the like. Therefore, it is possible to reliably prevent the image quality from being lowered and to display a high-quality image.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  According to the electronic apparatus of the present invention, since the electro-optical device according to the present invention described above is provided, a projection display device capable of performing high-quality display, a television, a mobile phone, an electronic notebook, a word processor, Various electronic devices such as a viewfinder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. Further, as the electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper can be realized.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Electro-optical device>
The electro-optical device according to this embodiment will be described with reference to FIGS. In the following embodiments, a drive circuit built-in TFT (Thin Film Transistor) active matrix drive type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.

<First Embodiment>
First, the overall configuration of the electro-optical device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the overall configuration of the electro-optical device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG.

  1 and 2, in the electro-optical device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are disposed to face each other. The TFT array substrate 10 is an example of the “substrate” in the present invention, and is, for example, a transparent substrate such as a quartz substrate or a glass substrate, a silicon substrate, or the like. The counter substrate 20 is a transparent substrate such as a quartz substrate or a glass substrate. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films. The TFT array substrate 10 and the counter substrate 20 are bonded to each other by a sealing material 52 provided in a sealing region located around the image display region 10a provided with a plurality of pixel electrodes. The image display area 10a is an example of the “pixel area” in the present invention.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like for bonding the two substrates, and is applied on the TFT array substrate 10 in the manufacturing process and then cured by ultraviolet irradiation, heating, or the like. It is. In the sealing material 52, a gap material such as glass fiber or glass bead is dispersed for setting the distance between the TFT array substrate 10 and the counter substrate 20 (that is, the inter-substrate gap) to a predetermined value. Note that the gap material may be arranged in the image display region 10a or a peripheral region located around the image display region 10a in addition to or instead of the material mixed in the seal material 52.

  A light-shielding frame light-shielding film 53 that defines the frame area of the image display area 10a is provided on the counter substrate 20 side in parallel with the inside of the seal area where the sealing material 52 is disposed. A part or all of the frame light shielding film 53 may be provided as a built-in light shielding film on the TFT array substrate 10 side.

  In the peripheral region, the data line driving circuit 101 and the external circuit connection terminal 102 as an example of the “image signal output means” of the present invention are arranged in the region located outside the sealing region where the sealing material 52 is disposed. It is provided along one side of the array substrate 10. The scanning line driving circuit 104 is provided along two sides adjacent to the one side so as to be covered with the frame light shielding film 53. Further, in order to connect the two scanning line driving circuits 104 provided on both sides of the image display area 10 a in this way, a plurality of the pixel lines are covered along the remaining side of the TFT array substrate 10 and covered with the frame light shielding film 53. Wiring 105 is provided.

  In regions facing the four corners of the counter substrate 20 on the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are disposed. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  In FIG. 2, on the TFT array substrate 10, a laminated structure in which pixel switching TFTs as drive elements, wiring lines such as scanning lines and data lines are formed is formed. Although the detailed configuration of this laminated structure is not shown in FIG. 2, pixel electrodes 9a made of a transparent material such as ITO (Indium Tin Oxide) are provided on the laminated structure with a predetermined pattern for each pixel. It is formed in an island shape.

  The pixel electrode 9 a is formed in the image display area 10 a on the TFT array substrate 10 so as to face the counter electrode 21. On the surface of the TFT array substrate 10 facing the liquid crystal layer 50, that is, on the pixel electrode 9a, an alignment film 16 is formed so as to cover the pixel electrode 9a.

  A light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. For example, the light shielding film 23 is formed in a lattice shape when viewed in plan on the facing surface of the facing substrate 20. In the counter substrate 20, a non-opening area is defined by the light shielding film 23, and an area partitioned by the light shielding film 23 is an opening area that transmits light emitted from, for example, a projector lamp or a direct viewing backlight. The light shielding film 23 may be formed in a stripe shape, and the non-opening region may be defined by the light shielding film 23 and various components such as data lines provided on the TFT array substrate 10 side.

  On the light shielding film 23, a counter electrode 21 made of a transparent material such as ITO is formed so as to face the plurality of pixel electrodes 9a. Further, in order to perform color display in the image display region 10a, a color filter (not shown in FIG. 2) may be formed on the light shielding film 23 in a region including a part of the opening region and the non-opening region. Good. An alignment film 22 is formed on the counter electrode 21 on the counter surface of the counter substrate 20.

  In addition to the above-described drive circuits such as the data line drive circuit 101 and the scanning line drive circuit 104, the image signal on the image signal line is sampled on the TFT array substrate 10 shown in FIGS. A sampling circuit 7 for supplying the line is provided. Also, a precharge circuit for supplying a precharge signal of a predetermined voltage level to a plurality of data lines in advance of the image signal, an inspection circuit for inspecting the quality, defects, etc. of the electro-optical device during manufacture or at the time of shipment Etc. may be formed.

  Next, an electrical configuration of the pixel portion of the electro-optical device according to the present embodiment will be described with reference to FIG. FIG. 3 is an equivalent circuit diagram of various elements, wirings, and the like in a plurality of pixels formed in a matrix forming the image display area of the electro-optical device according to this embodiment.

  In FIG. 3, a pixel electrode 9a and a TFT 30 are formed in each of a plurality of pixels formed in a matrix that forms the image display region 10a. The TFT 30 is electrically connected to the pixel electrode 9a, and performs switching control of the pixel electrode 9a during the operation of the electro-optical device according to the present embodiment. The data line 6a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. May be.

  The scanning line 3a is electrically connected to the gate of the TFT 30, and the electro-optical device according to the present embodiment pulse-scans the scanning signals G1, G2,. Gm is applied in this order in a line sequential manner. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,... Supplied from the data line 6a is closed by closing the switch of the TFT 30 serving as a switching element for a certain period. Sn is written at a predetermined timing. A predetermined level of image signals S1, S2,..., Sn written in the liquid crystal as an example of the electro-optical material via the pixel electrode 9a is held for a certain period with the counter electrode formed on the counter substrate. The

  The liquid crystal constituting the liquid crystal layer 50 (see FIG. 2) modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. For example, in the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel. In the normally black mode, the transmittance is applied in units of each pixel. As a result, the transmittance for incident light is increased, and light having a contrast corresponding to an image signal is emitted from the electro-optical device as a whole.

  In order to prevent the image signal held here from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode 21 (see FIG. 2). The storage capacitor 70 is a capacitive element that functions as a storage capacitor that temporarily holds the potential of each pixel electrode 9a in response to supply of an image signal. One electrode of the storage capacitor 70 is electrically connected to the drain of the TFT 30 in parallel with the pixel electrode 9a, and the other electrode is electrically connected to the capacitor line 300 having a fixed potential so as to have a constant potential. ing. According to the storage capacitor 70, the potential holding characteristic in the pixel electrode 9a is improved, and display characteristics such as contrast improvement and flicker reduction can be improved.

  Next, a more specific configuration of the electro-optical device according to the present embodiment will be described with reference to FIGS. FIG. 4 is a block diagram illustrating a specific configuration of the electro-optical device according to the first embodiment. FIG. 5 is a circuit diagram showing the configuration of the phase difference correction circuit, and FIG. 6 is a circuit diagram showing the configuration of the inverter in the phase difference correction circuit. In FIG. 4 and subsequent figures, detailed members shown in FIGS. 1 to 3 are omitted as appropriate for convenience of explanation.

  In FIG. 4, the data line driving circuit 101 in the electro-optical device according to this embodiment includes a shift register 51, a logic circuit 52, and a phase difference correction circuit 200.

  The shift register 51 receives a transfer signal Pi (i = 1,...) From each stage based on an X-side clock signal CLX having a predetermined period, an inverted signal CLXB, and a shift register start signal DX input into the data line driving circuit 101. .., N) are sequentially output.

  The logic circuit 52 includes a pulse width control unit 540, has a function of shaping the transfer signal Pi sequentially output from the shift register 51 based on the enable signals ENB1 to ENB4, and finally outputting the sampling circuit drive signal Si. Have. The logic circuit 52 includes a precharge circuit 521 and buffer circuits 522 and 523 in addition to the pulse width control unit 540.

  The pulse width control unit 540 includes a logic circuit that shapes the waveform of the transfer signal Pi output from the shift register 51. More specifically, the pulse width control unit 540 is configured by unit circuits 540A provided corresponding to each stage of the shift register 51, and the unit circuit 540A is configured by a NAND circuit.

  The transfer signal Pi output from the corresponding stage of the shift register 51 and one of the enable signals ENB1 to ENB4 supplied to the four enable supply lines 81 are input to the gate of the NAND circuit 540A. The NAND circuit 540A shapes the transfer signal Pi by calculating a logical product of the input transfer signal Pi and the enable signals ENB1 to ENB4. Thereby, the NAND circuit 540A generates and outputs a shaped signal Qai that is a signal obtained by shaping the transfer signal Pi. In addition to the NAND circuit, each unit circuit 540A is provided with a transfer signal Pi or enable signals ENB1 to ENB4 input to the NAND circuit and an inverting circuit for inverting the logic of the shaping signal Qai output from the NAND circuit. May be.

  The waveform of the transfer signal Pi is trimmed based on the waveforms of the enable signals ENB1 to ENB4 having a narrower pulse width by the pulse width control unit 540, and finally the pulse shape such as the pulse width and the pulse period is limited.

  As described above, the pulse width control unit 540 is formed by integrating the logic circuits and shaped by the NAND circuit 540A. Therefore, the pulse width control unit 540 can be simplified without increasing the number of circuit elements and wirings. It becomes possible to make it a simple structure. Therefore, it is possible to form the pulse width control unit 540 by reducing the space without substantially increasing the space on the TFT array substrate 10.

  The precharge circuit 521 includes unit circuits 521A provided corresponding to the respective stages of the shift register 51. The unit circuit 521A includes an inversion circuit 521a that inverts the logic of the precharge selection signal NRG supplied to the precharge signal supply line 83, and a precharge selection signal NRG and a shaping signal in which the logic is inverted in the inversion circuit 521a. The NAND circuit 521b to which Qai is input to the gate is substantially formed as a NOR circuit. The NOR circuit 521A calculates the logical sum of the shaping signal Qai and the precharge selection signal NRG, and outputs either the shaping signal Qai or the precharge selection signal NRG as the output signal Qbi. The output signal Qbi output in this way is output as a sampling pulse Si via the buffer circuits 522 and 523.

  According to such a circuit configuration of the logic circuit 52, the precharge circuit 521 can be simplified, and the precharge circuit 521 can be formed without increasing the number of circuit elements or wirings. It becomes possible. As a result, the space for installing the precharge circuit 521 on the TFT array substrate 10 can be further reduced.

  The sampling circuit 7 (see FIG. 1) includes a plurality of sampling switches 7s electrically connected to the data line 6a. Each sampling switch 7s receives the image signal VID supplied to the image signal line 6 shown in FIG. Sampling is performed according to the sampling pulse Si, and each is applied to the data line 6a as a data signal. The sampling switch 7s is constituted by, for example, a P-channel or N-channel single-channel TFT or a complementary TFT.

  In the present embodiment, a case where the number of the image signal lines 6 is one and each of the sampling switches 7s is supplied with the image signal VID from the image signal lines 6 will be described. Phase expansion). For example, when image signals are serial-parallel developed into six phases of image signals VID1 to VID6, these image signals are input to the sampling circuit 7 via six image signal lines, respectively. When parallel image signals obtained by converting serial image signals are simultaneously supplied to a plurality of image signal lines 6, image signals can be input to the data lines 6a for each group, and the drive frequency is suppressed. Is possible.

  The phase difference correction circuit 200 is an example of the “phase difference correction means” in the present invention, and is arranged in the middle of a signal line that supplies the clock signal CLX and the inverted clock signal CLXB. The phase difference correction circuit 200 appropriately adjusts the timing between the clock signal CLX (in other words, the normal clock signal) and the inverted clock signal CLXB. More specifically, the phase difference correction circuit 200 sets the phases of the clock signal CLX and the inverted clock signal CLXB to mutually inverted phases.

  In FIG. 5, the phase difference correction circuit 200 includes a first buffer circuit 201, a bistable circuit 202, and a second buffer circuit 203. The first buffer circuit includes inverters 201a and 201b, the bistable circuit 202 includes inverters 202a and 202b, and the second buffer circuit 203 includes inverters 203a, 203b, 203c, and 203d.

  In FIG. 6, the power supply VDDX is supplied to the source of one transistor 211 constituting each inverter. The power supply VSSX is supplied to the drain of the other transistor 212. That is, the phase difference correction circuit 200 is driven by the power supply potential supplied to the shift register 51 and the like described above.

  Returning to FIG. 5, the phase difference correction circuit 200 supplements the driving capability of the transistor in the circuit that supplies the clock signal CLX and the inverted clock signal CLXB in the buffer circuit 201 including the inverters 201 a and 201 b, and also includes a bistable circuit. In 202, a phase difference in which a phase difference is generated between the phase of the inverted clock signal CLXB and the phase of the clock signal CLX is corrected. Specifically, the output of one inverter 202a of the bidirectional circuit 202 is supplied to the input of the other inverter 202b, and the output of the other inverter 202b is supplied to the input of the one inverter 202a. The configuration is such that the phase difference is eliminated or reduced by applying positive feedback to the input signals of 202a and 202b.

  Further, a second buffer circuit 203 is provided at the subsequent stage of the bistable circuit 202, and the function of the second buffer circuit 203 prevents a reduction in the driving capability of the bistable circuit 202. More specifically, the second buffer circuit 203 prevents the driving capability of the bistable circuit 202 from being lowered. For example, when the clock signal CLX and the inverted clock signal CLXB are respectively supplied from the bistable circuit 202, the second buffer circuit 203 Deterioration of the clock signal CLX and the inverted clock signal CLXB caused by the capacity of the signal line that supplies the signal CLX and the inverted clock signal CLXB is reduced.

  Returning to FIG. 4, the scanning line driving circuit 104 in the electro-optical device according to the present embodiment is electrically connected to the first high potential power supply line 401 and the first low potential power supply line 402. It is driven by supplying VSSY. The scanning line driving circuit 104 is a reference clock for applying a scanning signal in order to scan a plurality of pixel electrodes 9a (see FIG. 3) arranged in a matrix in the array direction of the scanning lines 11a using a data signal and a scanning signal. A scanning signal generated based on the Y-side clock signal CLY, its inverted signal CLYB, and the shift register start signal DY is sequentially applied to the plurality of scanning lines 11a. The scanning line driving circuit 104 is supplied with an enable signal ENBY for shaping the scanning signal.

  Here, in this embodiment, in particular, the first high potential power supply line 401 and the first low potential power supply line 402 that supply power VDDY and VSSY for driving the scanning line drive circuit 104 are the data line drive circuit 101. Is also electrically connected to the buffer circuit 523 in FIG. In other words, the buffer circuit 523 is driven by the power supplies VDDY and VSSY supplied to the scanning line driving circuit 104.

  Each circuit other than the buffer circuit 523 in the data line driving circuit 101 is driven by the power supply VDDX supplied from the second high potential power supply line 403 and the VSSX supplied from the second low potential power supply line. For this reason, the buffer circuit 523 and the phase difference correction circuit 200 are driven by different power supply potentials. Here, the first high potential power supply line 401 and the first low potential power supply line 402 are an example of the “first power potential supply means” of the present invention. The 2 low potential power supply line 404 is an example of the “second power supply potential supply means” in the present invention.

  The power supply VDDY and VSSY can be shared between the scanning line driving circuit 104 and the logic circuit 52 because the frequency of the scanning signal output from the scanning line driving circuit 104 and the data line driving circuit 101 are processed or output. This is because the transfer signal Pi and the frequency of the sampling pulse Si differ greatly to the extent that they do not interfere with each other. Specifically, for example, the clock signal CLY supplied to the scanning line driving circuit 104 is about several tens of kHz, and the clock signal CLX supplied to the data line driving circuit 101 is about several MHz, and between these clock signals, The frequency magnitude is very different.

  Between circuits operating in response to a clock signal having such a frequency difference, the occurrence of waveform disturbance due to clock noise can be reduced to a level where there is no problem in practical use even if the power supply is shared. Therefore, by sharing the power supplies VDDY and VSSY between the scanning line driving circuit 104 and the logic circuit 52, the number of power supplies can be reduced and the circuit configuration can be simplified as compared with the case where power is individually supplied to each circuit. Can do. In addition, signal disturbance due to interference between wirings can be reduced as compared with the case where a number of wirings corresponding to the number of power supply lines are provided to supply a plurality of power supply lines.

  Next, the effect of the electro-optical device according to the present embodiment will be described with reference to FIGS. FIG. 7 is a block diagram illustrating a configuration of the electro-optical device according to the comparative example. 8 is a graph showing waveforms of VSSX and CLX in the electro-optical device according to the comparative example, and FIG. 9 is a partially enlarged view of FIG. 10 is a graph showing waveforms of VSSX and CLX in the electro-optical device according to the present embodiment, and FIG. 11 is a partially enlarged view of FIG.

  In FIG. 7, the scanning line driving circuit 104 is electrically connected to the first high potential power supply line 401 and the first low potential power supply line 402, and all the circuits in the data line driving circuit 101 are It is assumed that the second high potential power supply line 403 and the second low potential power supply line 404 are electrically connected. In this case, the scanning line driving circuit 104 is driven by the power supplies VDDY and VSSY, and the data line driving circuit 101 is driven by the power supplies VDDX and VSSX.

  8 and 9, according to the configuration shown in FIG. 7, the waveform VSS (that is, the power supply VSSX supplied to the phase difference correction circuit 200 is affected by the clock signal CLX in the phase difference correction circuit 200. , Voltage) will be disturbed. Specifically, when the clock signal CLX rises and falls, the voltage of the power supply VSSX is swung up and down. That is, it becomes difficult to keep the power supply VSSX at a constant value.

  Although only the waveforms of the clock signal CLX and the power supply VSSX are illustrated here, the power supply VDDX is similarly affected by the clock signal CLX, and the waveform is disturbed. The inverted clock signal CLXB also affects the power supplies VDDX and VSSX.

  The above-mentioned waveform disturbance makes the operation of the logic circuit 52 (particularly, the buffer circuit 523) supplied with the power supplies VDDX and VSSX unstable, resulting in an image signal output to the data line 6a. Will cause disturbance. Thereby, for example, streaky unevenness or strip-like unevenness may occur in the image displayed in the image display area 10a.

  10 and 11, however, in the electro-optical device according to this embodiment as shown in FIG. 4, as described above, the buffer circuit 523 which is the last stage in the data line driving circuit 101, the phase difference correction circuit 200, and the like. Are driven by different power supply potentials. That is, the buffer circuit 523 is driven by power supplies VSSY and VDDY that are not affected by the clock signal CLX and the inverted clock signal CLXB as shown in the figure. Therefore, the buffer circuit 523 can output a signal to be output with a predetermined waveform and timing. Therefore, the image signal is supplied to each pixel unit at an appropriate timing and with an appropriate waveform, and the occurrence of streak-like unevenness or strip-like unevenness in the image display area can be reduced.

  As described above, according to the electro-optical device according to the first embodiment, the influence of the clock signal CLX and the inverted clock signal CLXB on the power supply potential can be eliminated or reduced, so that a high-quality image can be obtained. It is possible to display.

<Second Embodiment>
Next, an electro-optical device according to a second embodiment will be described with reference to FIGS. FIG. 12 is a block diagram illustrating a specific configuration of the electro-optical device according to the second embodiment, and FIG. 13 is a timing chart illustrating waveforms of signals in the electro-optical device according to the comparative example. The second embodiment differs from the first embodiment described above in the configuration of the power supply wiring, and the other configurations are generally the same. Therefore, in the second embodiment, portions different from the first embodiment will be described in detail, and descriptions of other overlapping portions will be omitted as appropriate.

  In FIG. 12, in the electro-optical device according to the second embodiment, the scanning line driving circuit 104 and the logic circuit 52 are electrically connected to the first high potential power supply line 401 and the first low potential power supply line 402. The shift register 51 and the phase difference correction circuit 200 are electrically connected to the second high potential power supply line 403 and the second low potential power supply line 404. That is, in the second embodiment, each circuit other than the buffer circuit 523 included in the logic circuit 52 is driven by the power supplies VDDY and VSSY as compared to the first embodiment described above. As a result, the logic circuit 52 and the phase difference correction circuit 200 are driven by different power sources.

  In FIG. 13, the influence of the clock signal CLX and the inverted clock signal CLXB on the power supplies VDDX and VDDY extends even when the NAND circuit 540A calculates the logical product of the transfer signal Pi and the enable signals ENB1 to ENB4. As a result, distortion due to disturbance of the power supplies VDDX and VDDY occurs in A (ENB1) to A (ENB4), which is the logical product of the transfer signal Pi and the enable signals ENB1 to ENB4. Such distortion may cause the quality of the image displayed in the image display area 10a to deteriorate.

  However, in the electro-optical device according to the second embodiment, as described above, the logic circuit 52 and the phase difference correction circuit 200 are driven by different power sources. Therefore, it is possible to prevent distortion caused by disturbance of the power supplies VDDX and VDDY in the logical products A (ENB1) to A (ENB4). Accordingly, it is possible to more effectively reduce the occurrence of stripe-like unevenness or strip-like unevenness in the image display area.

  As described above, according to the electro-optical device according to the second embodiment, the influence of the clock signal CLX and the inverted clock signal CLXB on the logic circuit 52 can be eliminated or reduced, so that a high-quality image can be obtained. It is possible to display.

<Third Embodiment>
Next, an electro-optical device according to a third embodiment will be described with reference to FIG. FIG. 14 is a block diagram illustrating a specific configuration of the electro-optical device according to the third embodiment. The third embodiment is different from the first and second embodiments described above in the configuration of the power supply wiring, and the other configurations are generally the same. For this reason, in 3rd Embodiment, a different part from each embodiment mentioned above is demonstrated in detail, and description is abbreviate | omitted suitably about another overlapping part.

  In FIG. 14, in the electro-optical device according to the third embodiment, the scanning line driving circuit 104 and the phase difference correction circuit 200 are electrically connected to the first high potential power supply line 401 and the first low potential power supply line 402. The other circuits in the data line driving circuit 101 other than the phase difference correction circuit 200 are electrically connected to the second high potential power supply line 403 and the second low potential power supply line 404. As a result, the shift register 51, the logic circuit 52, and the phase difference correction circuit 200 are driven by different power sources.

  In the third embodiment, unlike the first and second embodiments described above, the phase difference correction circuit 200 is driven by the power supplies VDDY and VSSY. Therefore, here, the first high-potential power supply line 401 and the first low-potential power supply line 402 are an example of the “second power supply potential supply means” of the present invention. The low potential power supply line 404 is an example of the “first power supply potential supply means” in the present invention.

  In the third embodiment, since the phase difference correction circuit 200 is driven by the power supplies VDDY and VSSY, the power supply VDDY and VSSY include the clock signal CLXB and the inverted clock signal as in the power supply VSSX shown in FIGS. Disturbance resulting from CLXB will occur. However, since the power supplies VDDX and VSSX are not supplied to the phase difference correction circuit 200, the disturbance is reduced like the power supply VSSY shown in FIGS. Thus, the shift register 51 and the logic circuit 52 driven by the power supplies VDDX and VSSX are not affected by the clock signal CLXB and the inverted clock signal CLXB. Therefore, it becomes possible to output a signal with an appropriate waveform at an appropriate timing, and the occurrence of streak-like unevenness or strip-like unevenness in the image display area can be reduced.

  As described above, according to the electro-optical device according to the third embodiment, a high-quality image can be displayed more reliably.

<Electronic equipment>
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described. FIG. 15 is a plan view showing a configuration example of the projector. Hereinafter, a projector using the liquid crystal device as a light valve will be described.

  As shown in FIG. 15, a projector 1100 includes a lamp unit 1102 made up of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R and 1110B.

  In addition, since light corresponding to each primary color of R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  In addition to the electronic device described with reference to FIG. 15, a mobile personal computer, a mobile phone, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic device Examples include a notebook, a calculator, a word processor, a workstation, a videophone, a POS terminal, and a device equipped with a touch panel. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal devices described in the above embodiments, the present invention includes a reflective liquid crystal device (LCOS), a plasma display (PDP), a field emission display (FED, SED), an organic EL display, and a digital micromirror device. (DMD), electrophoresis apparatus and the like are also applicable.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification, and an electro-optical device with such a change. In addition, an electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

1 is a plan view showing an overall configuration of an electro-optical device according to a first embodiment. It is the HH 'sectional view taken on the line of FIG. FIG. 3 is an equivalent circuit diagram of various elements, wirings, and the like in a plurality of pixels formed in a matrix that forms an image display region of the electro-optical device according to the first embodiment. FIG. 3 is a block diagram illustrating a specific configuration of the electro-optical device according to the first embodiment. It is a circuit diagram which shows the structure of a phase difference correction circuit. It is a circuit diagram which shows the structure of the inverter in a phase difference correction circuit. It is a block diagram which shows the structure of the electro-optical apparatus which concerns on a comparative example. 6 is a graph showing waveforms of VSSX and CLX in an electro-optical device according to a comparative example. It is the elements on larger scale of FIG. 6 is a graph showing waveforms of VSSX and CLX in the electro-optical device according to the first embodiment. It is the elements on larger scale of FIG. FIG. 6 is a block diagram illustrating a specific configuration of an electro-optical device according to a second embodiment. 6 is a timing chart showing waveforms of signals in an electro-optical device according to a comparative example. FIG. 10 is a block diagram illustrating a specific configuration of an electro-optical device according to a third embodiment. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  3a ... scanning line, 6 ... image signal line, 6a ... data line, 7 ... sampling circuit, 7s ... sampling switch, 9a ... pixel electrode, 10 ... TFT array substrate, 10a ... image display area, 20 ... counter substrate, 30 ... TFT, 50 ... Liquid crystal layer, 51 ... Shift register, 52 ... Logic circuit, 83 ... Precharge signal supply line, 101 ... Data line drive circuit, 102 ... External circuit connection terminal, 104 ... Scanning line drive circuit, 200 ... Phase difference correction circuit 201 ... first buffer circuit 202 ... bistable circuit 203 ... second buffer circuit 401 ... first high potential power supply line 402 ... first low potential power supply line 403 ... second high Potential power supply line, 404 ... second low potential power supply line, 521 ... precharge circuit, 522,523 ... buffer circuit, 540 ... pulse width control unit

Claims (6)

On the board
A pixel region composed of a plurality of pixels;
Image signal output means having an output circuit for outputting an image signal to the pixel region;
In the image signal output means, a phase difference correction means for correcting a phase difference between a clock signal that synchronizes the timing of outputting the image signal and an inverted clock signal obtained by inverting the phase of the clock signal;
First power supply potential supply means for supplying a power supply potential to the output circuit;
An electro-optical device comprising: a second power supply potential supply unit that supplies a power supply potential to the phase difference correction unit. The image signal output means has another circuit provided in the preceding stage of the output circuit,
The electro-optical device according to claim 1, wherein the first power supply potential supply unit supplies a power supply potential to the other circuit in addition to the output circuit. A plurality of scanning lines and data lines provided to correspond to the plurality of pixels;
The electro-optical device according to claim 1, wherein the output circuit is electrically connected to the data line. Scanning signal output means for outputting a scanning signal to the scanning line;
The electro-optical device according to claim 3, wherein the first power supply potential supply unit supplies a power supply potential to the scanning signal output unit in addition to the output circuit. Scanning signal output means for outputting a scanning signal to the scanning line;
The electro-optical device according to claim 3, wherein the second power supply potential supply unit supplies a power supply potential to the scanning signal output unit in addition to the phase difference correction unit.   An electronic apparatus comprising the electro-optical device according to claim 1.

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