JP4529484B2 - Electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device and an electronic apparatus such as a liquid crystal projector including the same.

In this type of electro-optical device, for example, as a liquid crystal device, a plurality of pixel portions connected to a plurality of scanning lines and data lines, a data line driving circuit for driving the data lines, and a scanning line are provided on a substrate. A scanning line driving circuit for driving, a sampling circuit for sampling an image signal, and the like are built in. At the time of the operation, the sampling circuit samples the image signal supplied onto the image signal line and supplies it to the data line at the timing of the sampling circuit drive signal supplied from the data line drive circuit.
Also, in order to realize high-definition image display while suppressing an increase in drive frequency, serial image signals are converted into a plurality of parallel image signals such as 3-phase, 6-phase, 12-phase, 24-phase, etc. A technique is applied in which the data lines are supplied to the data lines via a plurality of image signal lines after (ie, phase expansion). In this case, a plurality of image signals are simultaneously sampled by a plurality of sampling switches and are simultaneously supplied to a plurality of data lines. In this specification, such conversion is referred to as “serial-parallel conversion”.

  In performing such phase development, an enable circuit is further introduced in the electro-optical device. The enable circuit is a circuit that takes the logical product of each sampling circuit drive signal and the enable signal so that the sampling circuit drive signals that precede and follow overlap each other and the sampling switch does not malfunction. The pulse width of the signal is reduced to the pulse width of the enable signal. Normally, the output of the enable circuit is called a sampling circuit drive signal, and the original signal input to the enable circuit is distinguished as a transfer signal. When the pulse width is limited in this way, a slight time interval is generated as a time margin between two adjacent sampling circuit drive signals. For this reason, along with high-frequency driving, on-resistance in active elements such as thin film transistors (hereinafter referred to as “TFT” as appropriate) constituting a sampling circuit, data line driving circuit, etc., wiring resistance of various wirings, capacitance in elements and wirings, Even if the adverse effect such as delay is relatively increased, the adverse effect can be reduced (see, for example, Patent Document 1).

JP 2000-47643 A JP 2000-242237 A JP 2000-227784 A

  However, in this type of electro-optical device, high-frequency noise is generated in the image signal line, which affects the unit of data lines that are driven simultaneously by phase expansion, and therefore causes periodic vertical stripes on the screen. There is a technical problem that the display quality is deteriorated. As will be described later, in the observation by the inventor of the present invention, such high-frequency noise is generated mainly in response to rising and falling of the clock signal, and is considered to be caused by crosstalk between wirings and the like.

  The present invention has been made in view of, for example, the above-described problems. When a plurality of data lines are driven at the same time, noise in an image signal line that is manifested in a group unit including data lines that are driven at the same time. It is an object to provide an electro-optical device such as a liquid crystal device and an electronic apparatus such as a liquid crystal projector that can reduce display defects based on the above.

In order to solve the above problems, an electro-optical device of the present invention has a plurality of scanning lines and a plurality of data lines arranged in a crossing manner in an image display region on a substrate, the plurality of scanning lines, and the plurality of data. A plurality of pixel portions arranged corresponding to each intersection with the line, and a plurality of image signal lines to which an image signal is supplied to a peripheral region located around the image display region; and the image signal line A sampling circuit that samples the image signal according to a sampling circuit drive signal and supplies the image signal to the plurality of data lines, a shift register that sequentially outputs a transfer signal from each stage based on a clock signal having a predetermined period, and a predetermined pulse width pulses of the signal pulse width is delayed by short and predetermined time for a enabling signal said clock signal, and outputs the further delayed relative to the clock signal And control circuit for each stage of the shift register, the logical product of the enable signal output the transfer signal outputted by being delayed from the pulse control circuit with respect to the clock signal from each stage of said shift register An enable circuit that supplies the sampling circuit as the sampling circuit drive signal, and the pulse control circuit is formed in the same process as an inverter provided on the output path of the transfer signal in each stage of the shift register. It is composed of the same number of inverters.

  According to the electro-optical device of the present invention, during the operation, a transfer signal is sequentially output from each stage based on a clock signal having a predetermined period by the shift register. In parallel with this, an enable signal having a predetermined pulse width supplied from the outside or previously generated in the peripheral circuit is output after being delayed or distorted by the pulse control circuit. Subsequently, for each stage of the shift register, the enable circuit calculates the logical product of the delayed or distorted enable signal and the transfer signal, and supplies the logical product to the sampling circuit as a sampling circuit drive signal. Is done. At this time, the “predetermined pulse width” of the enable signal is set to be shorter than the pulse width of the clock signal, so that the sampling circuit drive signals supplied adjacent to each other do not overlap each other. Alternatively, for example, the “predetermined pulse width” of the enable signal is set to a half width of the pulse width of the clock signal, so that the drive frequency of the sampling circuit drive signal is double the frequency of the transfer signal. More generally, the predetermined width of the enable signal is set to a width equal to n (n is a natural number of 2 or more) of the pulse width of the clock signal, so that the drive frequency of the sampling circuit drive signal is set to the transfer signal. The frequency is n times. Subsequently, in the sampling circuit, the image signal supplied from the outside is sampled and supplied to the data line in accordance with the sampling circuit drive signal. Subsequently, in the image display area, light is modulated in each pixel unit in accordance with the image signal supplied from the data line, and image display is performed.

  Here, according to the research of the inventors of the present invention, high-frequency noise generated in synchronism with the rise and fall of the clock signal is observed on the image signal line during such driving. This high-frequency noise is considered to be due to electrical interaction such as parasitic capacitance between the wiring for drawing the clock signal from the outside to the data line driving circuit and the image signal line, and the n number of simultaneously driven It is considered that the data lines are visualized as regular vertical stripes on the screen by superimposing them on the image signal.

  However, in the present invention, the enable signal is delayed or distorted by the pulse control circuit. Therefore, little or no image signal is sampled during the rising period of the clock signal where noise is likely to occur on the image signal as described above. That is, almost no adverse effects due to noise generated during the rising period are brought into the sampled image signal. Accordingly, the pixel portion can display a high-quality image with reduced display spots based on the image signal with reduced noise.

  The enable signal is preferably delayed until the noise on the image signal line is almost converged because the noise component superimposed on the image signal is reduced according to the delay amount. Even if the waveform is distorted without delay, the sampling circuit drive signal is distorted, so that a substantial sampling delay occurs, and an effect of reducing noise components can be obtained. Therefore, the pulse control circuit may be any circuit as long as it gives a delay or distortion to the enable signal. For example, the pulse control circuit may be configured as an inverter circuit or a circuit used as a normal delay circuit.

  Furthermore, according to the research of the inventors of the present invention, the transfer signal is delayed or distorted according to the characteristics of the transistors constituting the shift register while passing through the shift register. In addition, the convergence time of the noise derived from the clock signal in the image signal line is also extended. Therefore, for example, even if an enable signal delayed in advance is input, the relative delay amount of the enable signal with respect to the transfer signal and noise may be smaller than an assumed amount. On the other hand, in the present invention, since the delay amount of the enable signal is adjusted in the device by the pulse control circuit, it is possible to absorb the influence of the transistor in the device on the noise.

  As a result of the above, according to the electro-optical device of the present invention, it is possible to display a high-quality image in which display spots generated at the interval between the data lines that are driven simultaneously are reduced due to noise derived from the clock signal. It becomes.

  In order to solve the above-described problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention.

  Since the electronic apparatus of the present invention includes the above-described electro-optical device of the present invention, a liquid crystal device capable of high-quality image display, an electrophoretic device such as electronic paper, and a display device using an electron-emitting device (Field Emission Display and Surface-Conduction Electron-Emitter Display), various display devices such as display devices using DMD (Digital Micromirror Device), projectors, television receivers, mobile phones, electronic notebooks, word processors, viewfinder type or Various electronic devices such as a monitor direct-view video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized.

  Such an operation and other advantages of the present invention will become apparent from the embodiments described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
First, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an overall block diagram of a liquid crystal device as an example of an electro-optical device including a data line driving circuit. FIG. 2 is a circuit diagram of the data line driving circuit, and FIG. 3 is a timing chart of various signals in the data line driving circuit. In this embodiment, the present invention is applied to a liquid crystal device of an active matrix driving system by TFT driving.

  In FIG. 1, the liquid crystal device 200 includes a liquid crystal display unit 1 a in which liquid crystal is sealed between a pair of substrates, a data line driving circuit 101, a scanning line driving circuit 104, and a sampling circuit 301. These drive circuits and the like are provided in a peripheral region located on the periphery of the TFT array substrate 10 made of, for example, a quartz substrate, a glass substrate, or a silicon substrate. In the screen display region located at the center on the TFT array substrate 10, a plurality of pixel electrodes 11 arranged in a matrix, a plurality of data lines 35 arranged in the X direction and extending along the Y direction, A plurality of scanning lines 31 arranged in the Y direction and extending along the X direction are formed, and the liquid crystal display unit 1a is constructed. Although not shown here, between each pixel electrode 11 and the data line 35, a TFT whose conduction state and non-conduction state are controlled according to a scanning signal supplied via the scanning line 31 respectively. In addition, a capacitor wiring for a storage capacitor that maintains a voltage applied to the pixel electrode 11 for a long time is formed.

  The data line driving circuit 101 drives the sampling circuit 301 to convert the image signals VID1 to VID6 supplied from the image signal line 400 into the X-side clock signal CLX (and its inverted clock CLX) that is a reference clock signal for data signal application. Sampling is performed according to ') and applied to the data lines 35 as data signals. That is, the image signals VID <b> 1 to VID <b> 6 are serially / parallel-developed into six phases by an external image signal processing circuit and input to the sampling circuit 301 via the six image signal lines 400. Six sampling circuit drive signals Si (i = 1,..., N) whose pulse width is limited by the enable circuit in the data line drive circuit 101 are passed through the sampling circuit drive signal lines 306 branched into six. Are input to the adjacent sampling switch 302. Therefore, the sampling circuit 301 is driven simultaneously for each group of these six sampling switches 302.

  The scanning line driving circuit 104 performs scanning in the liquid crystal display unit 1a including a plurality of pixel units arranged in a matrix so as to perform vertical scanning in a direction perpendicular to the scanning line 31 (Y direction) by a data signal and a scanning signal. A scanning signal is sequentially applied to the plurality of scanning lines 31 based on a Y-side clock signal CLY (and its inverted clock CLY ′) that is a reference clock for signal application.

  The sampling circuit 301 includes a plurality of sampling switches 302 connected to the plurality of data lines 35, respectively. Any one of the image signals VID1 to VID6 is supplied to each sampling switch 302, and each sampling switch 302 is sequentially closed by a transfer signal from a later-described shift register circuit included in the data line driving circuit 101. That is, the image signals VID <b> 1 to VID <b> 6 are sampled for each data line 35 according to the transfer signal and applied to the plurality of data lines 35 as data signals, respectively.

  More specifically, the sampling switch 302 is composed of, for example, a P-channel or N-channel single-channel TFT or a complementary TFT, and the image signal line 400 is connected to the source electrode of the sampling switch 302. The sampling circuit drive signal line 306 is connected to the gate electrode of the sampling switch 302. When the image signals VID1 to VID6 are input via the image signal line 400 and the sampling circuit driving signal Si is input from the data line driving circuit 101 via the sampling circuit driving signal line 306, the image inputs VID1 to VID6 are input. Is sampled and applied to each data line 35.

  Next, the configuration of the data line driving circuit 101 will be described in detail with reference to FIGS.

  2, the data line driving circuit 101 includes a shift register circuit 500 including a plurality of stages, a plurality of enable circuits 502, and a pulse control circuit 503.

  As shown in FIG. 2, the shift register circuit 500 sequentially outputs transfer signals Ai (i = 1, 2, 3,...) From each stage in a transfer direction corresponding to the direction from left to right. Three clocked inverters 501 that feed back the transfer signal and transfer it to the next stage each time the binary level of the clock signal CLX and its inverted signal CLX ′ supplied from an external image signal processing device changes. Each is composed. Note that a shift register start signal DX for starting transfer of the transfer signal Ai is input to the shift register circuit 500 from the left side in the figure, and a power supply voltage necessary for driving each clocked inverter 501 is also supplied from the outside. It is configured to be.

  The enable circuit 502 calculates a logical product of the transfer signals A1, A2, A3,... And any one of the enable signals ENB1 to ENB4, and outputs them to the sampling drive signal line 306 as sampling circuit drive signals S1, S2, S3,. Is configured to do. More specifically, as shown in FIG. 2, the enable circuit 502 applies the transfer signals A1, A2, A3,..., Which are respectively inputted, at the pulse application timing of any one of the enable signals ENB1, ENB2, ENB3, and ENB4. A NAND circuit 505 that outputs as the sampling and sampling circuit drive signals S1, S2, S3,... The enable signals ENB1 to ENB4 have only about half the pulse width of the clock signal CLX or the inverted signal CLX 'as shown in FIG. 3, and are output so as to correspond to the first half and the second half of one transfer signal Ai. Therefore, the obtained sampling circuit drive signals S1, S2, S3,... Are multiplied by the transfer signal Ai. Furthermore, in the present embodiment, a slight time interval is provided in advance between the enable signals ENB1 to ENB4 in order to prevent mutual time overlap.

  In the present embodiment, the enable signals ENB 1 to ENB 4 are input to the pulse control circuit 503 in the previous stage of the enable circuit 502. The pulse control circuit 503 is configured to provide the enable signals ENB1 to ENB4 with a delay and distortion larger than the delay and distortion that the transfer signal Ai (i = 1, 2, 3,...) Receives from each stage of the shift register circuit 500. Has been. Specifically, since the pulse control circuit 503 includes three inverters connected in series and is larger in number than two clocked inverters 501 (that is, inverters that contribute to the delay of the transfer signal Ai), The delay and distortion of the enable signals ENB1 to ENB4 are configured to be larger than the transfer signal Ai by passing therethrough. Thus, in order to set the delay characteristic in the pulse control circuit 503 to be equal to or higher than that of the clocked inverter 501, it is considered that the number of inverters equal to or higher than that of the clocked inverter 501 is sufficient. The inverter 501 does not necessarily have the same configuration. However, in addition to simply providing a difference in characteristics, in order to control the difference in characteristics by the number of circuits, it is necessary to make the characteristics of the transistors constituting each inverter substantially equal, and the pulse control circuit 503, the shift register circuit 500, Are preferably formed in the same step. Hereinafter, signals input to the pulse control circuit 503 are referred to as enable signals ENB1 to ENB4, and outputs from the pulse control circuit 503 corresponding to the enable signals ENB1 to ENB4 are referred to as enable signals ENB11 to ENB14. It shall be.

  Here, operations of the shift register circuit 500, the enable circuit 502, and the pulse control circuit 503 will be described with reference to FIG.

  When the start signal DX and the clock signal CLX (and its inverted signal CLX ′) are input at the timing shown in the timing chart of FIG. 3, the transfer signal A1 is sequentially delayed from the shift register circuit 500 by the period of the clock signal CLX. , A2, A3,... Are sequentially output. On the other hand, the enable signals ENB1 to ENB4 are initially input into the data line driving circuit 101 during the application period based on the clock signal CLX. However, the pulse control circuit 503 delays the waveform by an amount corresponding to the rising period Δt1. Distortion is caused and input to the enable circuit 502 as enable signals ENB11 to ENB14. Then, in the enable circuit 502, the pulse widths of the transfer signals A1, A2, A3,... Are limited to the pulse widths of the enable signals ENB11 to ENB14, and the respective sampling circuit drive signals S1, S2, S3,. Sequentially supplied to the circuit 301.

  Here, the transfer signal Ai actually has a slight delay with respect to the clock signal CLX and is distorted due to the characteristics of the TFT in the clocked inverter 501, and requires a period Δtr to rise. During this driving, high-frequency noise is generated in the image signal line 400 substantially in synchronization with the rise and fall of the clock signal CLX. This high frequency noise is considered to be caused by crosstalk between the image signal line 400 and the wiring for supplying the clock signal CLX from the outside, the wiring for transmitting the transfer signal Ai, and the like. The time required for convergence differs depending on the characteristics of the TFT in the clocked inverter 501. That is, the noise generation period Δtn here can be regarded as having a correspondence relationship with the degree of distortion of the transfer signal Ai, specifically, the rising period Δtr of the transfer signal Ai. Therefore, in the present embodiment, the rising period Δt1 of the enable signals ENB11 to ENB14 is set to be longer than the rising period Δtr of the transfer signal Ai, and the enable signals ENB11 to ENB14 rise after the transfer signal Ai ( Δt1> Δtr).

  Therefore, high frequency noise can be excluded from the image signals VID1 to VID6 sampled based on the sampling circuit drive signals S1, S2, S3,... Generated based on the delayed enable signals ENB11 to ENB14. If such delay is not applied to the sampling circuit drive signals S1, S2, S3,..., The six sampling switches 302 of the sampling circuit 301 include the image signals VID1 to VID6 including a period in which high-frequency noise is superimposed. The data is sampled and supplied to the data line 35. As a result, image signals VID1 to VID6 including noise are supplied for each of the six data lines 35 corresponding to the number of phase expansions, and display spots of this width are visually recognized. That is, here, such display spots can be improved or eliminated.

  As described above, according to the present embodiment, it is possible to effectively prevent the adverse effect of crosstalk or the like on the display even in the case of high frequency driving by the action of the pulse control circuit 503. In particular, since the pulse control circuit 503 is built in the liquid crystal device 200, it is possible to absorb a change in noise derived from peripheral circuits such as the TFT characteristics described above, and to accurately delay and distort the enable signal. Can be given.

<Second Embodiment>
Next, a second embodiment will be described with reference to FIGS. 4 is an overall block diagram of a liquid crystal device as an example of an electro-optical device, FIG. 5 is a circuit diagram showing a configuration of the data line driving circuit 101, and FIG. 6 is a diagram of various signals in the data line driving circuit. It is a timing chart.

  In the present embodiment, the enable signals ENB1 to ENB4 generated by the external circuit at a timing delayed from the rising edge of the clock signal CLX are supplied to the data line driving circuit 101, and the delays given to the enable signals ENB1 to ENB4 and The second embodiment is the same as the first embodiment except that the pulse amount control circuit is set so that the distortion amount is equivalent to the delay and distortion amount of the transfer signal Ai in the shift register circuit 500. Therefore, in the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  As shown in FIG. 4, the clock signal CLX input to the data line driving circuit 101, its inverted signal CLX ′, the start signal DX and the enable signal ENB, and the clock signal CLY input to the scanning line driving circuit 104, Various timing signals such as the inversion signal CLY ′ and the start signal DY are generated by, for example, the timing generator 600 and supplied to the drive circuit on the TFT array substrate 10 via the external circuit connection terminal. The timing generator 600 generates the enable signals ENB1 to ENB4 based on the clock signal CLX. Here, the timing generator 600 is configured to generate and output the enable signals ENB1 to ENB4 with a delay of Δt2 from the clock signal CLX.

  As shown in FIG. 5, the enable signals ENB 1 to ENB 4 are the same as the delay and distortion that the transfer signal Ai (i = 1, 2, 3,...) Receives from each stage of the shift register circuit 500 in the pulse control circuit 504. The signals are output as enable signals ENB21 to ENB24 with a certain delay and distortion. Specifically, the pulse control circuit 504 includes two inverters connected in series, and enables the same delay and distortion as two clocked inverters 501 (that is, an inverter that contributes to the delay of the transfer signal Ai). The signals ENB1 to ENB4 are configured to be given. In this way, in order to set the delay characteristic in the pulse control circuit 504 to be equal to that of the clocked inverter 501, it is considered sufficient to use the same number of inverters as the clocked inverter 501, and the configuration of each inverter is changed to the clocked inverter 501. The inverter 501 does not necessarily have the same configuration. For example, the actual clocked inverter 501 is a latch circuit composed of a large number of transistors, but each inverter of the pulse control circuit 504 may be configured by a very simple inverter circuit composed of one complementary TFT.

  Here, operations of the shift register circuit 500, the enable circuit 502, and the pulse control circuit 504 will be described with reference to FIG.

  When the start signal DX and the clock signal CLX (and its inverted signal CLX ′) are input at the timing shown in the timing chart of FIG. 6, transfer signals A1, A2, A3,. Is output. Since the transfer signal Ai involves delay and distortion with respect to the clock signal CLX, a period Δtr is required for rising.

  On the other hand, the enable signals ENB1 to ENB4 are input into the data line driving circuit 101 with a delay of Δt2 from the clock signal CLX, respectively. However, the pulse control circuit 504 further delays the waveform by an amount corresponding to the rising period Δt3. Distortion is caused and input to the enable circuit 502 as enable signals ENB21 to ENB24. In the present embodiment, due to the configuration of the pulse control circuit 504, the rising period Δt3 is almost equal to the rising period tr of the transfer signal Ai (Δt3 = tr). Therefore, the enable signals ENB21 to ENB24 are signals that are surely delayed by the delay amount Δt2 of the enable signal ENB compared to the transfer signal Ai (Δt2 + Δt3> Δtr).

  That is, the pulse control circuit 504 applies a bias to the enable signals ENB1 to ENB4 and aligns the delay or distortion with the transfer signal Ai so that the effect of the delay or distortion of the enable signals ENB1 to ENB4 (that is, removal of high frequency noise). The effects of the delay and distortion of the transfer signal Ai with respect to) are relatively offset. At the same time, the delay or distortion for removing the high frequency noise is applied to the enable signals ENB1 to ENB4 by the timing generator 600. If only the delay Δt2 by the timing generator 600 is added to the enable signals ENB1 to ENB4, the noise removal effect is relatively reduced by an amount not considering the delay of the transfer signal Ai.

  The enable signals ENB21 to ENB24 regulate the pulse width of the sampling circuit drive signals S1, S2, S3,..., So that high frequency noise can be eliminated from the sampled image signals VID1 to VID6. In particular, if the preset delay amount Δt2 is set to be equal to or greater than the noise generation period Δtn, the noise on the image signal line 400 is almost completely removed regardless of the delay of the transfer signal Ai, and the image signals VID1 to VID1. VID6 can be sampled. Therefore, in this case as well, display spots can be improved or eliminated.

  As described above, according to the second embodiment, the delay or distortion of the transfer signal Ai is taken into consideration by giving the enable signals ENB1 to ENB4 delay or distortion in two stages with respect to the first embodiment. Therefore, noise can be accurately removed. Since the delay amount of the enable signals ENB1 to ENB4 with respect to noise is defined only by the delay amount Δt2 by the timing generator 600, the delay amount of the enable signals ENB1 to ENB4 can be set appropriately and simply here. Become.

  In the above embodiment, the case where the four enable signals ENB1 to ENB4 are used has been described. However, the circuit configuration of the data line driving circuit according to the present invention is not limited to the above embodiment. The enable signal is supplied to the data line driving circuit as a function that defines the application timing and pulse width of the transfer signal, for example, for the normally expected function, that is, for preventing the overlap between the transfer signals and multiplying the frequency. What is necessary is just to be provided, and not only four but two, if possible, only one may be supplied.

<Overall configuration of liquid crystal device>
The overall configuration of each embodiment of the liquid crystal device configured as described above will be described with reference to FIGS. FIG. 7 is a plan view of the TFT array substrate 10 as viewed from the side of the counter substrate 20 together with the components formed thereon. FIG. It is H 'sectional drawing.

  7 and 8, the counter substrate 20 is disposed opposite to the TFT array substrate 10. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are sealed by a sealing material 52 provided in a seal region located around the image display region. They are glued together.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like for bonding the two substrates, and is applied on the TFT array substrate 10 in the manufacturing process and then cured by ultraviolet irradiation, heating, or the like. It is. In the sealing material 52, a gap material such as glass fiber or glass beads for dispersing the distance (inter-substrate gap) between the TFT array substrate 10 and the counter substrate 20 to a predetermined value is dispersed. In addition, a light-shielding frame light-shielding film 53 that defines the frame area of the image display area is provided on the counter substrate 20 side in parallel with the inside of the seal area in which the sealing material 52 is disposed. However, part or all of the frame light shielding film 53 may be provided as a built-in light shielding film on the TFT array substrate 10 side.

  A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 outside the area where the sealing material 52 is arranged in the peripheral area located around the image display area. ing. The scanning line driving circuit 104 is provided along two sides adjacent to the one side so as to be covered with the frame light shielding film 53. Further, in order to connect the two scanning line driving circuits 104 provided on both sides of the image display area in this way, a plurality of the light-shielding films 53 are covered along the remaining side of the TFT array substrate 10 and covered with the frame light-shielding film 53. A wiring 105 is provided.

  In addition, vertical conduction members 106 that function as vertical conduction terminals between the two substrates are disposed at the four corners of the counter substrate 20. On the other hand, the TFT array substrate 10 is provided with vertical conduction terminals in a region facing these corner portions. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  In FIG. 8, on the TFT array substrate 10, a pixel electrode 11 is formed on a pixel switching TFT, various wirings, and the like, and an alignment film is formed thereon. On the other hand, on the counter substrate 20, in addition to the counter electrode 21, a lattice-shaped or striped light-shielding film 23 is formed, and an alignment film is further formed thereon. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  Although not shown here, a sampling circuit 301 is formed on the TFT array substrate 10 in addition to the data line driving circuit 101 and the scanning line driving circuit 104. In addition to this, a precharge circuit that supplies a precharge signal of a predetermined voltage level to a plurality of data lines in advance of the image signal, and the quality, defects, etc. of the electro-optical device during manufacture or at the time of shipment An inspection circuit or the like for inspection may be formed. In addition, for example, the TN (twisted nematic) mode, the STN (super TN) mode, and the D-STN (double- A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as an STN mode or a normally white mode / normally black mode.

<Electronic equipment>
Next, the case where the liquid crystal device described above is applied to various electronic devices will be described.

  (Projector) First, a projector in which a liquid crystal device as an example of the “electro-optical device” of the present invention is applied to a light valve will be described. FIG. 9 is a plan view showing a configuration example of the projector. As shown in the figure, a projector 1100 is provided with a lamp unit 1102 composed of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. It enters the liquid crystal devices 1110R, 1110B, and 1110G. The configurations of the liquid crystal devices 1110R, 1110B, and 1110G are the same as, for example, the liquid crystal devices in the above-described embodiments. In each of them, R, G, and B primary color signals supplied from an image signal processing circuit (not shown) are modulated. The Light modulated by these liquid crystal devices is incident on the dichroic prism 1112 from three directions. In the dichroic prism 1112, R and B light is refracted by 90 degrees, while G light travels straight. As a result, the images of the respective colors are synthesized and a color image is projected onto the screen or the like via the projection lens 1114.

  (Mobile Computer) Next, an example in which the liquid crystal device as the electro-optical device is applied to a mobile personal computer will be described. FIG. 10 is a perspective view showing the configuration of this personal computer. The personal computer 1200 includes a main body 1204 having a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 has a configuration in which a backlight is added to the above-described liquid crystal device 1005 as an electro-optical device.

  (Mobile Phone) An example in which the liquid crystal device as the electro-optical device is applied to a mobile phone will be described. FIG. 11 is a perspective view showing the configuration of this mobile phone. A cellular phone 1300 in the figure includes a liquid crystal device 1005 together with a plurality of operation buttons 1302 and a built-in circuit. Here, the liquid crystal device 1005 is of a reflective type, and a front light is provided on the front surface thereof as necessary.

  In the above, the electro-optical device of the present invention has been specifically described by taking a liquid crystal device as an example. However, the electro-optical device of the present invention also includes a display device using DMD (Digital Micromirror Device), an electric device, and the like. It can be widely applied to electrophoresis devices, display devices using electron-emitting devices (Field Emission Display and Surface-Conduction Electron-Emitter Display), and the like.

  In addition to the above-described electronic apparatus, the electro-optical device of the present invention includes a television receiver, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, a pager, and an electronic notebook. It can be applied to a calculator, a word processor, a workstation, a video phone, a POS terminal, a device equipped with a touch panel, and the like.

  The present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification, and an electro-optical device with such a change, In addition, an electronic device including the same is also included in the technical scope of the present invention.

1 is a block diagram illustrating an overall configuration of an electro-optical device according to a first embodiment of the invention. FIG. 2 is a circuit diagram of a data line driving circuit in FIG. 1. 3 is a timing chart of the data line driving circuit shown in FIG. 2. It is a block diagram showing the whole structure of the electro-optical apparatus which concerns on 2nd Embodiment. FIG. 5 is a circuit diagram of a data line driving circuit in FIG. 4. 14 is a timing chart of the data line driving circuit shown in FIG. It is a top view which shows the whole structure of an electro-optical apparatus. It is HH 'sectional drawing of FIG. It is sectional drawing which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied. 1 is a cross-sectional view illustrating a configuration of a personal computer as an example of an electronic apparatus to which an electro-optical device is applied. It is sectional drawing which shows the structure of the mobile telephone which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a ... Liquid crystal display part, 10 ... TFT substrate, 11 ... Pixel electrode, 31 ... Scan line, 35 ... Data line, 101 ... Data line drive circuit, 104 ... Scan line drive circuit, 301 ... Sampling circuit, 400 ... Image signal line , 500 ... Shift register circuit, 501 ... Clocked inverter, 502 ... Enable circuit, 503 ... Pulse control circuit, 600 ... Timing generator, CLX ... Clock signal, A1, A2, A3 ... Transfer signal, ENB, ENB1, ENB2 ... Enable Signal, S1, S2, S3... Sampling circuit drive signal.

Claims (2)

In the image display area on the substrate,
A plurality of scanning lines and a plurality of data lines arranged in crossing with each other;
A plurality of pixel portions arranged corresponding to each intersection of the plurality of scanning lines and the plurality of data lines,
In the peripheral area located around the image display area,
A plurality of image signal lines to which image signals are supplied;
A sampling circuit that samples an image signal of the image signal line in accordance with a sampling circuit drive signal and supplies the sampling signal to the plurality of data lines;
A shift register that sequentially outputs a transfer signal from each stage based on a clock signal of a predetermined period;
A pulse control circuit that outputs an enable signal having a predetermined pulse width, a signal having a short pulse width with respect to the clock signal and delayed by a predetermined time , further delayed with respect to the clock signal;
For each stage of the shift register, the sampling circuit drives the logical product of the transfer signal output from the stage of the shift register after being delayed with respect to the clock signal and the enable signal output from the pulse control circuit. An enable circuit for supplying the sampling circuit as a signal,
The electro-optical device, wherein the pulse control circuit includes the same number of inverters formed in the same process as inverters provided on an output path of the transfer signal in each stage of the shift register. An electronic apparatus comprising the electro-optical device according to claim 1 .

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