JP2003015152A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform adjustment of a clock signal at a low cost. SOLUTION: This display device has one or more inverter circuits for adjusting a delay time between an external clock signal input parts T1, T2 for inputting external clock signals CKH1, CKH2, and a sampling signal generating circuit (shift register) on a substrate 10, and selects only a necessary inverter circuit from them, and connects it to delay a sampling timing of a video signal. The connections of the inverter circuits to signal routes can be realized only by altering a connection wiring pattern mask according to the number of the inverters to be connected, without altering the other manufacturing process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to timing control for sampling a video signal based on a clock signal in a drive circuit of a video display device.

[0002]

2. Description of the Related Art In recent years, video display devices have particularly strong market needs as monitors for portable display devices such as portable televisions and mobile phones, and in these applications, the display devices have been downsized accordingly. Since there are strong demands for weight reduction and power saving, research and development are being actively conducted to meet the demands.

FIG. 8 shows an equivalent circuit diagram of a conventional liquid crystal display device, and FIG. 9 shows a timing chart when the liquid crystal display device is driven.

As shown in FIG. 8, a liquid crystal display panel P includes a plurality of gate signal lines 51 connected to a gate driver 50 for supplying a gate signal and a drain driver 60 for supplying a drain signal on an insulating substrate 10. The sampling transistors SPt1, SPt2, ..., SPtn are turned on according to the timing of the sampling pulse output from the data signal line (video signal line) 62, and the data signal (video signal) Sig of the data signal line (video signal line) 62 is supplied accordingly. A plurality of drain signal lines 61 are arranged, and both of these signal lines 5
In the vicinity of the intersection of 1 and 61, both of these signal lines 51 and 6
The TFT 70 connected to 1 and the display electrode 80 connected to the TFT 70 are arranged.

A panel driving LSI is provided on an external circuit board which is a board different from the insulating board 10.
Clock signals CKH1 and CKH2 are supplied from an external panel driving LSI via the external clock input sections T1 and T2. This clock signal CKH1 and C
KH2 is a clock signal whose phase is opposite to each other, and sampling transistors SPt1, SPt2, SPt3 ...
Is a reference signal for generating a timing signal that determines the timing of latching the video signal.

From the panel driving LSI, the vertical driver start signal STV and the horizontal driver start signal STH are input to the gate driver 50 and the drain driver 60, respectively, and the data signal Sig is input to the data signal line 62. To be done.

First, a clock signal input from the outside,
That is, the external clock signals CKH1 and CKH2 are input to the level shifter (L / S), and 0-3V is boosted to 0-8V, for example. Then, the output signal is input to the shaping inverter circuit 102, and the buffer circuit 101
Is input as a clock signal to each shift register that constitutes the drain driver 60 via.

Each shift register is composed of an inverter circuit and a clocked inverter circuit, and a clock signal is sequentially transferred to the next stage based on a horizontal start signal STH, and a sampling pulse is generated by each shift register.

Based on this sampling pulse, a video signal input from the outside is sampled by the sampling TFT and output to each drain signal line 61. That is, the sampling TFT SPt is turned on according to the sampling signal based on the start signal STH, and the video signal of the video signal line 62 is supplied to the drain signal line 61.

Further, a gate signal is input from the gate signal line 51 to the gate electrode 13, and the TFT 70 is turned on. As a result, a drain signal is applied to the display electrode 80 via the TFT 70. At the same time, a drain signal is also applied to the auxiliary capacitor 85 via the TFT 70 in order to hold the voltage applied to the display electrode 80 for one field period. One electrode of this auxiliary capacitance 85 is connected to the source 11s of the TFT 70, and the other electrode is connected to each display pixel P.
11, P12, P13 ..., P21, P22, P23
, A common potential is applied.

When the gate 13 of the TFT 70 is opened and a drain signal is applied to the liquid crystal 21, it must be held for one field period. However, only the liquid crystal 21 causes the voltage of the signal to gradually decrease with time. Then, flicker and display unevenness appear, and good display cannot be obtained. Therefore, an auxiliary capacitor 85 is provided to hold the voltage for one field period.

The voltage applied to the display electrode 80 is applied to the liquid crystal 21.
The liquid crystal 21 is oriented according to the voltage by applying the voltage to the display, and a display can be obtained.

[0013]

However, in the conventional liquid crystal display device, the characteristics of each circuit, for example, the inverter circuits 101 and 102 may vary due to variations in manufacturing process conditions and the like. As a result, the timing of sampling the video signal based on the clock signal may be changed such that it becomes earlier or later.

Therefore, the potential of the drain signal supplied from the video signal line 62 to the drain signal line 61 is the video signal S.
Before being sufficiently charged to the potential of ig, it is sampled and determined by the sampling TFT SPt. In this case, an insufficient voltage is applied to the display electrode 80, resulting in a display device with low display quality. There was a problem of being lost.

FIG. 9 shows a timing chart at each point of A, B and C in FIG.

As described above, the horizontal start signal STH is shifted in the drain driver 60 based on the external clock signals CKH1 and CKH2 to generate the sampling timing signals STH, STH2, ... It is output (point A). This timing signal becomes a timing signal of the same phase with different polarity through different inverters, and the sampling TFT SPt
Is applied to (points B and C). However, the sampling TFTs S
When the timing signals (B, C) for turning on Pt are output at the timings shown in FIG. 9, the potential of the video signal S11 is sampled at the timing when the video signal line 62 is not yet fixed. Therefore, in such a case, the display quality will deteriorate.

In order to eliminate such a timing difference between the sampling signal and the video signal, the clock signal C
It is conceivable to adjust the phases of KH1 and CKH2.
Specifically, the phase adjustment means the clock signals CKH1,
By changing the delay time of CKH2, this may change the number of inverter circuits in the clock input section. However, since the inverter circuit cannot be changed after each circuit is formed, the source and drain electrodes of the TFT and the wiring are changed from another new pattern mask, that is, the pattern mask of the islanding process of the active layer of the TFT configuring the inverter circuit. All pattern masks up to the pattern mask for forming are to be produced. Then, there is a drawback that the cost is very high when the new pattern mask is manufactured.

The present invention has been made in view of the above-mentioned conventional drawbacks, and it is possible to easily set the timing at which the sampling transistor samples the video signal to an appropriate timing without increasing the cost. An object of the present invention is to provide a video display device capable of obtaining good display.

[0019]

According to the present invention, a display signal sequentially transferred from the outside is sampled on the basis of an external clock signal and is supplied to each pixel arranged in a matrix so as to be displayed on each pixel. A sampling signal generating circuit for generating a sampling signal for sampling the display signal based on the external clock signal, the sampling signal generating circuit, and the external clock signal supply terminal. And one or more clock delay circuits having a function of delaying the external clock signal, the one or more clock delay circuits supplying the external clock signal to the sampling signal generating circuit. The number of delay circuit connections required for the wiring in the signal transmission wiring and the connection wiring forming process for the signal transmission wiring. In response to connection it is formed by changing the pattern mask connection wire to be used.

According to another aspect of the present invention, in the display device, the clock delay circuit is an inverter circuit configured by complementarily connecting an n-type thin film transistor and a p-type thin film transistor, and one inverter circuit is provided. The active layers of the n-type and p-type thin film transistors constituting the above are separated from each other by a distance larger than the line width of the signal transmission wiring.

According to another aspect of the present invention, in the above display device, a switching element is formed in each of the pixels, an electrode or a wiring connected to the switching element, the signal transmission wiring and the one or more of the one or more. The connection wiring of the clock delay circuit is made of the same material.

According to such a display device, the sampling of the video signal by the sampling transistor can be easily executed at an appropriate timing without increasing the cost, and thus a good display can be obtained.

In another aspect of the present invention, a display signal sequentially transferred from the outside is sampled based on an external clock signal and supplied to each pixel arranged in a matrix,
A display device for displaying on each pixel, a sampling signal creating circuit for creating a sampling signal for sampling the display signal based on the external clock signal, the sampling signal creating circuit, and the supply of the external clock signal At least one circuit for clock delay disposed between the terminal and the circuit for delaying the external clock signal, and at least one of the one or more circuits for clock delay is provided in the sampling signal generation circuit. It is insulated from the signal transmission wiring for supplying the external clock signal.

According to another aspect of the present invention, in the display device, the signal transmission wiring is formed in the formation region of the one or more clock delay circuits which are not electrically connected to the signal transmission path. It is arranged so that it can pass through while maintaining its insulation.

According to another aspect of the present invention, in the display device, the clock delay circuit is an inverter circuit configured by complementarily connecting an n-type thin film transistor and a p-type thin film transistor, and one inverter circuit. The active layers of the n-type and p-type thin film transistors constituting the above are separated from each other by a distance larger than the line width of the signal transmission wiring.

In another aspect of the present invention, in the display device, the clock delay circuit is an inverter circuit configured by complementarily connecting an n-type thin film transistor and a p-type thin film transistor, and the signal transmission wiring. In the formation region of the clock delay circuit, which is insulated from, the signal transmission wiring is arranged in a gap between the active layers of the n-type and p-type thin film transistors that can form one inverter circuit and are separated from each other. There is.

According to another aspect of the present invention, in the display device, the clock delay circuit is an inverter circuit configured by complementarily connecting an n-type thin film transistor and a p-type thin film transistor, and the signal transmission path. The n-type and p-type thin film transistors for the one or more clock delay circuits, which are not electrically connected to, are connected to the low voltage side power line and the high voltage side power line, respectively.

As for the transistors which are not connected to the signal path as described above, by connecting to the power supply line,
It does not become an electrically floating state, and the influence on other circuit elements can be made extremely small even if there is a delay circuit that is not connected.

In another aspect of the present invention, a display signal sequentially transferred from the outside is sampled based on an external clock signal and supplied to each pixel arranged in a matrix,
A display device for displaying on each pixel, a sampling signal creating circuit for creating a sampling signal for sampling the display signal based on the external clock signal, the sampling signal creating circuit, and the supply of the external clock signal One or more clock delay circuits having a function of delaying the external clock signal are connected to the signal transmission wiring between the terminals, and all of the one or more clock delay circuits configure each circuit. The plurality of elements are spaced apart from each other by a width greater than the line width of the signal transmission wiring.

According to another aspect of the present invention, in the display device, the one or more clock delay circuits are inverter circuits configured by complementarily connecting an n-type thin film transistor and a p-type thin film transistor. The active layers of the n-type and p-type thin film transistors that form one inverter circuit are separated from each other by a width greater than the line width of the signal transmission line.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION A video display device according to a preferred embodiment of the present invention (hereinafter referred to as an embodiment) will be described below with reference to the drawings.

FIG. 1 shows an equivalent circuit diagram when the image display device of the present invention is applied to a liquid crystal display device, and FIG. 2 shows a timing chart at the time of driving at each point of the liquid crystal display device.

As shown in FIG. 1, the liquid crystal display panel P is
An external panel drive LS separate from the liquid crystal display panel P
It is driven based on I and each signal supplied from each signal terminal.

In the liquid crystal display panel P, a plurality of gate signal lines 51 connected to a gate driver 50 for supplying a gate signal are arranged in the row direction (horizontal direction) and connected to a drain driver 60 for supplying a drain signal. The plurality of drain signal lines 61 are arranged in the column direction (vertical direction). A TFT 70, which is a switching element in the display area, is arranged near the intersection of the signal lines 51 and 61. Further, in the liquid crystal display panel P, a plurality of display pixels P11, P12, P13, ... Are arranged in a matrix. Each of these display pixels is formed in a region partitioned by the gate signal line 51 and the drain signal line 61. Display electrode 8 connected to this TFT 70
The rising and falling edges of the liquid crystal 21 are controlled by the voltage applied to 0.

In the liquid crystal display panel P, an external clock signal, a data signal, a counter electrode voltage for scanning each driver 50, 60 supplied from an external panel driving LSI, a voltage for driving each driver, and The terminals T1 to T9 for applying a voltage for driving the signal holding circuit are provided.

As described above, the external panel driving LSI
Are external clock signals CKV1, CKV2, CKH1, CKH for operating the above-mentioned drivers 50, 60.
2. Create timing signals (STV, STH) and display data signal (Sig). In addition, the signal terminals T1 to T9
Supplies an external clock signal, a counter electrode voltage Vcom, a driver power supply, and the like to the liquid crystal display panel P.

Each shift register has a drain driver 60.
Which is composed of an inverter circuit and a clocked inverter circuit, and supplies a horizontal start signal STH
Based on the clock signals CKH1 and CKH2, they are sequentially transferred to the next stage, and sampling pulses are output from each shift register. The configuration of the clocked inverter can be replaced with an inverter circuit and a transfer gate.

A characteristic of FIG. 1 is that a delay time adjusting circuit (delay circuit) 100 for adjusting sampling timing is provided between the external clock signal input sections T1 and T2 and the shift register (sampling signal creating circuit) 60. That is, a plurality of inverter circuits 111 are provided.

Now, a driving method of the image display device of the present invention will be described with reference to FIG.

An external clock signal CKH1, whose cycle is t1,
Based on CKH2, the shift register transfers the start signal STH, and the corresponding sampling TFTS
A sampling signal whose selection level is in the "t" period is output to Pt1, SPt2, SPt3, ... (See A in the figure). The sampling TFT SPt samples the video signal at a timing according to this sampling signal.

At points B and C, that is, at the sampling timing of the video signal of the sampling TFT, the video signal S11 is sufficiently charged in the video signal line 62, and the video signal line 62 is charged.
It is performed at the timing when the potential of (1) becomes equal to the original potential of the video signal S11.

As shown in FIG. 9, the timing at which the sampling TFT samples the video signal is
This is because the sampling timing is delayed by selecting the inverter circuit required to obtain the required delay time, as compared with the timing when the video signal line 62 is not sufficiently charged by the video signal S11. Therefore, sampling can be performed in a state where the potential is sufficiently charged, and a good display can be obtained.

FIG. 3 shows an example in which the inverter circuits 111 which are electrically independent of each other are selected and connected.

FIG. 3A shows a case where two inverter circuits electrically independent of each other are formed. However, in FIG. 3A, no inverter circuit 111 for timing adjustment is selected. 3B is an equivalent circuit when the two inverter circuits shown in FIG. 3A are connected between the external clock input sections T1 and T2 and the shift register 60. The connected inverter circuit is formed at the same time as the switching TFTs that form the drive circuit in the display area of the video display device and its peripheral area. Further, only the mask pattern used in the step of forming the source and drain electrodes and wirings of those switching TFTs adopts a pattern for connecting the inverter circuit, and based on the pattern, the electrode and wiring are formed and the inverter connection line is formed at the same time. The desired inverter circuit is connected.

The example of FIG. 3C shows a case where an electrically independent inverter circuit is formed, that is, no delay time adjusting inverter circuit is selected and connected.

In FIG. 3D and FIG. 3E, FIG.
Although the same inverter circuit as in the case of (c) is formed, by using a mask that connects one or two inverter circuits as a pattern mask between wirings and electrodes, a plurality of masks can be formed in the signal path as illustrated. The inverter circuits of are connected in parallel.

In this way, if two or three inverter circuits are connected in parallel, the size of the transistor (that is, the load of the circuit) in terms of the circuit can be changed as compared with the case of one inverter circuit. You can In addition,
For example, the channel length is fixed at 6 μm, the n-channel width is 50 μm, and the p-channel width is 75 μm.
When set to μm, the sampling timing of the video signal is 1
It can be delayed by 0 nanoseconds (nSec).

FIGS. 4 and 5 show the layout pattern of the inverter circuit of the present invention and the conventional image display, and FIG. 6 (a) is a sectional view taken along the line AA of FIG. 4 (a). 6
4B is a sectional view taken along the line BB of FIG.
4 (a) to 4 (c) show a case where four inverter circuit patterns are formed on a substrate.

In FIG. 4A, all the inverter circuits 111 are connected with a hatched connecting line pattern made of, for example, aluminum, particularly a connecting line (signal transmission line) L1 connecting the level shifter (L / S) to the buffer circuit. It shows the case where they are not connected. FIG. 4B shows a case where all four inverter circuits are connected by a connection line pattern, and FIG. 4C shows the left two inverter circuits in the figure among the four inverter circuits as connection lines. The case where the patterns are connected is shown. Further, in each drawing, an output signal from the shaping inverter circuit connected to L / S is input to the wiring L1 and output to the buffer circuit 101 via each connected inverter circuit. A power supply line extends above and below each figure, and power supply voltages VDD and VSS of the inverter circuit are applied.

When the video display device is manufactured, the sampling timing of the video signal is too early in a certain manufacturing lot, and the video signal line is not sufficiently charged by the video signal. If it is not possible, select an inverter circuit in the next manufacturing lot and connect with the connection line pattern. Then, the sampling timing is delayed. That is, as shown in FIG. 4A, the TF for the inverter is
It is assumed that the sampling timing is too early for a display manufactured in a manufacturing lot in which a pattern in which T is formed on the substrate but none of the inverter circuits remains separated from the signal path and is not selected. In this case, in the next manufacturing lot, the connection line pattern for non-selection (see FIG.
Instead of (the hatched area in (a)), four connection circuit patterns for selecting an inverter circuit (hatched area in FIG. 4B) are adopted, and four inverter circuits are arranged in the signal path. Alternatively, two inverter circuits are arranged by adopting a connection line pattern for selecting two inverter circuits as shown in a hatched area in FIG. 4C. By connecting the inverter circuit in the signal path in this manner, signals (here, the clock signals CKH1, CK) are generated.
Adjust the delay time of H2). Here, the number of inverter circuits to be selected may be set so that the sampling timing is a timing at which the video signal line is sufficiently charged by the video signal. It should be noted that the number of electrically independent inverter circuits formed on the substrate may be any number that can cover the delay or advance of sampling timing in each manufacturing lot.

Further, the contact position between each active layer shown by dotted lines in FIGS. 4A to 4C and each electrode and connecting line made of aluminum hatched with diagonal lines is shown by "X" in the drawing, Although the connections are different in all the drawings, the position of "X" is the same in all of FIGS. 4 (a) to 4 (c). Further, the contact position between the gate electrode made of, for example, chrome (Cr) of the TFT and the connection line is indicated by a mark "○" in the figure, and this contact is also the same as the contact indicated by "X" in FIG. 4 (a). 4 (c), the connections are different, but they are formed at the same position in all the drawings. Further, in both the inverter circuit connected to the signal path and the inverter circuit not connected, a contact between the active layer and the connection wiring, and a contact between the wiring to be the gate and the connection wiring are formed.

Therefore, the required number of delay circuits having an inverter structure can be connected here at the same time as the step of forming the drain signal lines of the TFTs forming the drive circuits in the display pixel region and its peripheral region. That is, when the number of delay circuits is changed, the TF that newly configures the inverter circuit
If the method of forming T is adopted, it is necessary to change the mask pattern up to the contact portion forming step for manufacturing.
However, in the present invention, a connection line pattern for connecting the inverter circuit to the signal path is used as a mask pattern to be used in the step of forming the electrodes and wirings of the TFTs which are the switching elements forming the drive circuit in the display area and its peripheral area. The delay time can be adjusted by simply changing the wiring pattern without increasing the number of steps and without changing the order of steps.

4 (a) to 4 (c), in addition to the contact positions indicated by "X" and "○", respectively,
In the present embodiment, the gate electrode 13 (white wiring in each drawing) made of Cr or the like is also used in FIGS. 4 (a) to 4 (c).
In each figure, they are all formed at the same position. Also,
Regardless of whether or not the inverter circuit is connected to the signal transmission line (L1), the positions of the TFTs forming the inverter circuit, specifically, the positions of the island-shaped active layers of the TFTs are all the same. As described above, since the active layer and the contact position are arranged at the same position regardless of whether or not there is a connection to the signal path of the inverter circuit, one inverter circuit 11 is provided in this embodiment.
The active layers of the nch-type TFT and the pch-type TFT that form part 1 are separated by the signal transmission line L1 of the inverter circuit so that they can be arranged therebetween. The inverter circuit not connected to the signal transmission wiring is shown in FIG.
As shown in (a), the signal transmission line L1 has nch-type TFTs and pch-type TFTs of each inverter circuit 111.
Is laid out to pass between the active layers of the.

When a plurality of inverter circuits are used as delay circuits, usually, a required number of inverter circuits are formed from the beginning, and the plurality of inverter circuits are connected in series. Then, as shown in FIG. 5A, the nch-type TFT and the pch-type TFT which form one inverter circuit are arranged as close to each other as possible. Therefore, when the number of required inverter circuit connections is changed, an inverter circuit forming mask corresponding to the number of connections is used in each manufacturing process.

On the other hand, in this embodiment, as described above, the inverter circuit formed on the substrate is formed at the same position regardless of whether or not it is connected to the signal transmission wiring of the clock, and each wiring is formed. The contact positions with the electrodes are also the same. Therefore, the wiring (for example, the data signal line of the display device, the VDD and VSS lines, the signal transmission wiring L
1) Only in the forming step, the number of connected inverter circuits can be changed by changing the mask into which the wiring pattern is drawn according to the number of connected inverter circuits.

FIGS. 5 (b) and 5 (c) show an inverter circuit functioning as a delay circuit shown in FIGS. 4 (a) -4 (c).
Shows a different layout. Note that in FIG. 5B, all the inverter circuits are insulated from the signal transmission wiring L1, and in FIG. 5C, all the inverter circuits are connected to the wiring L1. 4 (a) to 4 (c) is different in the arrangement direction of each TFT, and FIGS. 4 (a) to 4 (c)
Then, although the channel length direction of each TFT is along the extending direction of the VDD and VSS lines, FIG. 5B and FIG. 5C
In the layout, the TFT channel length direction is VDD
And a direction perpendicular to the extending direction of the VSS line. However, each TFT is formed between the VDD and VSS lines which are the power source of the inverter circuit, and constitutes one inverter circuit, nch type TFT and pch type TFT.
The common point is that the active layers are separately arranged regardless of whether or not they are connected to the signal transmission line L1. Further, similarly, with such an arrangement, the formation position of the TFT and the contact position with each electrode or wiring are the same regardless of whether or not they are connected to the signal transmission wiring L1. In addition,
In any of the wiring pattern masks of FIGS. 4A to 4C, 5B, and 5C, the electrodes and wiring patterns of the TFTs forming the drive circuit in the display region and its peripheral region are the same mask. Is drawn inside.

Next, a method of manufacturing the above-mentioned inverter circuit will be described with reference to FIG. First, an amorphous silicon film (hereinafter referred to as “a”) is formed on an insulating substrate 10 such as a non-alkali glass substrate or a quartz substrate by using a plasma CVD method.
-Si film ") is deposited, and XeC is deposited from the surface side.
l Excimer laser beam is irradiated while scanning, and a-
The Si film is melted and recrystallized to form a polycrystalline silicon film (hereinafter,
(Referred to as "p-Si film") 11. It is islanded by a photolithography technique using a photomask pattern, and it becomes the active layer of the thin film transistor.

On the entire surface of the substrate 10 covering the p-Si film 11,
As the gate insulating film 12, a SiN film and a SiO ₂ film are sequentially stacked by the CVD method. A gate electrode 13 made of a refractory metal such as Cr or W is formed on the gate insulating film 12 by photolithography using a photomask pattern having a gate electrode pattern. Using this gate electrode 13 as a mask, ion doping is performed on the region to be the source 11s or the drain 11d of the active layer.
Phosphorus (P) is introduced in the case of an n-channel TFT, and boron (b) is introduced in the case of a p-channel TFT.

After that, a SiO ₂ film, a SiN film and a SiO ₂ film are formed.
An interlayer insulating film 14 is formed by laminating films in order. Contact holes 15 are formed in regions of the interlayer insulating film 14 corresponding to the sources 11s and the drains 11d. Also in that case, the contact hole 15 is formed by the photolithography technique using a photomask pattern having a pattern for forming the contact hole. Then, aluminum (Al) is deposited on the interlayer insulating film 14 including the contact holes by using the sputtering method. Then, using a photomask pattern having the pattern of the source 16 and the drain electrode 17 and the wiring 18, this Al is formed by the photolithography technique.
Is patterned to form the source electrode 16 and the drain electrode 1
7 and the wiring 18 are formed. Finally, an insulating film is formed on the source and drain electrodes 16 and 17 and the wiring 18 to insulate the surface. The source / drain electrodes 16 and 17 in FIG. 6 are either VDD lines or VSS lines, depending on the connection pattern of the inverter circuit employed, as shown in FIGS. 4 (a) to 4 (c). It is also used for Of course, simultaneously with the formation of these electrodes and wirings, connection line wirings for connecting a desired number of inverter circuits are also formed.

The inverter circuit is completed as described above. At the same time when the peripheral drive circuit including such an inverter circuit is formed, the TFT 70 (for pixel switch) arranged in the display area of the image display device is also formed (see FIG. 1).

According to the structure of the present invention, depending on the delay condition, there is an inverter circuit formed on the substrate but not connected to the signal path. Even in this case, as shown in FIG. 4A, the unconnected inverter circuit is electrically connected to the VDD line or the VSS line in the signal path, and in this example, all of these TFTs have the OFF voltage. Is applied to the gate electrode 13,
Unexpected malfunction is surely prevented.

As described above, the pattern mask is used in each step in forming the TFT of the image display device. Conventionally, in order to adjust the sampling timing of a video signal, it is necessary to prepare a pattern mask for additionally forming various numbers of inverter circuits each time when changing the number of inverter circuits. is there. On the other hand, in the present invention, a plurality of inverter circuits are formed by the pattern mask of each process in which a pattern for forming a plurality of electrically independent inverter circuits is drawn in advance regardless of whether or not they are connected to a signal path. I'll do it. Therefore, in order to change the number of inverter circuits for delay time adjustment, prepare pattern masks that differ only in the inverter connection line patterns for connecting each inverter circuit, for the number of expected inverter circuit connections. You can leave it. That is, if a plurality of inverter circuits are prepared in advance and a pattern mask for connecting them as needed is prepared, it is not necessary to prepare a pattern mask necessary for a process before the connection line pattern formation. Absent.

A case will be described in which the number of inverter circuits formed in this way is selected as needed and the inverter circuits are connected.

In the two inverter circuits shown in FIG. 6, as described above, FIG. 6 (a) is a sectional view taken along the line AA of FIG. 4 (a). Not connected. On the other hand, FIG.
FIG. 4B is a cross-sectional view taken along line BB in FIG. 6B, in which all illustrated inverter circuits are connected to the signal path. The inverter circuits shown in FIGS. 5 (b) and 5 (c) have the same sectional structure as that shown in FIGS. 6 (a) and 6 (b).

That is, when connecting the inverter circuit, the inverter circuit is constructed by using a mask in which a pattern for connecting the necessary inverter circuit is drawn as a photomask pattern on which the source and drain electrodes and the wiring pattern are formed. The required number of n-channel TFTs and p-channel TFTs are connected. This makes it possible to control the delay of the sampling timing by a desired amount.

As described above, the photomask pattern on which each pattern for forming the switching elements of the drive circuit in the display area and the peripheral area is formed, and the mask pattern for forming a plurality of electrically independent inverter circuits is also formed. A plurality of inverter circuits, which are electrically independent from each other, are formed at the same time when the switching elements of the drive circuits in the display area and the peripheral area are formed by drawing.

The necessary inverter connection line pattern is also drawn on the mask pattern for forming the electrodes and wirings of the switching element after that, and the inverter circuit is connected at the same time when the drive circuits in the display area and the peripheral area are formed. .

In this way, the inverters can be simply switched between the external clock input section and the shift register according to the delay time of the sampling timing by switching the pattern mask on which the pattern for connecting the desired number of inverter circuits is formed. A circuit can be easily selected and connected, and the delay time can be adjusted, so that the sampling timing is good and the display is not disturbed.

As described above, according to the video display device of the present invention, when the sampling timing of the video signal of the video display device of a certain lot is deviated, the video display device of the next lot is manufactured. The number of inverter circuits, that is, the delay time is selected so that the timing delay time becomes an appropriate value, and the connection can be made by a photomask pattern having a wiring pattern for connecting the selected inverter circuit. Since the video signal can be sampled at an appropriate timing, it can be charged to a sufficient potential, so that a good display can be obtained.

In the above embodiment, the case where the delay time is increased has been described, but FIG.
When changing from the pattern of to the pattern of FIG. 4 (c),
That is, even when the delay time is reduced, the timing can be adjusted by reducing the number of inverters selected.

In the inverter circuit manufactured on the above-mentioned substrate, the delay time can be varied depending on the size of the TFT which constitutes the inverter circuit. Therefore,
If the sampling timing is greatly delayed by one inverter circuit, an inverter circuit having a large channel width may be manufactured. Conversely, if the delay amount is desired to be small, it can be realized by reducing the channel width. .

Further, in the above-described embodiment, the case where the inverter circuit is used as the delay circuit has been described, but the present invention is not limited to this, and FIG.
As shown in (a), the delay time can be adjusted by connecting a resistor and a capacitor and adjusting their resistance value and capacitance value. Further, as shown in FIG. 7B, the delay time can be adjusted by replacing the inverter circuit with a NAND gate circuit. Further, FIG. 7 (c)
As shown in, the delay time can be adjusted by using the NOR gate circuit.

Furthermore, in the present invention, the "delay time" includes not only the case where the sampling timing is delayed but also the case where it is early.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram when a display device according to an embodiment of the present invention is applied to a liquid crystal display device.

FIG. 2 is a timing chart of the display device according to the embodiment of the present invention.

FIG. 3 is a diagram showing a method of connecting an inverter circuit of a display device according to an embodiment of the present invention.

FIG. 4 is a diagram showing a method of connecting an inverter circuit of a display device according to an embodiment of the present invention.

FIG. 5 is a diagram showing a connection method of an inverter circuit of a general display device and an inverter circuit of a display device according to an embodiment of the present invention.

6 is a cross-sectional view of the inverter circuit of FIG.

FIG. 7 is an equivalent circuit diagram showing another embodiment of the delay time adjusting circuit of the present invention.

FIG. 8 is an equivalent circuit diagram of a conventional liquid crystal display device.

FIG. 9 is a timing chart at each point of a conventional liquid crystal display device.

[Explanation of symbols]

10 insulating substrate, 21 liquid crystal, 50 gate driver, 51 gate signal line, 60 drain driver (shift register), 61 drain signal line, 62 video signal line, 70 TFT, 80 display electrode, 100 delay time adjusting inverter circuit, L / S level shifter, L1
Connection wiring, P liquid crystal display panel, SPt1 to SPt3
Sampling transistor.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 623 G09G 3/20 623H 5F048 623M 5F064 3/36 3/36 5F110 H01L 21/336 H01L 27 / 08 331E 21/82 29/78 612C 21/822 27/04 M 27/04 21/82 S 27/08 331 29/78 612D 29/786 612B 613A F Term (reference) 2H092 GA31 JA24 JB35 NA11 PA06 2H093 NA16 NA31 NC21 NC34 NC90 ND34 NE03 5C006 AC09 AC21 AF46 AF50 AF51 AF52 AF53 AF72 BB16 BC13 BC20 BC23 BF03 BF07 BF11 BF27 BF33 BF34 EB05 FA16 FA20 5C080 AA10 BB05 DD09 CD08 CD06 CD06 E06 CD02 CD06 AV06 AF06 AF06 AF06 AF06 AF06 AF06 AF06 AF06 AF06 AF02 5F048 AB04 AC04 BA16 BB05 BB09 BC01 BD01 BF11 BG07 5F064 BB07 CC12 DD09 DD14 EE09 EE33 EE47 EE52 EE54 EE56 FF09 F F24 FF48 5F110 AA16 AA30 BB02 BB04 CC02 DD02 DD03 EE04 FF02 FF03 FF09 FF29 GG02 GG13 GG26 GG45 HJ01 HJ12 HL03 HL23 NN03 NN23 NN24 NN35 PP03 QQ01 QQ11

Claims (10)

[Claims] 1. A display device in which a display signal sequentially transferred from the outside is sampled based on an external clock signal and is supplied to each pixel arranged in a matrix so that each pixel displays the display signal. A sampling signal generation circuit that generates a sampling signal for sampling based on the external clock signal, and a sampling signal generation circuit that is arranged between the sampling signal generation circuit and the external clock signal supply terminal to delay the external clock signal. One or more clock delay circuits having a function of causing the signal transmission wiring to supply the external clock signal to the sampling signal generating circuit, And connection wiring used according to the number of delay circuit connections required in the connection wiring forming process A display device characterized by connecting by changing and forming a pattern mask for use. 2. The display device according to claim 1, wherein the clock delay circuit includes an n-type thin film transistor and a p-type thin film transistor.
An n-type thin film transistor and an active layer of the n-type and p-type thin film transistors that form one inverter circuit are separated from each other by a distance larger than the line width of the signal transmission line. A display device characterized by being. 3. The display device according to claim 1, wherein a switching element is formed in each of the pixels, an electrode or a wiring connected to the switching element, the signal transmission wiring, and the A display device, wherein the connection wiring of one or more clock delay circuits is made of the same material. 4. A display device for sampling a display signal sequentially transferred from the outside based on an external clock signal, supplying the sampled signal to each pixel arranged in a matrix, and displaying each pixel on the display signal. A sampling signal generation circuit that generates a sampling signal for sampling based on the external clock signal, and a sampling signal generation circuit that is arranged between the sampling signal generation circuit and the external clock signal supply terminal to delay the external clock signal. And at least one clock delay circuit having a function of enabling at least one of the at least one clock delay circuit,
A display device, which is insulated from a signal transmission line for supplying the external clock signal to the sampling signal generation circuit. 5. The display device according to claim 4, wherein the signal transmission wiring is formed within the formation region of the one or more clock delay circuits that are not electrically connected to the signal transmission path. A display device, which is arranged so as to pass through while maintaining the insulation of the display device. 6. The display device according to claim 5, wherein the clock delay circuit includes an n-type thin film transistor and a p-type thin film transistor.
An n-type thin film transistor and an active layer of the n-type and p-type thin film transistors that form one inverter circuit are separated from each other by a distance larger than the line width of the signal transmission line. A display device characterized by being. 7. The display device according to claim 5, wherein the clock delay circuit includes an n-type thin film transistor and a p-type thin film transistor.
In the formation region of the clock delay circuit that is insulated from the signal transmission line, the n-type and the n-type and the A display device, wherein the signal transmission line is arranged in a gap between active layers of a p-type thin film transistor which are arranged separately from each other. 8. The display device according to claim 5, wherein the clock delay circuit includes an n-type thin film transistor and a p-type thin film transistor.
An n-type and a p-type thin film transistor for the one or more clock delay circuits that are not electrically connected to the signal transmission path, A display device characterized by being connected to a low voltage side power line and a high voltage side power line, respectively. 9. A display device for sampling a display signal sequentially transferred from the outside based on an external clock signal, supplying the sampled signal to each pixel arranged in a matrix, and displaying each pixel on the display signal. A sampling signal generating circuit for generating a sampling signal for sampling based on the external clock signal, and a wiring for transmitting the signal between the sampling signal generating circuit and the supply terminal for the external clock signal, the external clock One or more clock delay circuits having a function of delaying a signal are connected, and in all of the one or more clock delay circuits, a plurality of elements forming each circuit are larger than a line width of the signal transmission wiring. A display device characterized by being separated. 10. The display device according to claim 9, wherein the at least one clock delay circuit is an inverter circuit configured by complementarily connecting an n-type thin film transistor and a p-type thin film transistor. A display device, wherein active layers of the n-type and p-type thin film transistors that form an inverter circuit are separated from each other by a distance larger than a line width of the signal transmission wiring.