JP2009122600A - Electrophoretic display device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrophoretic display device which can prevent occurrence of an operational malfunction in a memory circuit due to fluctuation of performance of elements, and is excellent in manufacturability and operational reliability. <P>SOLUTION: The electrophoretic display device is constructed in such a way that: a TFT 41 for driving and a latch circuit 70 are arranged for each pixel 40; the latch circuit 70 has a transfer inverter 70t and a feedback inverter 70f; a first switching transistor 75 is connected between a high potential power terminal PH of the feedback inverter 70f and a data input terminal N1; and a second switching transistor 76 is connected between a low potential power terminal PL of the feedback inverter 70f and the data input terminal N1, wherein a gate terminal of the first switching transistor 75 is connected to a scanning line 66 together with a gate terminal of the TFT 41 for driving, and meanwhile, a gate terminal of the second switching transistor 76 is connected to a reverse scanning line 67. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electrophoretic display device and an electronic apparatus.

As an active matrix electrophoretic display device, a device including a switching transistor and a memory circuit in a pixel has been known (see, for example, Patent Document 1). In the display device described in Patent Document 1, a microcapsule containing charged particles is bonded onto a first substrate on which a pixel switching transistor and a pixel electrode are formed. Then, a microcapsule is sandwiched between the counter electrode formed on the second substrate side and the pixel electrode on the first substrate side, and the charged particles are controlled by the electric field generated between the pixel electrode and the counter electrode. The image was being displayed.
JP 2003-84314 A

As described in Patent Document 1, a method of incorporating a latch that holds information as a potential in a pixel (herein referred to as an SRAM (Static Random Access Memory) method) is a capacitor built-in method of holding a potential by a capacitor ( Compared with a 1C system or a DRAM (Dynamic Random Access Memory) system), it is not necessary to write an image signal every fixed period, so that power consumption can be reduced.
Further, when the pixel circuit is formed of a low-temperature polysilicon TFT (Thin Film Transistor), it can be driven at a low voltage, and power consumption can be reduced. For this reason, low-temperature polysilicon TFTs (Thin Film Transistors) have been frequently used in pixel circuits of electrophoretic display devices.

  However, for example, a low-temperature polysilicon TFT crystallized by an excimer annealing method has a problem that the manufacturing variation of transistor elements is large. As an example, the ON current per unit width of a transistor may be different by about 2 to 3 times between adjacent transistors. Therefore, in an SRAM (latch circuit) composed of one bit line built in a pixel of an electrophoretic display device, image signal writing fails due to manufacturing variations of TFTs including a write transistor (pixel switching element). There was a risk of doing so.

Here, FIG. 21 is a diagram illustrating a pixel having the circuit configuration described in Patent Document 1. In FIG.
A pixel 540 illustrated in FIG. 21 includes a driving TFT 41 that is a writing transistor, a latch circuit 570, a pixel electrode 35, a common electrode 37, and an electrophoretic element 32. The latch circuit 570 is an SRAM including two P-MOS transistors 71 and 73 and N-MOS transistors 72 and 74. The specific configuration of each component illustrated in FIG. 21 has been described in detail with reference to FIG. 2 in the following embodiment.

  In the pixel 540, the driving TFT 41 is turned on by a selection signal input via the scanning line 66, and the data line 68 is connected to the data input terminal N 1 of the latch circuit 570, whereby the data line 68 and the latch circuit 570 are connected. The image signal is written to the. Then, the potential (power supply voltage Vdd or Vss) of the data output terminal N <b> 2 that changes based on the potential held in the latch circuit 570 is input to the pixel electrode 35.

  In general, in the pixel 540, the driving TFT 41 that supplies an image signal to the latch circuit 570 has a larger current driving capability (ON current) than the P-MOS transistor 73 and the N-MOS transistor 74 that constitute the latch circuit 570. Formed with. However, when these transistors are formed of low-temperature polysilicon TFTs, as described above, the manufacturing variation of the elements is large, so that the current driving capability of the driving TFT 41 and the current of the P-MOS transistor 73 or N-MOS transistor 74 are reduced. There was a risk that the driving ability would be reversed. If the current driving capability is reversed, writing of the image signal to the latch circuit 570 via the driving TFT 41 may fail, and the image signal input may not be accurately reflected on the display.

On the other hand, a liquid crystal panel using a negative power supply is also known in which writing is reliably performed on a pixel having a latch circuit. However, for example, in an electrophoretic display device that does not use a negative power source as in common swing driving described later, the size of the driving TFT 41 needs to be increased in order to avoid the influence of element variations. It was.
From experience, it is necessary to make the width of the driving TFT 41 3 to 5 times the width of the P-MOS transistor 73 and the N-MOS transistor 74 in order to sufficiently absorb the element variation. Then, since the area per pixel becomes large, it becomes difficult to cope with high definition, and furthermore, since the through current at the time of writing the image signal becomes large, the power consumption increases. In addition, there is a problem that leakage current through the data lines 68 cannot be ignored as panel consumption current.

The present invention has been made in view of the above-described problems, and is capable of preventing the occurrence of a malfunction in a memory circuit due to element variation, and an electrophoretic display device and an electrophoretic display device having excellent manufacturability and operational reliability. It is an object to provide a driving method and an electronic device.
Another object is to provide an electrophoretic display device with reduced power consumption, a method for driving the electrophoretic display device, and an electronic device.

  An electrophoretic display device of the present invention is an electrophoretic display device having an electrophoretic element including electrophoretic particles between a pair of substrates and having a display unit composed of a plurality of pixels. A pixel electrode is formed for each pixel, and a common counter electrode is formed on the other substrate for the plurality of pixels. For each pixel, a pixel switching element, the pixel switching element, and the pixel A transfer circuit having an input terminal connected to the pixel switching element and an output terminal connected to the pixel electrode, and the transfer circuit. A feedback inverter having an input terminal connected to the output terminal of the inverter and an output terminal connected to the pixel switching element, and the feedback inverter A first switching transistor is connected between the first inverter and the high-potential power supply terminal, and a second switching transistor is connected between the feedback inverter and the low-potential power supply terminal. The gate terminal of the transistor is connected to the scanning line together with the gate terminal of the transistor constituting the pixel switching element, while the gate terminal of the second switching transistor is connected to the inverting scanning line that supplies the inverted signal of the scanning line. It is characterized by.

According to this configuration, when the image signal is input to the memory circuit, the connection between the feedback inverter and the high potential power supply terminal and the low potential power supply terminal is cut off by the first and second switching transistors. Therefore, even if the current driving capability of the pixel switching element decreases due to manufacturing variations or the on-resistance of the transistor of the feedback inverter decreases, the data input terminal of the memory circuit (the input terminal of the transfer inverter; the output terminal of the feedback inverter) ) Can be reliably defined.
Thereby, an image signal can be reliably input to the memory circuit. Therefore, according to the present invention, it is possible to provide an electrophoretic display device that can perform reliable operation while suppressing the influence of manufacturing variations, and is excellent in manufacturability and operation reliability.
Further, according to the present invention, when the data held in the memory circuit is updated, all the transistors constituting the feedback inverter are simultaneously turned on and the through current flows through the feedback inverter. Can be shut off by the switching transistor. Therefore, power consumption of the display portion can be reduced.

It is preferable that a gate area defined by a gate width and a gate length in the transistor constituting the pixel switching element is not more than twice the gate area in the transistor constituting the memory circuit.
According to this configuration, since the area of the pixel switching element can be reduced, the parasitic capacitance in the pixel switching element can be reduced. As a result, the amount of charge charged in the pixel switching element decreases, so that the potential drop at the data input terminal (output terminal of the feedback inverter) of the memory circuit when an image signal is input is reduced, and malfunction of the memory circuit is prevented. Can be prevented.
Further, since the load capacity of the scanning line connected to the pixel switching element is also reduced, the size of the buffer of the scanning line driving circuit can be reduced, and the configuration contributes to narrowing the frame of the electrophoretic display device.

It is preferable that the first switching transistor is connected between a P-type transistor constituting the feedback inverter and the high potential power supply terminal.
With this configuration, the parasitic capacitance of the first switching transistor is charged by both the high potential power supply terminal and the P-type transistor. As a result, potential fluctuations at the data input terminal of the memory circuit can be suppressed, noise generation can be suppressed, and operation reliability can be improved.

The feedback inverter may have a plurality of P-type transistors, and the first switching transistor may be connected between the plurality of P-type transistors.
Also in this case, since the parasitic capacitance of the first switching transistor is charged by the two P-type transistors arranged on both sides, the potential fluctuation at the data input terminal of the memory circuit can be effectively suppressed. .

It is preferable that the second switching transistor is connected between an N-type transistor constituting the feedback inverter and the low potential power supply terminal.
With this configuration, the parasitic capacitance of the second switching transistor is charged by both the low-potential power supply terminal and the N-type transistor. As a result, potential fluctuations at the data input terminal of the memory circuit can be suppressed, noise generation can be suppressed, and operation reliability can be improved.

The feedback inverter may include a plurality of N-type transistors, and the second switching transistor may be connected between the plurality of N-type transistors.
Also in this case, since the parasitic capacitance of the second switching transistor is charged by the two N-type transistors arranged on both sides, the potential fluctuation at the data input terminal of the memory circuit can be effectively suppressed. .

A scanning line driving circuit having a level shifter and a buffer and connected to the scanning line and the inverted scanning line; the scanning line being connected to the level shifter via the buffer; Is preferably connected between a plurality of inverters constituting the buffer.
With such a configuration, the inverted scanning signal supplied to the inverted scanning line can be easily extracted. Since a buffer is not required for the reverse scanning line, the circuit can be realized without increasing the scale of the scanning line driving circuit.
Further, since the supply of the inverted scanning signal to the inverted scanning line is earlier than the signal supply to the scanning line, the second switching transistor can be turned on / off prior to the first switching transistor. As a result, when the input of the image signal to the pixel is started (when the pixel switching element is turned on), the charging of the parasitic capacitance in the second switching transistor has already been started or has been finished. Therefore, potential fluctuations at the data input terminal of the memory circuit accompanying charging of the parasitic capacitance can be suppressed. Therefore, according to the present invention, it is possible to realize an electrophoretic display device that hardly generates noise and has excellent operation reliability.

A scanning line driving circuit having a level shifter and first and second buffers and connected to the scanning line and the inverted scanning line, the scanning line being connected to the level shifter via the first buffer; It is preferable that the inverted scanning line is connected to the input terminal of the level shifter via the second buffer.
Even in such a configuration, since the signal supply to the inverted scanning line is started before the signal supply to the scanning line, the electrophoretic display device having excellent operation reliability as in the previous configuration. Can be realized.

A scanning line driving circuit having first and second level shifters and first and second buffers and connected to the scanning lines and the inversion scanning lines, wherein the scanning lines include the first buffer; It is preferable that the first scanning line is connected to the first level shifter via the first buffer, and the inverted scanning line is connected to the second level shifter via the second buffer.
With such a configuration, since signals are simultaneously supplied to the scanning line and the inverted scanning line, the first and second switching transistors are switched simultaneously when an image signal is input to the pixel. At this time, the parasitic capacitance is charged by each switching transistor. However, since the potential of the gate terminal of the first switching transistor and the potential of the gate terminal of the second switching transistor are inverted from each other, the parasitic capacitance is charged. Therefore, the drain potentials to be varied are different from each other. Therefore, potential fluctuations due to the operation of charging each other's parasitic capacitances cancel each other out. As a result, potential fluctuations at the data input terminals are suppressed, and noise is less likely to occur.

It is preferable that a switch circuit for switching connection between a plurality of control lines and the pixel electrode is provided for each pixel based on the output of the memory circuit.
With such a configuration, the image signal input to the memory circuit and the voltage applied to the pixel electrode for driving the electrophoretic element can be set to different potentials, and the image display can be performed. The degree of freedom of control is also improved. Further, by appropriately setting the potential state of the control line, leakage current can be prevented and power consumption can be reduced.

First and second control lines are connected to the switch circuit, and the switch circuit selectively selects the first and second control lines based on the output of the memory circuit, and the pixel electrode. It is preferable to connect with.
With such a configuration, an electrophoretic display device that has a simple configuration and a high degree of freedom in display control and that can reduce power consumption can be obtained.

Next, an electronic apparatus according to the present invention includes the electrophoretic display device according to the present invention described above.
According to this configuration, it is possible to provide an electronic device including a display unit that is excellent in operation reliability and manufacturability. In addition, an electronic device including a display unit with low power consumption can be provided.

The electrophoretic display device according to the present invention will be described below with reference to the drawings. In the present embodiment, an electrophoretic display device driven by an active matrix method will be described.
Note that this embodiment shows one aspect of the present invention, and does not limit the present invention, and can be arbitrarily changed within the scope of the technical idea of the present invention. Moreover, in the following drawings, in order to make each configuration easy to understand, the actual structure is different from the scale and number of each structure.

(First embodiment)
FIG. 1 is a schematic configuration diagram of an active matrix drive type electrophoretic display device 1.
The electrophoretic display device 1 includes a display unit 5 in which a plurality of pixels 40 are arranged. Around the display unit 5, a scanning line driving circuit 61, a data line driving circuit 62, a controller (control unit) 63, and a common power supply modulation circuit 64 are arranged. The scanning line driving circuit 61, the data line driving circuit 62, and the common power supply modulation circuit 64 are each connected to the controller 63. The controller 63 comprehensively controls these based on image data and synchronization signals supplied from the host device.

  The display unit 5 is provided with a plurality of scanning lines 66 extending from the scanning line driving circuit 61 and a plurality of data lines 68 extending from the data line driving circuit 62, and the pixels 40 are provided corresponding to the intersection positions thereof. Yes.

  The scanning line driving circuit 61 is connected to each pixel 40 via m scanning lines 66 (Y1, Y2,..., Ym). Under the control of the controller 63, the first to mth rows are connected. The scanning lines 66 are sequentially selected, and a selection signal defining the ON timing of the driving TFT 41 (see FIG. 2) provided in the pixel 40 is supplied via the selected scanning line 66.

The data line driving circuit 62 is connected to each pixel 40 via n data lines 68 (X1, X2,..., Xn), and corresponds to each pixel 40 under the control of the controller 63. An image signal defining 1-bit image data is supplied to the pixel 40.
In this embodiment, a low level image signal is supplied to the pixel 40 when the image data “0” is defined, and a high level image signal is supplied to the pixel 40 when the image data “1” is defined. It shall be.

The display unit 5 is also provided with a low potential power line 49, a high potential power line 50, a common electrode wiring 55, a first control line 91, and a second control line 92 extending from the common power modulation circuit 64. . Each wiring is connected to the pixel 40. Under the control of the controller 63, the common power supply modulation circuit 64 generates various signals to be supplied to each of the above wirings, and electrically connects and disconnects these wirings (high impedance).
In FIG. 1, the first control line 91 and the second control line 92 are represented by a single wiring, but they are actually independent wirings (see FIG. 2).

FIG. 2 is a circuit configuration diagram of the pixel 40.
As illustrated in FIG. 2, the pixel 40 includes a driving TFT (Thin Film Transistor) 41 (pixel switching element), a latch circuit (memory circuit) 70, a switch circuit 80, an electrophoretic element 32, and a pixel electrode 35. And a common electrode 37. A scanning line 66, a data line 68, a low-potential power line 49, and a high-potential power line 50 are arranged so as to surround these elements. The pixel 40 has an SRAM (Static Random Access Memory) type configuration in which the latch circuit 70 holds an image signal as a potential.

  The driving TFT 41 is a pixel switching element composed of an N-MOS (Negative Metal Oxide Semiconductor) transistor. The gate terminal of the driving TFT 41 is connected to the scanning line 66, the source terminal is connected to the data line 68, and the drain terminal is connected to the data input terminal N 1 of the latch circuit 70. The switch circuit 80 is connected to the data output terminal N 2 and the data input terminal N 1 of the latch circuit 70 and the pixel electrode 35. The electrophoretic element 32 is sandwiched between the pixel electrode 35 and the common electrode 37.

  The latch circuit 70 includes a transfer inverter 70t, a feedback inverter 70f, a first switching transistor 75, and a second switching transistor 76. Both the transfer inverter 70t and the feedback inverter 70f are C-MOS inverters. The first switching transistor 75 is a P-MOS transistor, and the second switching transistor 76 is an N-MOS transistor.

  The transfer inverter 70t and the feedback inverter 70f have a loop structure in which the other output terminal is connected to each other's input terminal, and each inverter has a high potential power line 50 connected via a high potential power terminal PH. Then, a power supply voltage is supplied from the low potential power supply line 49 connected via the low potential power supply terminal PL.

  The transfer inverter 70t includes a P-MOS transistor 71 and an N-MOS transistor 72 whose drain terminals are connected to the data output terminal N2, and the source terminal of the P-MOS transistor 71 is connected to the high potential power supply terminal PH. The source terminal of the N-MOS transistor 72 is connected to the low potential power supply terminal PL. The gate terminals of the P-MOS transistor 71 and the N-MOS transistor 72 (the input terminal of the transfer inverter 70t) are connected to the data input terminal N1.

  The feedback inverter 70f includes a P-MOS transistor 73 and an N-MOS transistor 74 whose drain terminals are connected to the data input terminal N1, and the gate terminals (feedback inverters) of the P-MOS transistor 73 and the N-MOS transistor 74. 70f input terminal) is connected to the data output terminal N2 (the output terminal of the transfer inverter 70t). The source terminal of the P-MOS transistor 73 is connected to the drain terminal of the first switching transistor 75. The source terminal of the N-MOS transistor 74 is connected to the drain terminal of the second switching transistor 76.

The first switching transistor 75 is connected between the feedback inverter 70f and the high potential power supply terminal PH. The gate terminal of the first switching transistor 75 is connected to the scanning line 66 common to the gate terminal of the driving TFT 41, the source terminal is connected to the high potential power supply terminal PH, and the drain terminal is the source terminal of the P-MOS transistor 73. Connected with.
The second switching transistor 76 is connected between the feedback inverter 70f and the low potential power supply terminal PL. The gate terminal of the second switching transistor 76 is connected to the inversion scanning line 67, the source terminal is connected to the low potential power supply terminal PL, and the drain terminal is connected to the source terminal of the N-MOS transistor 74.

The switch circuit 80 includes a first transmission gate TG1 and a second transmission gate TG2.
The first transmission gate TG1 includes an N-MOS transistor 81 and a P-MOS transistor 82. The source terminals of the N-MOS transistor 81 and the P-MOS transistor 82 are connected to the first control line 91, and the drain terminals of the N-MOS transistor 81 and the P-MOS transistor 82 are connected to the pixel electrode 35. The gate terminal of the N-MOS transistor 81 is connected to the drain terminal of the driving TFT 41 (data input terminal N1 of the latch circuit 70), and the gate terminal of the P-MOS transistor 82 is connected to the data output terminal N2 of the latch circuit 70. It is connected to the.

  The second transmission gate TG 2 includes an N-MOS transistor 83 and a P-MOS transistor 84. The source terminals of the N-MOS transistor 83 and the P-MOS transistor 84 are connected to the second control line 92, and the drain terminals of the N-MOS transistor 83 and the P-MOS transistor 84 are connected to the pixel electrode 35. The gate terminal of the N-MOS transistor 83 is connected to the data output terminal N 2 of the latch circuit 70, and the gate terminal of the P-MOS transistor 84 is connected to the drain electrode of the driving TFT 41.

Here, when image data “1” (high level image signal) is stored in the latch circuit 70 and a low level signal is output from the data output terminal N2, the first transmission gate TG1 is turned on, and the first A signal S 1 supplied via one control line 91 is supplied to the pixel electrode 35. On the other hand, when the image data “0” (low level image signal) is stored in the latch circuit 70 and a high level signal is output from the data output terminal N2, the second transmission gate TG2 is turned on, The signal S 2 supplied via the control line 92 is supplied to the pixel electrode 35.
In the present embodiment, the configuration in which the data output terminal N2 of the latch circuit 70 is connected to the switch circuit 80 is described as a preferred mode. However, the output terminal N2 is connected to the pixel electrode as in the conventional pixel 540 in FIG. A configuration in which a direct connection to 35 is possible. Even with this configuration, an image can be displayed on the electrophoretic element 32 in accordance with an output signal from the latch circuit 70. The same applies to each embodiment described below.

The pixel electrode 35 is formed of Al (aluminum) or the like, and applies a voltage to the electrophoretic element 32. The pixel electrode 35 is connected to the first transmission gate TG1 and the second transmission gate TG2.
The common electrode 37 has a function as a counter electrode of the pixel electrode 35 and is a transparent electrode formed of MgAg (magnesium silver), ITO (indium tin oxide), IZO (indium zinc oxide) or the like. The common electrode potential Vcom is supplied through the common electrode wiring 55. The electrophoretic element 32 is sandwiched between the pixel electrode 35 and the common electrode 37, and displays an image by an electric field generated by a potential difference between the pixel electrode 35 and the common electrode 37.

FIG. 3 is a diagram partially showing a wiring structure of the scanning line driving circuit 61.
The scanning line driving circuit 61 includes a level shifter 111 and a buffer 116 provided for each scanning line 66.
The level shifter 111 is a circuit that adjusts the potentials of the scanning signal and the inverted scanning signal. Specifically, in order to supply a sufficient gate voltage to the driving TFT 41, the high level potential of the scanning signal is adjusted to a potential higher than the high level potential of the image signal output from the data line driving circuit 62.
The buffer 116 is a circuit that amplifies the current of the scanning signal and the inverted scanning signal supplied from the level shifter 111. By providing the buffer 116, it is possible to reliably input a scanning signal to the pixel 40 at a position away from the scanning line driving circuit 61.

The input terminal of the level shifter 111 is connected to a signal line 112 to which a scanning signal is supplied and an inverted signal line 113 to which an inverted scanning signal whose potential is inverted with respect to the scanning signal is supplied. A buffer 116 is connected to the output terminal of the level shifter 111.
The buffer 116 includes first and second inverters INV1 and INV2 connected in series, and the scanning line 66 is connected to the output terminal of the second inverter INV2, which is the output terminal of the buffer 116. The inverted scanning line 67 is connected between the first inverter INV1 and the second inverter INV2, and the scanning signal inverted by the first inverter INV1 is supplied to the inverted scanning line 67 as an inverted scanning signal.

  FIG. 4 is a partial cross-sectional view of the electrophoretic display device 1 in the display unit 5. The electrophoretic display device 1 has a configuration in which an electrophoretic element 32 formed by arranging a plurality of microcapsules 20 is sandwiched between an element substrate 30 and a counter substrate 31. In the display unit 5, a plurality of pixel electrodes 35 are arranged on the electrophoretic element 32 side of the element substrate 30, and the electrophoretic elements 32 are bonded to the pixel electrodes 35 through an adhesive layer 33. A common electrode 37 having a planar shape facing the plurality of pixel electrodes 35 is formed on the electrophoretic element 32 side of the counter substrate 31, and the electrophoretic element 32 is provided on the common electrode 37.

  The element substrate 30 is a substrate made of glass, plastic, or the like and is not required to be transparent because it is disposed on the side opposite to the image display surface. Although not shown, between the pixel electrode 35 and the element substrate 30, the scanning line 66, the data line 68, the driving TFT 41, the latch circuit 70, the switch circuit 80, and the like shown in FIGS. Is formed.

The counter substrate 31 is a substrate made of glass, plastic, or the like, and is a transparent substrate because it is disposed on the image display side. The common electrode 37 formed on the counter substrate 31 is formed using a transparent conductive material such as MgAg (magnesium silver), ITO (indium tin oxide), or IZO (indium zinc oxide).
In general, the electrophoretic element 32 is formed in advance on the counter substrate 31 side, and is handled as an electrophoretic sheet including the adhesive layer 33. In the manufacturing process, the electrophoretic sheet is handled with a protective release paper attached to the surface of the adhesive layer 33. And the display part 5 is formed by sticking the said electrophoretic sheet which peeled off the release paper with respect to the element substrate 30 (The pixel electrode 35, various circuits, etc.) which were manufactured separately. For this reason, the adhesive layer 33 exists only on the pixel electrode 35 side.

  FIG. 5 is a schematic cross-sectional view of the microcapsule 20. The microcapsule 20 has a particle size of, for example, about 50 μm and encloses therein a dispersion medium 21, a plurality of white particles (electrophoretic particles) 27, and a plurality of black particles (electrophoretic particles) 26. It is a spherical body. As shown in FIG. 4, the microcapsule 20 is sandwiched between the common electrode 37 and the pixel electrode 35, and one or more microcapsules 20 are arranged in one pixel 40.

The outer shell (wall film) of the microcapsule 20 is formed using a transparent polymer resin such as acrylic resin such as polymethyl methacrylate and polyethyl methacrylate, urea resin, and gum arabic.
The dispersion medium 21 is a liquid that disperses the white particles 27 and the black particles 26 in the microcapsules 20. Examples of the dispersion medium 21 include water, alcohol solvents (methanol, ethanol, isopropanol, butanol, octanol, methyl cellosolve, etc.), esters (ethyl acetate, butyl acetate, etc.), ketones (acetone, methyl ethyl ketone, methyl isobutyl ketone, etc.). ), Aliphatic hydrocarbons (pentane, hexane, octane, etc.), alicyclic hydrocarbons (cyclohexane, methylcyclohexane, etc.), aromatic hydrocarbons (benzene, toluene, benzenes having a long-chain alkyl group ( Xylene, hexylbenzene, hebutylbenzene, octylbenzene, nonylbenzene, decylbenzene, undecylbenzene, dodecylbenzene, tridecylbenzene, tetradecylbenzene)), halogenated hydrocarbons (methylene chloride, chloroform, tetrachloride) Element, and 1,2-dichloroethane), can be exemplified a carboxylate, it may be other oils. These substances can be used alone or as a mixture, and a surfactant or the like may be further blended.

The white particles 27 are particles (polymer or colloid) made of a white pigment such as titanium dioxide, zinc white, and antimony trioxide, and are used, for example, by being negatively charged. The black particles 26 are particles (polymer or colloid) made of a black pigment such as aniline black or carbon black, and are used by being charged positively, for example.
These pigments include electrolytes, surfactants, metal soaps, resins, rubbers, oils, varnishes, compound charge control agents, titanium-based coupling agents, aluminum-based coupling agents, silanes as necessary. A dispersant such as a system coupling agent, a lubricant, a stabilizer, and the like can be added.
Further, instead of the black particles 26 and the white particles 27, for example, pigments such as red, green, and blue may be used. According to such a configuration, red, green, blue, or the like can be displayed on the display unit 5.

FIG. 6 is an operation explanatory diagram of the electrophoretic element. FIG. 6A shows a case where the pixel 40 displays white, and FIG. 6B shows a case where the pixel 40 displays black.
In the case of white display shown in FIG. 6A, the common electrode 37 is held at a relatively high potential and the pixel electrode 35 is held at a relatively low potential. As a result, the negatively charged white particles 27 are attracted to the common electrode 37, while the positively charged black particles 26 are attracted to the pixel electrode 35. As a result, when this pixel is viewed from the common electrode 37 side which is the display surface side, white is recognized.
In the case of black display shown in FIG. 6B, the common electrode 37 is held at a relatively low potential, and the pixel electrode 35 is held at a relatively high potential. As a result, the positively charged black particles 26 are attracted to the common electrode 37, while the negatively charged white particles 27 are attracted to the pixel electrode 35. As a result, when this pixel is viewed from the common electrode 37 side, black is recognized.

  In the electrophoretic display device 1 having the above configuration, an image signal is input to the data input terminal N1 of the latch circuit 70 via the driving TFT 41, and the image signal is stored in the latch circuit 70 as a potential. Then, by operating the switch circuit 80 based on the potential output from the data output terminal N2 based on the stored potential, the first and second control lines 91 and 92 are alternatively connected to the pixel electrode 35. Connecting. As a result, the control signal S1 or the control signal S2 is input to the pixel electrode 35, and the pixel 40 is displayed in black or white based on the potential difference from the common electrode 37 as shown in FIG.

  When an image signal is input to the latch circuit 70, a pulse-shaped selection signal is input to the scanning line 66, and a high level is input to the gate terminal of the driving TFT 41 of the pixel 40 to be operated. As a result, the driving TFT 41 is turned on, the data line 68 and the data input terminal N1 of the latch circuit 70 are electrically connected, and the image signal (high level, low level) supplied from the data line 68 is latched. It is stored in the circuit 70 as a potential.

  In the electrophoretic display device 1 of the present embodiment, as shown in FIG. 2, a first switching transistor 75 is provided between the P-MOS transistor 73 and the high potential power supply terminal PH, and the N-MOS transistor 74 and the low potential power supply terminal PH. Since the second switching transistor 76 is provided between the potential power supply terminal PL, the image signal can be reliably written to the latch circuit 70 described above. Hereinafter, this operation will be described in detail.

When an image signal having a potential different from the potential held in the latch circuit 70 is written and the data of the latch circuit 70 is updated, the data input is performed against the P-MOS transistor 73 or the N-MOS transistor 74 of the latch circuit 70. It is necessary to force the potential of the terminal N1 to be the potential of the image signal.
Therefore, normally, the current driving capability of the driving TFT 41 is designed to be larger than the current driving capability of the P-MOS transistor 73 and the N-MOS transistor 74 so that the image signal can be written reliably. That is, a TFT having a width larger than that of the P-MOS transistor 73 and the N-MOS transistor 74 and having a low on-resistance is used as the driving TFT 41.

  However, if the on-currents of the driving TFT 41, the P-MOS transistor 73, and the N-MOS transistor 74 deviate from the design values due to manufacturing variations, there is a possibility that the above-described data update of the latch circuit 70 may fail. In particular, when a TFT is manufactured by a low-temperature polysilicon process, the on-current per unit width may fluctuate by about 2 to 3 times, and the current driving capability of the driving TFT 41 may be lower than the design value. The on-resistance of the P-MOS transistor 73 and the N-MOS transistor 74 is likely to be low.

  In contrast, in the present embodiment, when a high level is supplied to the gate terminal of the driving TFT 41 when an image signal is input to the latch circuit 70, the first switching transistor 75, which is a P-MOS transistor, is turned off. And the feedback inverter 70f is disconnected from the high potential power supply terminal PH. The second switching transistor 76, which is an N-MOS transistor, also transitions to an off state by a low level input of an inverted scanning signal supplied via the inverted scanning line 67, and the feedback inverter 70f is switched from the low potential power supply terminal PL. Cut off.

First, when a low-level image signal is input to the latch circuit 70 that holds a high-level potential, data is input from the high-potential power supply terminal PH because the first switching transistor 75 is off. No current flows into the terminal N1. Therefore, the potential of the data input terminal N1 can be reliably set to the low level regardless of the strength relationship between the current driving capability between the driving TFT 41 and the P-MOS transistor 73.
When the data input terminal N1 becomes low level, the P-MOS transistor 71 of the transfer inverter 70t is driven and the data output terminal N2 becomes high level (Vdd), thereby turning off the P-MOS transistor 73 of the feedback inverter 70f. State, the N-MOS transistor 74 transitions to the ON state.
Thereafter, the potential of the scanning line 66 becomes low level and the potential of the inversion scanning line 67 becomes high level, so that the first and second switching transistors 75 and 76 are turned on. At this time, since the P-MOS transistor 73 of the feedback inverter 70f is off and the N-MOS transistor 74 is on, the potential of the data input terminal N1 of the latch circuit 70 is held at a low level (Vss). .

Similarly, when a high-level image signal is input to the latch circuit 70 that holds a low-level potential, the second switching transistor 76 is also in an off state, so that the data input terminal N1 No current flows to the low potential power supply terminal PL. Therefore, the potential of the data input terminal N1 can be reliably set to a high level regardless of the strength relationship of the current driving capability between the driving TFT 41 and the N-MOS transistor 74.
Then, the N-MOS transistor 72 of the transfer inverter 70t is turned on by the high level of the data input terminal N1, and the data output terminal N2 becomes low level (Vss). As a result, the N-MOS transistor 74 of the feedback inverter 70f is turned off and the P-MOS transistor 73 is turned on. After that, when the potential of the scanning line 66 becomes low level and the potential of the inverting scanning line 67 becomes high level, the first and second switching transistors 75 and 76 are turned on. At this time, since the P-MOS transistor 73 is in the on state, the potential of the data input terminal N1 is held at the high level (Vdd).

As described above, in the electrophoretic display device 1 of the present embodiment, the feedback inverter 70f can be disconnected from the power source by the first and second switching transistors 75 and 76, and thus there is a manufacturing variation in the semiconductor elements constituting the pixel 40. Even if it occurs, the image signal can be reliably written to the latch circuit 70.
Therefore, the electrophoretic display device according to the present embodiment is an electrophoretic display device that is excellent in manufacturability having a configuration capable of suppressing the influence of manufacturing variations, and also excellent in reliability related to circuit operation.

  The first and second switching transistors 75 and 76 are always in the off state when the P-MOS transistor 73 and the N-MOS transistor 74 of the feedback inverter 70f are switched on and off. Thereby, even if the P-MOS transistor 73 and the N-MOS transistor 74 are switched on at the same time, the through current can be prevented from flowing through the feedback inverter 70f. Therefore, power consumption can be reduced in the electrophoretic display device of this embodiment.

Further, since the first and second switching transistors 75 and 76 are provided, the image signal can be reliably input to the latch circuit 70 even if the current driving capability of the driving TFT 41 is small. The gate area (product of gate width and gate length) of the driving TFT 41 can be reduced. Further, by narrowing the formation region of the driving TFT 41, the total area of the pixel circuit can be reduced, and the electrophoretic display device can easily cope with high definition of the pixel.
Further, since the parasitic capacitance is reduced by reducing the gate area, the potential fluctuation of the data input terminal N1 due to the charging of the parasitic capacitance is reduced, and malfunction of the latch circuit 70 due to noise can be prevented.
Furthermore, by reducing the gate area, the load capacity of the scanning line 66 can be reduced. Therefore, a sufficient current can be secured even if the buffer 116 for driving the scanning line 66 is made small. Thereby, the scanning line driving circuit 61 can be made small, and the electrophoretic display device can be narrowed.

The gate area of the driving TFT 41 is preferably less than twice the gate area of the transistors (P-MOS transistors 71 and 73 and N-MOS transistors 72 and 74) constituting the latch circuit 70. By setting it as such a range, the effect mentioned above can be acquired more reliably.
In addition, the gate area of the driving TFT 41 is preferably set to be 1/2 or more of the gate area of the transistors constituting the latch circuit 70. With such a range, the above-described effects can be obtained while ensuring the current driving capability of the driving TFT 41.

In the present embodiment, the first switching transistor 75 is connected between the P-MOS transistor 73 and the high potential power supply terminal PH. According to this configuration, the parasitic capacitance of the first switching transistor 75 is charged by the P-MOS transistor 73 and the high-potential power supply line 50, so that a potential fluctuation occurs at the data input terminal N1 of the latch circuit 70. It becomes difficult.
The second switching transistor 76 is also charged with parasitic capacitance by the N-MOS transistor 74 and the low-potential power line 49, so that the potential fluctuation at the data input terminal N1 hardly occurs.
Therefore, according to the present embodiment, it is possible to suppress the generation of noise due to the potential fluctuation of the data input terminal N1, and it is possible to realize an electrophoretic display device including a pixel circuit that hardly causes a malfunction.

  As shown in FIG. 3, the scanning line driving circuit 61 according to the present embodiment has a configuration in which the inverted scanning line 67 is branched from the middle of the buffer 116 connected to the scanning line 66. As a result, there is no need to form a level shifter or a buffer for supplying the inverted scanning signal to the inverted scanning line 67, so that the inverted scanning line 67 can be driven without increasing the circuit scale of the scanning line driving circuit 61. realizable.

  Further, according to the above configuration, the signal input to the inversion scanning line 67 is earlier than the signal input to the scanning line 66 by the delay time of the second inverter INV2. As a result, the second switching transistor 76 that is switched by the inverted scanning signal transitions to the off state earlier than the driving TFT 41 and the first switching transistor 75 transition to the on state and the off state, respectively. Therefore, the feedback inverter 70f and the low-potential power supply terminal PL can be electrically disconnected at an early timing, and the through current of the feedback inverter 70f can be reliably prevented.

In addition, since the second switching transistor 76 is turned on earlier than the first switching transistor 75, the parasitic capacitances of the first and second switching transistors 75 and 76 are not charged simultaneously. . Therefore, the potential fluctuation of the data input terminal N1 accompanying the charging of the parasitic capacitance can be more effectively suppressed.
These effects can be similarly obtained even when a circuit configuration in which the data output terminal N2 of the latch circuit 70 is directly connected to the pixel electrode 35 is employed. The same applies to each embodiment described below.

[Driving method]
Next, a driving method of the electrophoretic display device 1 of the present invention will be described.
Table 1 shows the potential of each wiring and electrode in the following description of the driving method. FIG. 7 is a diagram illustrating a timing chart in the driving method of the present embodiment. FIG. 8A is a diagram showing a potential relationship between the pixels 40A and 40B in the black image display period ST101 shown in FIG. FIG. 8B is a diagram showing a potential relationship between the pixels 40A and 40B in the white image display period ST102 shown in FIG.
In FIGS. 7 and 8, the subscripts “A”, “B”, “a”, and “b” of the reference numerals clearly distinguish the two pixels 40 that are the object of description from the constituent elements that belong to them. There is no other intention.

Table 1 shows the image signal Da input to the pixel 40A, the image signal Db input to the pixel 40B, the potential Va of the pixel electrode 35a, the potential Vb of the pixel electrode 35b, and the potential S1 of the first control line 91. , And the potential S2 of the second control line 92 is shown.
FIG. 7 also shows the potential S1 of the first control line 91, the potential S2 of the second control line 92, the potential Va of the pixel electrode 35a, the potential Vb of the pixel electrode 35b, and the potential Vcom of the common electrode 37. ing.

  The driving method of the electrophoretic display device according to the present invention is based on the first step of inputting an image signal to the latch circuit 70 via the driving TFT 41 and the output of the latch circuit 70 holding the image signal. The second step of displaying an image by connecting the first or second control line 91, 92 selected by the switch circuit 80 and the pixel electrode 35 and inputting a potential to the pixel electrode 35. And having.

  FIG. 7 shows an image display period ST100, which is the second step of the above driving method, and a subsequent power-off period ST105. In the image display period ST100, a black image display period ST101 and a white image display period ST102 are sequentially executed.

In this driving method, an image signal is input to the latch circuit 70 (70a, 70b) of the pixel 40 (40A, 40B) prior to the image display period ST100 (first step).
In the pixel 40A displayed in black, the high level (H) is supplied to the data line 68a, and the high level (H) is input to the latch circuit 70a via the driving TFT 41a. On the other hand, in the pixel 40B displayed in white, the low level (L) is supplied to the data line 68b, and the low level (L) is input to the latch circuit 70b via the driving TFT 41b.

When an image signal is input to the latch circuits 70a and 70b, the potential of the high potential power line 50 is set to a high level (Vdd) for image display, and the potential of the low potential power line 49 is set to a low level (Vss). Is done. Thereby, the potential of the data input terminal N1a in the pixel 40A becomes high level (Vdd), and the potential of the data output terminal N2a becomes low level (Vss). Further, the potential of the data input terminal N1b in the pixel 40B is low level (Vss), and the potential of the data output terminal N2b is high level (Vdd).
As described above, after an image signal is input to the latch circuits 70a and 70b of the pixels 40A and 40B, the process proceeds to the image display period ST100 (second step).

When a transition is made to the black image display period ST101 in the image display period ST100, a high-level potential VH is supplied to the first control line 91 as shown in FIGS. Is in a high impedance state where it is electrically disconnected.
In the pixel 40A to which a high level (H) image signal is input, the potential of the data input terminal N1a is high level (Vdd), and the potential of the data output terminal N2a is low level (Vss). As a result, the transmission gate TG1a of the switch circuit 80a is turned on, and the high level potential VH is input from the first control line 91 to the pixel electrode 35a. The common electrode 37 receives a pulse-like signal that periodically repeats a high level (VH) period and a low level (VL) period.

Then, during the period in which the common electrode 37 is at the low level (VL), the positively charged black particles 26 are caused to become common electrode due to the potential difference between the pixel electrode 35a and the common electrode 37 as shown in FIG. The white particles 27 attracted to the 37 side and negatively charged are attracted to the pixel electrode 35a side, and the pixel 40A is displayed in black.
Note that during the period in which the common electrode 37 is at the high level (VH), both the pixel electrode 35a and the common electrode 37 are at the high level (VH), and no potential difference is generated, so the electrophoretic particles do not move.

  On the other hand, in the pixel 40B to which the low level (L) image signal is input, the potential of the data input terminal N1b is low level (Vss), and the potential of the data output terminal N2b is high level (Vdd). As a result, the transmission gate TG2b of the switch circuit 80b is turned on, and the second control line 92 and the pixel electrode 35b are connected. At this time, since the second control line 92 is in a high impedance state (Hi-Z), the pixel electrode 35b is in a high impedance state. The current display is maintained regardless of the potential of the common electrode 37.

Next, when the white image display period ST102 is entered, as shown in FIGS. 7 and 8B, the low-level potential VL is supplied to the second control line 92, and the first control line 91 has a high impedance. State.
In the pixel 40A to which a high-level (H) image signal is input, the first control line 91 and the pixel electrode 35a are connected via the transmission gate TG1a of the switch circuit 80a. Therefore, the pixel electrode 35a is in a high impedance state, and the black display made in the black image display period ST101 is maintained.

On the other hand, in the pixel 40B to which the low level (L) image signal is input, the second control line 92 and the pixel electrode 35b are connected via the transmission gate TG2b of the switch circuit 80b. Therefore, the low-level potential VL is input to the pixel electrode 35b.
Since a pulse-like signal that periodically repeats the high level (VH) and low level (VL) periods is input to the common electrode 37, the pixels in the period when the common electrode 37 is at the high level (VH) are input. A potential difference is generated between the electrode 35 b and the common electrode 37. As a result, as shown in FIG. 6A, the negatively charged white particles 27 are attracted to the common electrode 37 side, and the positively charged black particles 26 are attracted to the pixel electrode 35a side. Displayed in white. Note that during the period when the common electrode 37 is at a low level (VL), the electrophoretic particles do not move because no potential difference is generated between the pixel electrode and the common electrode.

  When the white image display period ST102 is followed by the power supply off period ST105, the first and second control lines 91 and 92 and the common electrode 37 are electrically disconnected by the common power supply modulation circuit 64 and become a high impedance state. . Thereby, the pixel electrodes 35a and 35b connected to one of the first and second control lines 91 and 92 are also in a high impedance state. Thus, in the power-off period ST105, the electrophoretic element 32 is in an electrically isolated state, and an image can be held without consuming power.

In the driving method according to the present embodiment, in the image display period ST100, a pulse signal that periodically repeats a high level (VH) and a low level (VL) is input to the common electrode 37 for a plurality of periods.
This driving method is referred to as “common swing driving” in the present application. In addition, the definition of common swing driving is a driving method in which a pulse that repeats a high level (VH) and a low level (VL) is applied to the common electrode 37 for at least one period in the image display period ST100.

According to this common swing driving method, the black particles and the white particles can be moved to the desired electrode more reliably, so that the contrast can be increased. Further, since the potential applied to the pixel electrode and the common electrode can be controlled by binary values of high level (VH) and low level (VL), the voltage can be lowered and the circuit configuration can be simplified. Further, when a TFT is used as the switching element of the pixel electrode 35, there is an advantage that the reliability of the TFT can be secured by low voltage driving.
In addition, it is preferable that the frequency and the number of cycles of the common swing drive are appropriately determined according to the specifications and characteristics of the electrophoretic element 32.

  According to the driving method of the present embodiment described above, it is possible to effectively prevent the occurrence of leakage current due to the potential difference between the pixel electrodes 35a and 35b. Hereinafter, the effect of preventing the leakage current will be described.

In the electrophoretic display device, in order to sufficiently move the electrophoretic particles to ensure contrast, it is common to apply a voltage of 10 V or more between the pixel electrode 35 and the common electrode 37. Then, as shown in each figure of FIG. 8, when the black display pixel 40A and the white display pixel 40B are adjacent to each other, if a voltage is simultaneously applied to the pixel electrodes 35a and 35b, 10V is applied between the pixel electrodes 35a and 35b. Due to the above potential difference, a strong lateral electric field is formed.
When the electric field is formed, a leak current flows through the adhesive layer 33 due to the influence of slight moisture contained in the adhesive layer 33. In FIG. 8, when the pixel electrode 35a is at a high level and the pixel electrode 35b is at a low level, the leakage current is routed from the first control line 91 to the switch circuit 80a, the pixel electrode 35a, and the adhesive layer 33. This is a path that reaches the second control line 92 via the pixel electrode 35b and the switch circuit 80b.

  On the other hand, in the driving method of the present embodiment, the black image display period ST101 and the white image display period ST102 are provided as separate periods. Therefore, in the black image display period ST101, the second control line 92 is in a high impedance state. In the white image display period ST102, the first control line 91 can be in a high impedance state. As a result, the above-described leakage path is blocked, and the occurrence of leakage current can be prevented. Therefore, according to the present embodiment, power consumption in the entire electrophoretic display device can be reduced.

  Although the above-described effect of preventing leakage current cannot be obtained, it is also possible to perform image display in parallel with the black image display period ST101 and the white image display period ST102. That is, the first control line 91 and the second control line 92 are simultaneously driven, and the voltage application to the pixel electrodes 35a and 35b of the pixels 40A and 40B is simultaneously performed. Thereby, the time required for image display can be shortened.

[Modification]
Next, a modification of the present embodiment will be described with reference to FIGS. The electrophoretic display device according to the modification is obtained by changing the configuration of the scanning line driving circuit.
FIG. 9 is a diagram partially showing a circuit configuration of the scanning line driving circuit 261 provided in the electrophoretic display device according to the first modification. FIG. 10 is a diagram partially showing a circuit configuration of the scanning line driving circuit 361 provided in the electrophoretic display device according to the second modification.

  First, the scanning line drive circuit 261 according to the first modification includes a level shifter 111 provided corresponding to each scanning line 66 and a first buffer 216 as shown in FIG. Further, a second buffer 217 provided corresponding to the reverse scanning line 67 is provided.

  The first inverter INV1a and the second inverter INV2a constituting the first buffer 216 are connected in series to the output terminal of the level shifter 111, and the scanning line 66 is connected to the output terminal of the second inverter INV2a. ing. The second buffer 217 includes a first inverter INV1b and a second inverter INV2b connected in series, and the input terminal of the first inverter INV1a is connected to the input terminal of the inverted scanning signal of the level shifter 111. Has been. An inversion scanning line 67 is connected to the output terminal of the second inverter INV2b.

  According to the scanning line driving circuit 261 having the above configuration, since the inverting scanning line 67 is branched on the input terminal side of the level shifter 111, the inverting scanning line 67 is also inverted compared with the scanning line driving circuit 61 in the first embodiment. The signal input to the scanning line 67 is earlier than the signal input to the scanning line 66. Thereby, the timing at which the second switching transistor 76 transitions to the off state and the timing at which the second switching transistor 76 returns to the on state are earlier than the timing at which the state of the driving TFT 41 transitions. Therefore, the parasitic capacitance can be reliably charged when the second switching transistor 76 returns to the on state. Therefore, according to this modification, the potential fluctuation of the data input terminal N1 can be further reduced, and malfunction of the latch circuit 70 due to noise can be prevented more reliably.

  In the configuration according to the first modification, since the inverted scanning signal that does not pass through the level shifter 111 is supplied to the inverted scanning line 67, the inverted scanning supplied to the pixel 40 as compared with the configuration according to the first embodiment. The high level potential of the signal is lowered. However, since the second switching transistor 76 is connected to the low-potential power supply side of the feedback inverter 70f, and the high-level potential Vss is not applied, the second switching transistor 76 is the second inversion scanning signal even if the high-level potential is slightly low. This is sufficient for switching of the switching transistor 76.

  Next, as shown in FIG. 10, the scanning line driving circuit 361 according to the second modification includes a first level shifter 111 and a first buffer 216 provided corresponding to each scanning line 66, respectively. The second level shifter 311 and the second buffer 316 provided corresponding to the reverse scanning line 67 are provided.

  The wiring structure from the first level shifter 111 to the scanning line 66 is common to the first modification. On the other hand, the first inverter INV1c and the second inverter INV2c constituting the second buffer 316 are connected in series to the output terminal of the second level shifter 311 and inverted to the output terminal of the second inverter INV2c. A scanning line 67 is connected. The first level shifter 111 outputs a scanning signal from its output terminal, and the second level shifter 311 outputs an inverted scanning signal from its output terminal.

According to the scanning line driving circuit 361 having the above configuration, the signal input to the scanning line 66 and the signal input to the inverted scanning line 67 are made almost simultaneously. Therefore, the driving TFT 41 of the pixel 40 and the first and second switching transistors 75 and 76 change state almost simultaneously. Then, after the input of the image signal to the pixel 40, the parasitic capacitance charging operation when the first switching transistor 75 returns to the on state and the parasitic capacitance when the second switching transistor 76 returns to the on state. The charging operation is performed at the same time.
At this time, since the first switching transistor 75 sets the drain terminal to the high level and the second switching transistor 76 attempts to set the drain terminal to the low level, the potential fluctuations at these drain terminals cancel each other, thereby inputting the data. The potential fluctuation at the terminal N1 is suppressed.
Therefore, according to the second modification, it is possible to suppress the occurrence of noise due to the potential fluctuation of the data input terminal N1, and to effectively prevent the malfunction of the latch circuit 70.

[Example]
Next, the results of circuit simulation as an example according to the first embodiment will be described with reference to FIGS.
FIG. 11 is a diagram illustrating a circuit simulation result in the electrophoretic display device of the first embodiment. FIG. 12 is a diagram showing a circuit simulation result when the potential of the inversion scanning line 67 is switched after the scanning line 66 in the pixel circuit shown in FIG.
In FIG. 11, “D” is the potential of the data line 68, “G” is the potential of the scanning line 66, “Gb” is the potential of the inverted scanning line 67, “N1” is the potential of the data input terminal N1, and “N2” is This is the potential of the data output terminal N2.

Specific conditions for the circuit simulation are as follows.
At time t10 shown in each graph of FIG. 11, the potential G of the scanning line 66 is set to 5 V (high level), and the potential D (3.3 V; high level) of the data line 68 is input to the data input terminal N1 of the latch circuit 70. did.
Next, the potential Gb of the inversion scanning line 67 was switched from 0 V (low level) to 5 V (high level) from time t11 to time t12 after a predetermined time elapsed from time t10.
Next, the potential G of the scanning line 66 was switched from 5 V (high level) to 0 V (low level) from time t13 to time t14 after the potential Gb of the inversion scanning line 67 became 5V.

  According to the simulation result of the potential of the data input terminal N1 for the above operation, the potential of the data input terminal N1 is from 3.3V (high level) to approximately 2.6V in the transition period when the potential G of the scanning line 66 is switched. Declined. However, when the potential G of the scanning line 66 subsequently shifts to 0 V (low level), the potential of the input terminal N1 returns to 3.3 V (high level) again, and 3.3 V (high level) at the data input terminal N1. Inversion of the image signal did not occur.

  Next, in FIG. 12, “D” is the potential of the data line 68, “G” is the potential of the scanning line 66, “Gb” is the potential of the inverted scanning line 67, “N1” is the potential of the data input terminal N1, and “ “N2” is the potential of the data output terminal N2.

Specific conditions for the circuit simulation are as follows.
12, the potential G of the scanning line 66 is set to 5 V (high level), and the potential D of the data line 68 (3.3 V; high level) is input to the data input terminal N1 of the latch circuit 70. did.
Next, the potential G of the scanning line 66 was switched from 5 V (high level) to 0 V (low level) from time t21 to time t22 after a predetermined time elapsed from time t20.
Next, from time t23 to t24 after the potential G of the scanning line 66 became 0V, the potential Gb of the inverted scanning line 67 was switched from 0V (low level) to 5V (high level).

  According to the simulation result of the potential of the data input terminal N1 in the above operation, the potential of the data input terminal N1 is increased from 3.3V (high level) to approximately 2.6V in the transition period in which the potential G of the scanning line 66 is switched. Temporarily declined. However, after that, the voltage again recovered to 3.3 V, and the inversion of the image signal at the data input terminal N1 did not occur.

  As described above, in the circuit simulation whose results are shown in FIG. 11 and FIG. 12, even if the timing for inputting the scanning signal (G) and the inverted scanning signal (Gb) is varied, the potential fluctuation of the data input terminal N1 There was no significant difference in width. This is considered to be because the first switching transistor 75 and the second switching transistor 76 are both arranged on the power supply side from the feedback inverter 70f. That is, since these switching transistors 75 and 76 are not directly connected to the data input terminal N1, it is considered that the potential fluctuation due to charging of the parasitic capacitance hardly affected the potential of the data input terminal N1.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.
FIG. 13 is a circuit configuration diagram of the pixel 240 provided in the electrophoretic display device according to the second embodiment. In FIG. 13, the same components as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

A pixel 240 illustrated in FIG. 13 includes a driving TFT 41, a latch circuit (memory circuit) 270, a switch circuit 80, a pixel electrode 35, an electrophoretic element 32, and a common electrode 37.
Since the configuration other than the latch circuit 270 (driving TFT 41, switch circuit 80, etc.) is common to the pixel 40 shown in FIG. 2, the latch circuit 270 will be mainly described below.

The latch circuit 270 includes a transfer inverter 70t, a feedback inverter 70f, a first switching transistor 75, and a second switching transistor 76.
In the pixel 240 according to this embodiment, the arrangement of the first and second switching transistors 75 and 76 is different from that of the first embodiment. That is, the first switching transistor 75 is connected between the P-MOS transistor 73 and the data input terminal N1, and the second switching transistor 76 is connected between the N-MOS transistor 74 and the data input terminal N1. Has been.

  Also in the electro-optical device including the pixel 240 having the above-described configuration, it is possible to obtain the same effects as the electro-optical device according to the first embodiment. That is, when the image signal is input to the latch circuit 270, the first switching transistor 75 connected to the scanning line 66 and the second switching transistor 76 connected to the inverted scanning line 67 are turned off. As a result, the data input terminal N1 of the latch circuit 270 is electrically disconnected from the high potential power supply terminal PH and the low potential power supply terminal PL by the switching transistors 75 and 76, respectively. It can be defined reliably. Therefore, an image signal can be reliably input to the latch circuit 270, and an electrophoretic display device excellent in manufacturability and operation reliability can be realized.

Also in the electrophoretic display device of this embodiment, the scanning line driving circuit 61 shown in the first embodiment and the scanning line driving circuits 261 and 361 according to the first and second modifications are all employed. Can do.
If the scanning line driving circuit 61 shown in FIG. 3 or the scanning line driving circuit 261 shown in FIG. 9 is used, a circuit that supplies an inverted scanning signal to the inverted scanning line 67 and a circuit that supplies a scanning signal to the scanning line 66 are used. Therefore, it is possible to input a signal to the inverted scanning line 67 without increasing the circuit scale of the scanning line driving circuit.
Further, when the scanning line driving circuit 361 shown in FIG. 10 is used, the first and second switching transistors 75 and 76 are turned on and off at the same time. , 76 is advantageous in that the potential fluctuation of the data input terminal N1 when the parasitic capacitance charging operation occurs can be suppressed.

[Example]
Next, the results of circuit simulation as an example according to the second embodiment will be described with reference to FIGS.
FIG. 14 is a diagram illustrating a circuit simulation result of an electrophoretic display device including the pixel 240 according to the second embodiment and the scanning line driving circuit 61 having the configuration illustrated in FIG. 3.
FIG. 15 is a diagram illustrating a circuit simulation result of the electrophoretic display device including the pixel 240 according to the second embodiment and the scanning line driving circuit 361 having the configuration illustrated in FIG. 10.
FIG. 16 is a diagram showing a circuit simulation result when the switching timing of the potential Gb of the inversion scanning line 67 is delayed from the switching timing of the scanning line 66 in the same configuration as the conditions shown in FIG. .
14 to 16, “D” is the potential of the data line 68, “G” is the potential of the scanning line 66, “Gb” is the potential of the inverted scanning line 67, “N1” is the potential of the data input terminal N1, and “ “N2” is the potential of the data output terminal N2.

Specific conditions of the circuit simulation corresponding to FIG. 14 are as follows.
At time t30 shown in each graph of FIG. 14, the potential G of the scanning line 66 is set to 5V (high level), and the potential D (3.3V; high level) of the data line 68 is applied to the data input terminal N1 of the latch circuit 270. I input it.
Next, the potential Gb of the reverse scanning line 67 was switched from 0 V (low level) to 5 V (high level) from time t31 to time t32 after a predetermined time elapsed from time t30.
Next, the potential of the scanning line 66 was switched from 5 V (high level) to 0 V (low level) from time t33 to time t34 after the potential Gb of the inversion scanning line 67 became 5V.

  According to the simulation result of the potential of the data input terminal N1 for the above operation, the potential of the data input terminal N1 is temporarily changed from 3.3 V (high level) to about 2 in the transition period when the potential G of the scanning line 66 is switched. Reduced to 6V. However, when the potential G of the scanning line 66 subsequently shifts to 0V (low level), the potential of the input terminal N1 returns to 3.3V (high level) again, and an image of 3.3V (high level) at the data input terminal N1. No signal inversion occurred.

Next, the specific conditions of the circuit simulation corresponding to FIG. 15 are as follows.
At time t40 shown in each graph of FIG. 15, the potential G of the scanning line 66 is set to 5V (high level), and the potential D (3.3V; high level) of the data line 68 is input to the data input terminal N1 of the latch circuit 270. did.
Next, an operation of switching the potential G of the scanning line 66 from 5 V (high level) to 0 V (low level) and a potential Gb of the inverted scanning line 67 from time t41 to time t42 after a predetermined time has elapsed from time t40. Was switched from 0 V (low level) to 5 V (high level).

  According to the simulation result of the potential of the data input terminal N1 in the above operation, the potential of the data input terminal N1 is 3.3 V (high level) in the transition period in which the potentials G and Gb of the scanning line 66 and the inverted scanning line 67 are switched. ) To about 2.4V. However, when the potential G of the scanning line 66 shifts to 0V (low level) and the potential Gb of the inverting scanning line 67 shifts to 5V (high level), the potential of the data input terminal N1 is again 3.3V (high level). Returning to FIG. 3, the inversion of the 3.3V (high level) image signal did not occur at the data input terminal N1.

Next, the specific conditions of the circuit simulation corresponding to FIG. 16 are as follows.
At time t50 shown in each graph of FIG. 16, the potential G of the scanning line 66 is set to 5V (high level), and the potential D (3.3V; high level) of the data line 68 is input to the data input terminal N1 of the latch circuit 270. did.
Next, the potential G of the scanning line 66 was switched from 5 V (high level) to 0 V (low level) from time t51 to time t52 after a predetermined time elapsed from time t50.
Next, from time t53 to time t54 after the potential G of the scanning line 66 became 0V, the potential Gb of the inverted scanning line 67 was switched from 0V (low level) to 5V (high level).

  According to the simulation result of the potential of the data input terminal N1 in the above operation, the potential of the data input terminal N1 is changed from 3.3V (high level) to about 2.3V in the transition period when the potential G of the scanning line 66 is switched. Temporarily declined. However, after that, the voltage recovered to 3.3 V, and no inversion of the image signal occurred.

  As described above, based on the circuit simulation results shown in FIGS. 14 to 16, the driving method (FIG. 14) for switching the potential Gb of the inversion scanning line 67 before the potential G of the scanning line 66 is the data input. It can be seen that this is the most preferable driving method for suppressing the potential fluctuation of the terminal N1. Therefore, the circuit configurations of the scanning line driving circuit 61 (FIG. 3) and the scanning line driving circuit 261 (FIG. 9) capable of performing such a driving method are effective in this embodiment.

"
(Third embodiment)
Next, a third embodiment of the present invention will be described.
FIG. 17 is a circuit configuration diagram of the pixel 340 provided in the electrophoretic display device according to the third embodiment. In FIG. 17, the same components as those in FIGS. 2 and 13 are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

  A pixel 340 illustrated in FIG. 17 includes a driving TFT 41, a latch circuit (memory circuit) 370, a switch circuit 380, a pixel electrode 35, an electrophoretic element 32, and a common electrode 37. Since the configuration other than the latch circuit 370 and the switch circuit 380 (the driving TFT 41, the pixel electrode 35, etc.) is the same as that of the pixel 40 shown in FIG. 2, the following mainly describes the latch circuit 370 and the switch circuit 380. explain.

  The latch circuit 370 includes a transfer inverter 370t, a feedback inverter 370f, a first switching transistor 75, and a second switching transistor 76.

  The transfer inverter 370t is a C-MOS inverter composed of two P-MOS transistors 71a and 71b and two N-MOS transistors 72a and 72b. The gate terminals of the P-MOS transistors 71a and 71b and the N-MOS transistors 72a and 72b are connected to the data input terminal N1 of the latch circuit 370.

The P-MOS transistors 71a and 71b are connected in series, the source terminal of the P-MOS transistor 71a is connected to the high potential power supply terminal PH, and the drain terminal of the P-MOS transistor 71b is the data output terminal N2 of the latch circuit 370. It is connected to the.
The N-MOS transistors 72a and 72b are connected in series, the source terminal of the N-MOS transistor 72a is connected to the low potential power supply terminal PL, and the drain terminal of the N-MOS transistor 72b is the data output terminal N2 of the latch circuit 370. It is connected to the.

  The feedback inverter 370f is a C-MOS inverter composed of two P-MOS transistors 73a and 73b and two N-MOS transistors 74a and 74b. In this embodiment, the first switching transistor 75 is connected between the two P-MOS transistors 73a and 73b, and the second switching transistor 76 is connected to the two N-MOS transistors 74a and 74b. Connected between.

That is, on the P channel side of the feedback inverter 370f, the P-MOS transistor 73a, the first switching transistor 75, and the P-MOS transistor 73b are connected in series in this order from the high potential power supply terminal PH side. The drain terminal of the P-MOS transistor 73b is connected to the data input terminal N1 of the latch circuit 370.
On the N channel side, an N-MOS transistor 74a, a second switching transistor 76, and an N-MOS transistor 74b are connected in series in this order from the low potential power supply terminal PL side. The drain terminal of the N-MOS transistor 74b is connected to the data input terminal N1 of the latch circuit 370.
Further, the gate terminals of the P-MOS transistors 73 a and 73 b and the N-MOS transistors 74 a and 74 b are connected to the data output terminal N 2 of the latch circuit 370.
The gate terminal of the first switching transistor 75 is connected to the scanning line 66, and the gate terminal of the second switching transistor 76 is connected to the inversion scanning line 67.

The switch circuit 380 includes a first transmission gate TG11 and a second transmission gate TG22.
The first transmission gate TG11 includes two N-MOS transistors 81a and 81b connected in series and two P-MOS transistors 82a and 82b connected in series.
The source terminals of the N-MOS transistor 81 a and the P-MOS transistor 82 a are connected to the first control line 91. The drain terminals of the N-MOS transistor 81 b and the P-MOS transistor 82 b are connected to the pixel electrode 35.
The gate terminals of the N-MOS transistors 81a and 81b are connected to the data input terminal N1 of the latch circuit 370, and the gate terminals of the P-MOS transistors 82a and 82b are connected to the data output terminal N2 of the latch circuit 370.

The second transmission gate TG22 includes two N-MOS transistors 83a and 83b connected in series and two P-MOS transistors 84a and 84b connected in series.
The source terminals of the N-MOS transistor 83 a and the P-MOS transistor 84 a are connected to the second control line 92. The drain terminals of the N-MOS transistor 83 b and the P-MOS transistor 84 b are connected to the pixel electrode 35.
The gate terminals of the N-MOS transistors 83a and 83b are connected to the data output terminal N2 of the latch circuit 370, and the gate terminals of the P-MOS transistors 84a and 84b are connected to the data input terminal N1 of the latch circuit 370.

  In the pixel 340 having the above configuration, since the first switching transistor 75 is connected between the P-MOS transistors 73a and 73b, the parasitic capacitance when the first switching transistor 75 transits from the off state to the on state. Is charged by two P-MOS transistors 73a and 73b. Similarly, the charging of the parasitic capacitance in the second switching transistor 76 is also performed by the N-MOS transistors 74a and 74b. Therefore, a potential fluctuation due to charging of the parasitic capacitance hardly affects the potential of the data input terminal N1, and the pixel circuit is less likely to generate noise.

  Further, when the image signal is input to the latch circuit 370, the first and second switching transistors 75 and 76 are in an off state, so that the P-MOS transistors 73a and 73b and the N-MOS transistors 74a and 74b are turned on. It is possible to prevent the generation of a through current when switching between ON and OFF. Thereby, the power consumption of the pixel circuit can be reduced.

  In the pixel 340 as well, as in the pixels 40 and 240 in the previous embodiment, when the driving TFT 41 is turned on and an image signal is input from the data line 68 to the latch circuit 370, the first and first pixels The two switching transistors 75 and 76 are turned off. That is, the data input terminal N1 of the latch circuit 370 is disconnected from the high potential power terminal PH and the low potential power terminal PL. Therefore, the potential of the data input terminal N1 can be reliably defined, and the input image signal can be reliably stored in the latch circuit 370.

Also in the electrophoretic display device of this embodiment, the scanning line driving circuit 61 shown in the first embodiment and the scanning line driving circuits 261 and 361 according to the first and second modifications are all employed. Can do.
If the scanning line driving circuit 61 shown in FIG. 3 or the scanning line driving circuit 261 shown in FIG. 9 is used, a circuit that supplies an inverted scanning signal to the inverted scanning line 67 and a circuit that supplies a scanning signal to the scanning line 66 are used. Therefore, it is possible to input a signal to the inverted scanning line 67 without increasing the circuit scale of the scanning line driving circuit.
Further, when the scanning line driving circuit 361 shown in FIG. 10 is used, the first and second switching transistors 75 and 76 are turned on and off at the same time. , 76 is advantageous in that the potential fluctuation of the data input terminal N1 when the parasitic capacitance charging operation occurs can be suppressed.

[Electronics]
Next, the case where the electrophoretic display device 1 of each of the above embodiments is applied to an electronic device will be described.
FIG. 18 is a front view of the wrist watch 1000. The wrist watch 1000 includes a watch case 1002 and a pair of bands 1003 connected to the watch case 1002.
A display unit 1005 including the electrophoretic display device 1 of each of the above embodiments, a second hand 1021, a minute hand 1022, and an hour hand 1023 are provided on the front surface of the watch case 1002, and an operation element is provided on the side surface of the watch case 1002. The crown 1010 and the operation buttons 1011 are provided. The crown 1010 is connected to a winding stem (not shown) provided inside the case, and is integrally provided with the winding stem so that it can be pushed and pulled in multiple stages (for example, two stages) and can be rotated. . The display unit 1005 can display a background image, a character string such as date and time, or a second hand, a minute hand, and an hour hand.

Next, FIG. 19 is a perspective view illustrating a configuration of the electronic paper 1100. An electronic paper 1100 includes the electrophoretic display device 1 of each of the above embodiments as a display area 1101. The electronic paper 1100 is flexible and includes a main body 1102 made of a rewritable sheet having the same texture and flexibility as conventional paper.
FIG. 20 is a perspective view showing the configuration of the electronic notebook 1200. An electronic notebook 1200 is obtained by bundling a plurality of electronic papers 1100 shown in FIG. The cover 1201 includes display data input means (not shown) for inputting display data sent from an external device, for example. Thereby, according to the display data, the display content can be changed or updated while the electronic paper is bundled.

According to the wristwatch 1000, the electronic paper 1100, and the electronic notebook 1200 described above, the electrophoretic display device according to the present invention is employed in the display unit, and thus the electronic device includes the display unit with excellent operation reliability. Yes. In addition, power consumption in the display portion can be reduced.
Note that the electronic devices illustrated in FIGS. 18 to 20 are examples of the electronic device according to the present invention, and do not limit the technical scope of the present invention. For example, the electrophoretic display device according to the present invention can be suitably used for a display portion of an electronic device such as a mobile phone or a portable audio device.

1 is a schematic configuration diagram of an electrophoretic display device according to a first embodiment. FIG. 3 is a diagram illustrating a pixel circuit of the electrophoretic display device according to the first embodiment. 1 is a configuration diagram of a scanning line driving circuit according to a first embodiment. FIG. 1 is a schematic cross-sectional view of an electrophoretic display device according to a first embodiment. The schematic sectional drawing of a microcapsule. Operation | movement explanatory drawing of an electrophoretic element. 4 is a timing chart in the driving method according to the first embodiment. FIG. 6 is a diagram illustrating a state of a pixel in the driving method according to the first embodiment. The block diagram of the scanning-line drive circuit which concerns on a 1st modification. The block diagram of the scanning-line drive circuit which concerns on a 2nd modification. The figure which shows the circuit simulation result of the Example which concerns on 1st Embodiment. The figure which shows the circuit simulation result of the Example which concerns on 1st Embodiment. FIG. 6 is a diagram illustrating a pixel circuit of an electrophoretic display device according to a second embodiment. The figure which shows the circuit simulation result of the Example which concerns on 2nd Embodiment. The figure which shows the circuit simulation result of the Example which concerns on 2nd Embodiment. The figure which shows the circuit simulation result of the Example which concerns on 2nd Embodiment. FIG. 10 is a diagram illustrating a pixel circuit of an electrophoretic display device according to a third embodiment. FIG. 14 illustrates an example of an electronic device. FIG. 14 illustrates an example of an electronic device. FIG. 14 illustrates an example of an electronic device. The figure which shows the conventional pixel circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Electrophoretic display apparatus, 5 Display part, 40,240,340 Pixel, 32 Electrophoretic element, 33 Adhesive layer, 35 Pixel electrode, 37 Common electrode (counter electrode), 41 Driving TFT (pixel switching element), 61 , 261, 361 scan line drive circuit, 66 scan line, 67 reverse scan line, 70, 270, 370 latch circuit (memory circuit), 70f, 370f feedback inverter, 70t, 370t transfer inverter, 75 first switching transistor, 76 Second switching transistor, 80, 380 switch circuit, 91 first control line, 92 second control line, 111, 311 level shifter, 116, 216, 217, 316 buffer, INV1, INV2 inverter, TG1, TG11 first Transmission gate, TG2, TG 22 Second transmission gate, PH high potential power terminal, PL low potential power terminal

Claims (12)

An electrophoretic display device having an electrophoretic element including electrophoretic particles between a pair of substrates and having a display unit composed of a plurality of pixels,
A pixel electrode is formed for each of the pixels on one of the substrates, and a common counter electrode is formed on the other substrate for the plurality of pixels.
For each pixel, a pixel switching element and a memory circuit connected between the pixel switching element and the pixel electrode are provided,
The memory circuit includes a transfer inverter having an input terminal connected to the pixel switching element and an output terminal connected to the pixel electrode, an input terminal connected to the output terminal of the transfer inverter, and the pixel switching element And a feedback inverter having an output terminal connected to the
A first switching transistor is connected between the feedback inverter and the high potential power supply terminal, and a second switching transistor is connected between the feedback inverter and the low potential power supply terminal,
The gate terminal of the first switching transistor is connected to a scanning line together with the gate terminal of the transistor that constitutes the pixel switching element, while the gate terminal of the second switching transistor supplies an inversion signal of the scanning line. An electrophoretic display device connected to a scanning line.   The gate area defined by a gate width and a gate length in a transistor constituting the pixel switching element is not more than twice the gate area in the transistor constituting the memory circuit. Electrophoretic display device.   The electrophoretic display device according to claim 1, wherein the first switching transistor is connected between a P-type transistor constituting the feedback inverter and the high-potential power supply terminal.   3. The electric circuit according to claim 1, wherein the feedback inverter includes a plurality of P-type transistors, and the first switching transistor is connected between the plurality of P-type transistors. Electrophoretic display device.   5. The electric circuit according to claim 1, wherein the second switching transistor is connected between an N-type transistor constituting the feedback inverter and the low-potential power supply terminal. Electrophoretic display device.   5. The feedback inverter according to claim 1, wherein the feedback inverter has a plurality of N-type transistors, and the second switching transistor is connected between the plurality of N-type transistors. The electrophoretic display device according to item. A scanning line driving circuit having a level shifter and a buffer and connected to the scanning line and the inverted scanning line;
The scanning line is connected to the level shifter via the buffer;
The electrophoretic display device according to claim 1, wherein the inversion scanning line is connected between a plurality of inverters constituting the buffer. A scanning line driving circuit having a level shifter and first and second buffers and connected to the scanning line and the inverted scanning line;
The scanning line is connected to the level shifter via the first buffer;
The electrophoretic display device according to claim 1, wherein the inverted scanning line is connected to an input terminal of the level shifter via the second buffer. A scanning line driving circuit having first and second level shifters and first and second buffers and connected to the scanning line and the inverted scanning line;
The scanning line is connected to the first level shifter via the first buffer;
The electrophoretic display device according to claim 1, wherein the inversion scanning line is connected to the second level shifter via the second buffer.   10. The switch circuit according to claim 1, wherein a switch circuit that switches connection between a plurality of control lines and the pixel electrode is provided for each of the pixels based on an output of the memory circuit. 11. The electrophoretic display device described.   First and second control lines are connected to the switch circuit, and the switch circuit selectively selects the first and second control lines based on the output of the memory circuit, and the pixel electrode. The electrophoretic display device according to claim 10, wherein the electrophoretic display device is connected to the electrophoretic display device.   An electronic apparatus comprising the electrophoretic display device according to claim 1.

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