JPH10223905A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high voltage resistant semiconductor integrated circuit capable of uniformly dividing voltage applied to a cascode-connected TFT(thin- film transistor), and eliminating dispersion of voltage resistant in the circuit. SOLUTION: M LDD(lightly doped drain) structured NMOS transistor cascode- connected N1-Nm are connected by a contact hole 111 between an output signal line 104 and the power supply line 102, and VSS giving low level to the main circuit is applied to the power supply line 102. n LDD structured PMOS transistor P1-Pn cascode-connected, in order of precedence, are connected by the contact hole 111 between the output signal line 104 and the power supply line 101, and VDD giving high level to the main circuit is applied to the power supply line 101. A gate electrode of the NMOS transistor N1-Nm and PMOS transistor P1-Pn is commonly connected together to an input signal line 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a polycrystalline silicon thin film transistor integrated circuit used for a peripheral drive circuit such as a liquid crystal display or a plasma display.

[0002]

2. Description of the Related Art Conventionally, a liquid crystal display [hereinafter referred to as an LCD]
(Liquid Crystal Display)] In order to reduce the size and cost of the device,
Technology for integrating peripheral driving circuits on the same substrate as the substrate is being developed.

This peripheral driving circuit is a thin film transistor [hereinafter referred to as a TFT (TFT) forming an active matrix array.
a thin film transistor), and a horizontal drive circuit for supplying a video signal to a data bus line. These peripheral driving circuits are usually formed by integrating polycrystalline silicon thin film transistors (hereinafter referred to as p-Si TFTs).

On the other hand, a driver IC chip manufactured by integrating p-Si TFTs on a glass substrate is used as an LCD substrate or a plasma display panel [hereinafter, referred to as a PDP (Plas).
ma Display Panel)]. Technology development for mounting on a substrate is also in progress.

[0005] A peripheral drive circuit of an LCD or PDP is usually required to be able to output a logic voltage of 5 V or a high voltage exceeding 3.3 V. For example, LC
The vertical drive circuit of D requires an output voltage of 20 to 40 V, and the vertical drive circuit of PDP requires an output voltage of about 200 V.

[0006] Therefore, development of a high withstand voltage circuit is one of the major issues in peripheral drive circuits for LCDs and PDPs. In order to increase the withstand voltage of a circuit, the withstand voltage between the source and the drain of the transistor to which the output voltage is directly applied is improved, or the voltage applied between the source and the drain of the transistor is devised. There is a need.

FIG. 11 shows a conventional CM in which the circuit has a high withstand voltage by cascade connection.
2 shows an OS inverter circuit. As shown in FIG. 11, the NMOS transistor has a configuration in which a first NMOS transistor 1101 and a second NMOS transistor 1102 are cascode-connected.

Similarly, the PMOS transistor has a first P
The MOS transistor 1103 and the second PMOS transistor 1104 are cascode-connected. The cascode-connected NMOS transistor is connected between the output signal line 104 and the second power supply line 102 by a contact hole 111. To the second power supply line 102, VSS (usually 0 V) which gives a low level of the CMOS inverter circuit is usually applied.

On the other hand, the cascode-connected PMOS transistors are connected between the output signal line 104 and the first power supply line 101 by a contact hole 111. To the first power supply line 101, VDD that gives a high level of the CMOS inverter circuit is normally applied. Further, as shown in FIG. 11, the first and second NMOS transistors 1101 and 1102 and the first and second PMOS transistors
Gate electrodes of the transistors 1103 and 1104 are commonly connected to the input signal line 103.

By adopting such a configuration,
Since a voltage applied between the output signal line 104 and the first power supply line 101 or between the output signal line 104 and the second power supply line 102 is divided by two cascode-connected transistors, individual The voltage applied between the source and the drain of the transistor can be reduced. That is, when the input signal is the low level signal VSS, the output signal is V
DD, and VDD is applied to the two cascode-connected NMOS transistors in total. However, the source-drain voltage of each NMOS transistor becomes smaller than VDD due to the voltage dividing effect.

On the other hand, when the input signal is the high-level signal VDD, the output signal becomes VSS (= 0 V), and a total of (-VDD) is applied to the two cascode-connected PMOS transistors. Due to the pressure effect, the absolute value of the source-drain voltage of each PMOS transistor becomes smaller than the absolute value of (-VDD).

As described above, the cascode connection C
In the MOS inverter circuit, the voltage between the source and the drain of each transistor can be reduced, so that the circuit withstand voltage can be substantially improved.

[0013]

However, FIG.
In the cascode connection type CMOS inverter circuit shown in (1), the ratio of the voltage applied between the source and the drain of each transistor (voltage division ratio) greatly depends on the leakage current characteristics of the transistor, so that it is difficult to design the breakdown voltage. Occurs. In particular, in the case of a p-Si TFT, a stable leak current characteristic is not always obtained, and causes a variation in circuit withstand voltage.

In a p-Si TFT, a single crystal S
Since the leak current characteristic of the p-Si TFT that is not seen in the leak current characteristic of the iMOS transistor is exhibited, the voltage division ratio does not become 1: 1 and an efficient voltage division ratio cannot be obtained.

Here, the efficient voltage dividing ratio means a voltage dividing ratio that maximizes the circuit withstand voltage, and the voltage dividing ratio is 1: 1. If the voltage division ratio is 1: 1, the source-drain voltage of the two cascode-connected transistors is half the output voltage, so that the circuit withstand voltage is doubled.

FIGS. 13 and 14 show CMs shown in FIG. 11, respectively.
FIG. 7 is a diagram illustrating an example of drain current-gate voltage characteristics of an n-channel p-SiTFT and a p-channel p-SiTFT for explaining an operating point when an OS inverter circuit is manufactured with a p-SiTFT. As shown in FIGS. 13 and 14, generally, when a reverse bias (negative voltage for an n-channel TFT, positive voltage for a p-channel TFT) is applied to a gate voltage in a p-Si TFT, the reverse bias increases and And the characteristic that the leakage current increases. This leak current is said to be a tunnel current via a trap level in the forbidden band of the depleted channel region near the drain electrode, and is peculiar to the p-Si TFT.

In the CMOS inverter circuit shown in FIG. 11, when VDD = 20V and VSS = 0V, and an input voltage VIN of 0V is input, the output voltage VOUT becomes 20.
V. As a result, a total of 20 V is applied to the two cascode-connected n-channel thin film transistors N1 and N2. Here, as shown in FIG. 11, the n-channel thin film transistors N1 and N2 are a TFT on the second power supply line 102 side and a TFT on the output signal line 104 side, respectively.
Is shown.

The operating point at this time can be known from the drain current-gate voltage characteristics of the n-channel TFT shown in FIG. That is, since the same off-state current must flow through the two cascode-connected n-channel TFTs, the drain voltage Vds and the gate voltage Vgs of each TFT that gives the same current value may be obtained.

As a result, the operating point when the input voltage VIN = 0V is as shown in FIG. That is, the gate voltage Vgs = 0 V and the drain voltage Vds = 13 V are applied to the n-channel thin film transistor N1, and the gate voltage Vgs = −13 V, V
When ds = 7 V is applied, the n-channel thin film transistors N1 and N2 have the same current value, and this point is the operating point. Therefore, when the input voltage VIN = 0V, the two cascode-connected n-channel thin film transistors N1, N1
The source-drain voltage of N2 is 13V and 7V, respectively. FIG. 12A is a diagram showing the bias state at this time by an equivalent circuit.

On the other hand, in the CMOS inverter circuit shown in FIG. 11, when VDD = 20 V and VSS = 0 V, 2
When an input voltage VIN of 0 V is input, the output voltage VOU
T becomes 0V. As a result, the two cascode-connected p-channel thin film transistors P1 and P2 have a total (−
20) V will be applied. Here, the p-channel thin film transistors P1 and P2 are, as shown in FIG.
The TFT on the first power supply line 101 side and the output signal line 10
The TFT on the fourth side is shown.

The operating point at this time can be known from the drain current-gate voltage characteristics of the p-channel TFT shown in FIG. That is, since the same off-state current must flow through the two cascode-connected p-channel TFTs, the drain voltage Vds and the gate voltage Vgs of each TFT giving the same current value may be obtained.

As a result, the operating point when the input voltage VIN = 20 V is as shown in FIG. That is, the gate voltage Vgs = 0 V and the drain voltage Vds = −11 V are applied to the p-channel thin film transistor P1, and the gate voltage Vgs = −11 to the p-channel thin film transistor P2.
When V and Vds = -9 V are applied, the p-channel thin film transistors P1 and P2 have the same current value, and this point is the operating point. Therefore, when the input voltage VIN = 20 V, the source-drain voltages of the two cascode-connected p-channel thin film transistors P1 and P2 are respectively -1.
1V and -9V. FIG. 12B is a diagram showing the bias state at this time by an equivalent circuit.

As described above, the CM shown in FIG.
When the OS inverter circuit is made of p-Si TFTs, the voltage is not evenly divided by the two cascode-connected TFTs, and the breakdown voltage cannot be efficiently increased. Further, as described above, since the leak current of the p-Si TFT is closely related to the trap level density in the forbidden band of the depleted channel region near the drain electrode, the same leak current characteristic is always obtained. Not limited, poor reproducibility.
Therefore, since the voltage division ratio of the voltages applied to the two cascode-connected TFTs is not determined, it is difficult to design the circuit withstand voltage.

Accordingly, an object of the present invention is to solve the above-mentioned problems, to uniformly divide the voltage applied to the cascode-connected TFTs, and to eliminate a variation in circuit withstand voltage. Is to provide.

[0025]

A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit manufactured by integrating a polycrystalline silicon thin film transistor on an insulating substrate, wherein gate electrodes are commonly connected and sequentially. M (m is an integer of 2 or more) n-type transistors which are cascode-connected and have a low-concentration impurity region in the drain region; At least one of n (n is an integer of 2 or more) p-type transistors having a region is provided.

Another semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit manufactured by integrating a polycrystalline silicon thin film transistor on an insulating substrate, wherein the gate electrodes are commonly connected to each other and sequentially cascode-connected. M (m is 2) having a low concentration impurity region in the drain region
(N is an integer greater than or equal to) and n (p is an integer greater than or equal to 2) p-type transistors whose gate electrodes are commonly connected to each other, are sequentially cascode-connected, and have a low-concentration impurity region in the drain region. CMOS
Circuit.

In another semiconductor integrated circuit according to the present invention, in the other semiconductor integrated circuit according to the present invention, the value of the number m of the n-type transistors is larger than the value of the number n of the p-type transistors. .

Still another semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit manufactured by integrating a polycrystalline silicon thin film transistor on an insulating substrate, wherein gate electrodes are commonly connected and sequentially cascode-connected. And m (m is an integer of 2 or more) n-type transistors having a low-concentration impurity region in the drain region, and one p-type transistor
And a CMOS circuit including a type transistor.

Still another semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit manufactured by integrating a polycrystalline silicon thin film transistor on an insulating substrate.
A CMOS circuit comprising a p-type transistor and n (n is an integer of 2 or more) p-type transistors whose gate electrodes are commonly connected to each other, are sequentially cascode-connected, and have a low-concentration impurity region in the drain region. ing.

That is, in the semiconductor integrated circuit of the present invention,
The m cascode-connected n n-type transistors having the LDD structure are connected by a contact hole between the output signal line and the second power supply line, and the n cascode-connected n-type transistors are sequentially connected.
P-type transistors having the LDD structure are connected to the output signal line and the first
, And the gate electrodes of the n-type transistor and the p-type transistor are commonly connected to the input signal line. This makes it possible to evenly divide the voltage applied to the cascode-connected TFTs and to obtain a high withstand voltage semiconductor integrated circuit with no variation in circuit withstand voltage.

[0031]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a semiconductor integrated circuit according to one embodiment of the present invention. In the figure, a CMOS inverter circuit according to an embodiment of the present invention includes m (m is an integer of 2 or more) LDD (Li
NMOS with Glyly Doped Drain structure
It is composed of transistors N1 to Nm and n (where n is an integer of 2 or more) PMOS transistors P1 to Pn having an LDD structure sequentially connected in cascode.

Here, the LDD structure is a structure in which an electric field is suppressed by providing a low-concentration drain region so that a tunnel current at a junction does not occur. This LDD structure is suitable for use as a transistor for driving a liquid crystal since the leakage current is not so affected by the drain electric field, and research and development are being actively conducted. However, with such a structure, the depletion layer expands, and therefore, attention must be paid to the current generated therein. This LDD structure is described in JP-A-4-344618.

The m cascode-connected NMOS transistors N 1 to Nm are connected between the output signal line 104 and the second power supply line 102 by a contact hole 111. The second power supply line 102 usually has a CMOS
VSS (normally 0) that gives a low level to the inverter circuit
V) is applied.

On the other hand, n cascode-connected PMOs
The S transistors P1 to Pn are connected between the output signal line 104 and the first power supply line 101 by a contact hole 111. Usually, the first power supply line 101 has C
VDD giving a high level to the MOS inverter circuit is applied.

As shown in FIG. 1, first to m-th NMOS transistors N1 to Nm and first to n-th P
The gate electrodes of the MOS transistors P1 to Pn are commonly connected to the input signal line 103. In this embodiment, the first to m-th NMOS transistors N1 to N
m and p-S as the first to n-th PMOS transistors.
It is assumed that an iTFT is used.

P-S of LDD structure with cascode connection
By employing the iTFT, m or n cascode-connected voltages applied between the output signal line 104 and the first power supply line 101 or between the output signal line 104 and the second power supply line 102 are applied. The voltage can be divided almost uniformly by the TFT.

This is because, in the p-Si TFT having the LDD structure, when the drain voltage Vds is constant, the leakage current exhibits a substantially constant characteristic in a wide range of the gate reverse bias voltage. As a result, the input signal becomes the low level signal VS.
At S, m cascode-connected n-channel p-S
VDD is applied to the iTFT in total, but the source / source of each n-channel p-SiTFT is divided by the voltage dividing effect.
The drain-to-drain voltage Vds becomes VDD / m. FIG. 2 (a)
Is a diagram showing the bias state at this time in an equivalent circuit.
In this embodiment, a resistor 201 in an LDD region is equivalently inserted on the drain electrode side of each transistor, as shown in FIG.

On the other hand, when the input signal is the high-level signal VDD, n cascode-connected p-channel p-Si
Although (-VDD) is applied to the TFT in total, the voltage between the source and drain of each p-channel p-Si TFT becomes (-VDD / n) due to the voltage dividing effect. FIG.
(B) is a diagram showing the bias state at this time in an equivalent circuit.

FIG. 3 is a diagram showing a specific example of a semiconductor integrated circuit according to one embodiment of the present invention, FIG. 4 is a diagram showing an equivalent circuit of the semiconductor integrated circuit shown in FIG. 3, and FIG. FIG. 6 is a diagram showing drain current-gate voltage characteristics of the n-channel p-Si TFT having the LDD structure shown in FIG.
Drain current of p-channel p-Si TFT with DD structure-
FIG. 4 is a diagram illustrating gate voltage characteristics.

The semiconductor integrated circuit according to one embodiment of the present invention will be described more specifically with reference to FIGS.

The semiconductor integrated circuit shown in FIG. 3 is different from the CMOS inverter circuit shown in FIG. 1 in that m = 2 and n = 2.
This is the case when That is, the CMO of this embodiment
The S inverter circuit is composed of two cascode-connected LDDs.
NMOS transistors N1 and N2 having a structure and two PMOS transistors P having an LDD structure connected in cascode.
1 and P2. Also in this embodiment, the first and second NMOS transistors 301 and 30 are also used.
2 and first and second PMOS transistors 303 and 30
4 is based on the assumption that a p-Si TFT is used.

P-S of cascode-connected LDD structure
By employing the iTFT, a voltage applied between the output signal line 104 and the first power supply line 101 or between the output signal line 104 and the second power supply line 102 is applied to the two cascode-connected TFTs. Thus, the pressure can be divided almost equally. The reason will be specifically described with reference to FIGS.

As shown in FIG. 5, the leak current characteristic of the n-channel p-Si TFT having the LDD structure is such that when the source-drain voltage Vds is constant, a substantially constant current flows with respect to the gate reverse bias voltage. FIG. 5 shows a case where VDD = 20 V and VSS = 0 V in the CMOS inverter circuit shown in FIG.
When the input voltage VIN of 0 V is input, the n-channel p-
The operating point of the SiTFT is shown. This operating point (bias point) is obtained as the drain voltage Vds and the gate voltage Vgs of each TFT that gives the same leak current value.

That is, the n-channel thin film transistor N
1, the gate voltage Vgs = 0 V and the drain voltage Vds = 1
0.1V is applied, and the gate voltages Vgs = -10.1V and Vds = are applied to the n-channel thin film transistor N2.
When 9.9 V is applied, the n-channel thin film transistors N1 and N2 have the same current value, and this point is the operating point. Therefore, when the input voltage VIN = 0V, the two cascode-connected n-channel thin film transistors N1, N1
The source-drain voltage of N2 becomes 10.1 V and 9.9 V, respectively, and is almost equally divided into two. FIG. 4A is a diagram showing a bias state at this time by an equivalent circuit.

On the other hand, assuming that VDD = 20 V and VSS = 0 V in the CMOS inverter circuit shown in FIG.
Is input, the output voltage VOUT becomes 0V. As a result, two cascode-connected p
The total (−2) is set for the channel thin film transistors P1 and P2.
0) V will be applied.

Here, the p-channel thin film transistor P
1 and P2 are, as shown in FIG.
1 shows a TFT on the first side and a TFT on the output signal line 104 side. The operating point at this time can be known from the drain current-gate voltage characteristics of the p-channel TFT shown in FIG.

That is, two cascode-connected p
Since the same off current must flow in the channel TFT, the drain voltage Vds and the gate voltage Vgs of each TFT that gives the same current value may be obtained. As a result, the operating points of the respective p-channel TFTs when the input voltage VIN = 20 V are as shown in FIG.

That is, the p-channel thin film transistor P1
The gate voltage Vgs = 0V and the drain voltage Vds = -1
0.1 V is applied, and the gate voltages Vgs = -10.1 V and Vds = − are applied to the p-channel thin film transistor P2.
When 9.9 V is applied, the p-channel thin film transistors P1 and P2 have the same current value, and this point is the operating point.

Therefore, when the input voltage VIN = 20 V, the source-drain voltages of the two cascode-connected p-channel thin-film transistors P1 and P2 are respectively -1.
0.1 V and -9.9 V, which are almost equally divided. FIG. 4B is a diagram showing a bias state at this time by an equivalent circuit.

As described above, the voltage applied between the source and the drain of each transistor can be reduced to half by employing the p-Si TFT having the LDD structure connected in two-stage cascode. As a result, the circuit withstand voltage can be doubled.

Japanese Unexamined Patent Publication No. 4-344618 discloses a thin-film transistor for driving each pixel of an active matrix type liquid crystal display, not for the purpose of improving the breakdown voltage, but for the purpose of reducing the leak current. There is disclosed a structure in which two LDD-structured TFTs each having the following structure are connected in series.

However, the structure disclosed in Japanese Patent Application Laid-Open No. 4-344618 is applied to suppress the leak current of the TFT provided in each pixel of the active matrix type liquid crystal display.
T has a structure provided on the source electrode side and the drain electrode side.

On the other hand, the semiconductor integrated circuit of the present invention is applied to increase the withstand voltage of peripheral drive circuits such as a liquid crystal display and a plasma display.
The structure is provided only on the drain electrode side of the FT. That is, in the semiconductor integrated circuit of the present invention, by forming the LDD region only on the drain electrode side of the TFT, the withstand voltage of the circuit can be increased without significantly reducing the operation speed of the drive circuit.

If the LDD regions are provided on the source electrode side and the drain electrode side of the TFT, the speed of the driving circuit is greatly reduced. In this respect, Japanese Patent Application Laid-Open No. 4-34
The structure of the liquid crystal driving transistor disclosed in Japanese Patent No. 4618 is different from the structure of the semiconductor integrated circuit of the present invention. Further, since the purpose of the semiconductor integrated circuit of the present invention is not to reduce the leak current of the p-SiTFT but to improve the breakdown voltage of the drive circuit formed by the p-SiTFT, the leakage current may be large. . The maximum voltage applied between the source and drain of each cascode-connected TFT is divided equally.

In this regard, JP-A-4-344618 discloses that the voltage applied between the source and the drain can be halved only by connecting two TFTs in series without using the LDD structure. It is noted. That is,
Japanese Patent Application Laid-Open No. 4-344618, page 2, right column, lines 1-5, states that "one of them is called a double gate structure, which is a circuit in which two transistors are connected in series. By reducing the drain electric field by half, the tunnel current is suppressed. "

However, as described in the above-mentioned prior art, the maximum voltage applied between the source and drain of each TFT cannot be halved by simply connecting two p-Si TFTs in series. In order to evenly divide the maximum voltage applied between the source and drain of each TFT, it is necessary to cascode the LDD structure TFT as in the semiconductor integrated circuit of the present invention. JP-A-4-
No. 344618 discloses nothing in this regard. Therefore, the semiconductor integrated circuit of the present invention is disclosed in
This is achieved by the functions and effects not described in JP-A-344618.

FIG. 7 is a plan view of a semiconductor integrated circuit according to another embodiment of the present invention, and FIG. 8 is a view showing the drain current-gate voltage characteristics of the n-channel p-Si TFT having the LDD structure shown in FIG. . A semiconductor integrated circuit according to another embodiment of the present invention will be described with reference to FIGS.

The semiconductor integrated circuit shown in FIG. 7 is different from the CMOS inverter circuit shown in FIG. 1 in that m = 3 and n = 2.
This is the case when That is, the CMO of this embodiment
The S inverter circuit is composed of three cascode-connected LDDs.
It comprises NMOS transistors N1, N2 and N3 having a structure and two PMOS transistors P1 and P2 having a cascode connection and having an LDD structure.

This embodiment is an example of a form used when the source-drain breakdown voltage of the p-channel TFT is higher than the source-drain breakdown voltage of the n-channel TFT. Also in the present embodiment, the first NMOS transistor 701, the second NMOS transistor 702, and the third N
It is assumed that p-Si TFTs are used for the MOS transistor 703 and the first and second PMOS transistors 704 and 705, respectively.

By employing two cascode-connected p-channel p-Si TFTs having an LDD structure, when the input voltage VIN is 20 V, the voltage applied between the output signal line 104 and the first power supply line 101 (− 20) As described above, V can be divided almost equally by two cascode-connected p-channel TFTs.

On the other hand, in this embodiment, the n-channel TFT is 3
The configuration is such that the cascode is connected to the stages. In that case, when the input voltage VIN is 0 V, a voltage of 20 V applied between the output signal line 104 and the second power supply line 102 can be divided into three equal parts by three cascode-connected n-channel TFTs. Become like The reason will be specifically described with reference to FIG.

As shown in FIG. 8, in the leak current characteristic of the n-channel p-Si TFT having the LDD structure, a substantially constant current flows with respect to the gate reverse bias voltage. FIG. 8 shows VDD = 20 V in the CMOS inverter circuit shown in FIG.
The operating point of the n-channel p-Si TFT when VSS = 0 V and an input voltage VIN of 0 V is input is shown. This operating point (bias point) is obtained as the drain voltage Vds and the gate voltage Vgs of each TFT that gives the same leak current value.

That is, the n-channel thin film transistor N
1, the gate voltage Vgs = 0V and the drain voltage Vds =
6.8 V is applied, and the n-channel thin film transistor N
2, the gate voltages Vgs = -6.8V and Vds = 6.7V
Is applied to the n-channel thin film transistor N3, and the gate voltage Vgs = -13.5V and the drain voltage Vds =
When 6.5 V is applied, the n-channel thin film transistors N1, N2, and N3 have the same current value, and this point is the operating point.

Therefore, when the input voltage VIN = 0V,
The source-drain voltages of the three cascode-connected n-channel thin-film transistors N1, N2, and N3 are 6.8 V, 6.7 V, and 6.5 V, respectively, which are almost equally divided into three.

As described above, the voltage applied between the source and the drain of each n-channel TFT is reduced to １ ／ by employing the n-channel p-Si TFT having the LDD structure connected in three-stage cascode. be able to. Generally, the breakdown voltage between the source and the drain of a p-Si TFT tends to be lower in an n-channel TFT than in a p-channel TFT. In such a case, as in this embodiment,
A higher breakdown voltage can be achieved by adopting a mode in which the number of connected n-channel TFTs is larger than the number of connected p-channel TFTs.

As described above, in the semiconductor integrated circuit of the present invention, the number of connected n-channel TFTs and the number of p-channel TFTs
Is independent of the number of connections. The number of connections is n
It may be determined in consideration of the withstand voltage of each of the channel and p-channel TFTs and the withstand voltage required for the circuit.

FIG. 9 is a plan view of a semiconductor integrated circuit according to another embodiment of the present invention. A semiconductor integrated circuit according to another embodiment of the present invention will be described with reference to FIG.

The semiconductor integrated circuit shown in FIG. 9 has two cascode-connected NMOS transistors N having an LDD structure.
1 and N2 and one PMOS transistor P1. In this embodiment, p
This is an example of a mode used when the withstand voltage of the channel TFT is sufficiently higher than the withstand voltage required for the circuit and it is not necessary to employ a means for increasing the withstand voltage such as a cascode connection or an LDD structure.

The breakdown voltage between the source and the drain of the TFT has a strong correlation with the hot carrier generated at the drain end. In this case, the breakdown voltage between the source and the drain of the n-channel TFT is p
In many cases, the breakdown voltage is smaller than the source-drain breakdown voltage of the channel TFT. The present embodiment is applied to such a case. Also in the present embodiment, the first
And the second NMOS transistors 801 and 802 and the first
PMOS transistors 803 and p-Si TFTs respectively
It is assumed that is used.

By adopting two cascode-connected n-channel p-Si TFTs having an LDD structure, when the input voltage VIN is 0 V, the voltage applied between the output signal line 104 and the second power supply line 102 is 20 V Can be divided almost equally by two cascode-connected n-channel TFTs as described above.

On the other hand, in this embodiment, since the cascode connection is not adopted for the p-channel TFT, when the input voltage VIN is 20 V, a voltage is applied between the output signal line 104 and the first power supply line 101. The voltage (−20 V) is directly applied between the source and the drain of the p-channel TFT 803. However, as described above, when the withstand voltage between the source and the drain of the p-channel TFT is higher than the withstand voltage required for the circuit, there is no problem regarding the withstand voltage of the circuit.

Conversely, when the withstand voltage between the source and the drain of the n-channel TFT is sufficiently higher than the withstand voltage required for the circuit and the withstand voltage of the p-channel TFT is lower than the withstand voltage required for the circuit, the circuit shown in FIG. In this case, the configurations of the n-channel TFT and the p-channel TFT may be reversed. That is, 1
NMOS transistors and cascode-connected n
A CMOS inverter circuit may be composed of a plurality of (n is an integer of 2 or more) LDD-structured PMOS transistors. With such a configuration, no problem occurs with respect to the circuit withstand voltage.

As described above, in the semiconductor integrated circuit according to another embodiment of the present invention, at least one of the n-channel TFT and the p-channel TFT is cascode-connected,
Further, it is characterized by having an LDD structure, and the structure of the other TFT is not limited. For example, the structure of the other TFT may be cascode-connected and have an LDD structure as in one embodiment of the present invention or another embodiment, or may have an LDD region as in another embodiment. It may be constituted by one TFT which is not provided. The other TFT may have another structure, for example, a cascode-connected structure.
It may be FT.

FIG. 10 is a plan view of a semiconductor integrated circuit according to still another embodiment of the present invention. The semiconductor integrated circuit shown in FIG.
This is an example applied to an ND circuit.

As shown in FIG. 10, the semiconductor integrated circuit according to the present embodiment includes first and second NMOS transistors 1001, 1 cascode-connected and having an LDD structure.
002 and third and fourth NMOS transistors 1003, also cascode-connected and having an LDD structure.
1004 and first and second PMOS transistors 100 also cascode-connected and having an LDD structure.
5,1006, also cascode connected and LDD
Third and fourth PMOS transistors 10 having a structure
07, 1008.

At this time, the gate electrodes of the first and second NMOS transistors N1 and N2 are connected to the first and second PMOs.
The gate electrodes of the S transistors P1 and P2 are commonly connected to a first input signal line 1009. The gate electrodes of the third and fourth NMOS transistors N3 and N4 and the gate electrodes of the third and fourth PMOS transistors P3 and P4 are commonly connected to a second input signal line 1010. Further, the drain electrode of the fourth NMOS transistor N4 and the drain electrodes of the second and fourth PMOS transistors P2 and P4 are commonly connected as an output signal line 104. Also in this embodiment, the individual transistors constituting the NAND circuit are all p-Si transistors.
It is assumed that it is a TFT.

With such a configuration, the first
The maximum voltage applied between the source and drain of each TFT is the first voltage regardless of whether the logic level of the signal input to the second input signal lines 1009 and 1010 is high or low. Of the voltage supplied to the power supply line 101 of FIG. The reason is that, as in the embodiment of the present invention, as shown in FIGS. 5 and 6, the leak current of the TFT is substantially constant with respect to the gate reverse bias voltage. As a result, the withstand voltage of the NAND circuit shown in FIG. 10 can be twice the withstand voltage between the source and drain of each TFT.

In this embodiment, the semiconductor integrated circuit of the present invention is
Although an example in which the present invention is applied to a NAND gate circuit having a MOS configuration has been described, the present invention may be applied to other logic gate circuits. For example, N
The present invention can be applied to all logic gate circuits such as an OR gate circuit and an EXNOR (exclusive NOR) gate circuit.

In addition, not a CMOS circuit but an NM in which the logic gate circuit is entirely constituted by NMOS transistors
An OS circuit may be used, or a PMOS circuit including all PMOS transistors may be used.

As described above, m n-type transistors having the LDD structure in which the gate electrodes are commonly connected to each other and sequentially connected to each other, and the n-type transistors having the LDD structure in which the gate electrodes are commonly connected to each other and sequentially connected to each other in cascode. By including at least one of the p-type transistors, the maximum voltage applied between the source and the drain of each of the cascode-connected TFTs can be equally divided. However, the circuit withstand voltage can be reliably improved. In addition, since there is no variation in circuit withstand voltage, design becomes easy and a high yield p-SiTFT high withstand voltage circuit can be provided.

[0081]

As described above, according to the present invention, in a semiconductor integrated circuit manufactured by integrating a polycrystalline silicon thin film transistor on an insulating substrate, the gate electrodes are connected together and sequentially cascode connected. In addition, m (m is an integer of 2 or more) n-type transistors each having a low-concentration impurity region in the drain region, the gate electrodes are commonly connected to each other, are sequentially cascode-connected, and have a low-concentration impurity region in the drain region. n (n
Is an integer of 2 or more), the voltage applied to the cascode-connected TFTs can be evenly divided, and the high withstand voltage without variation in circuit withstand voltage can be reduced. There is an effect that the semiconductor integrated circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit according to an embodiment of the present invention.

2A is a diagram showing an equivalent circuit of a bias state when an input signal is a low level signal VSS in the semiconductor integrated circuit shown in FIG. 1, and FIG. 2B is a diagram showing an input signal in the semiconductor integrated circuit shown in FIG. FIG. 3 is a diagram illustrating a bias state at the time of a high-level signal VDD by an equivalent circuit.

FIG. 3 is a diagram showing a specific example of a semiconductor integrated circuit according to one embodiment of the present invention.

4A is a diagram showing an equivalent circuit of a bias state when the input voltage VIN = 0V in the semiconductor integrated circuit shown in FIG. 3, and FIG. 4B is a diagram showing an input voltage VIN = 20V in the semiconductor integrated circuit shown in FIG. FIG. 6 is a diagram showing the bias state at the time of (1) by an equivalent circuit.

5 is an n-channel p-SiT having an LDD structure shown in FIG.
FIG. 9 is a diagram showing a drain current-gate voltage characteristic of the FT.

FIG. 6 shows a p-channel p-SiT having an LDD structure shown in FIG.
FIG. 9 is a diagram showing a drain current-gate voltage characteristic of the FT.

FIG. 7 is a plan view of a semiconductor integrated circuit according to another embodiment of the present invention.

8 is an n-channel p-SiT having the LDD structure shown in FIG.
FIG. 9 is a diagram showing a drain current-gate voltage characteristic of the FT.

FIG. 9 is a plan view of a semiconductor integrated circuit according to another embodiment of the present invention.

FIG. 10 is a plan view of a semiconductor integrated circuit according to still another embodiment of the present invention.

FIG. 11 is a plan view of a conventional semiconductor integrated circuit.

12A is a diagram showing an equivalent circuit of a bias state when an input signal is a low level signal VSS in the semiconductor integrated circuit shown in FIG. 11, and FIG. 12B is a diagram showing an input signal in the semiconductor integrated circuit shown in FIG. FIG. 3 is a diagram illustrating a bias state at the time of a high-level signal VDD by an equivalent circuit.

13 is a diagram showing drain current-gate voltage characteristics of the n-channel TFT shown in FIG.

14 is a diagram showing a drain current-gate voltage characteristic of the p-channel TFT shown in FIG.

[Explanation of symbols]

 101 first power supply line 102 second power supply line 103 input signal line 104 output signal line 105 first NMOS transistor 106 second NMOS transistor 107 m-th NMOS transistor 108 first PMOS transistor 109 second PMOS transistor Reference Signs List 110 n-th PMOS transistor 111 contact hole 112 LDD region 201 LDD resistor 301 first NMOS transistor 302 second NMOS transistor 303 first PMOS transistor 304 second PMOS transistor 701 first NMOS transistor 702 second NMOS Transistor 703 Third NMOS transistor 704 First PMOS transistor 705 Second PMOS transistor 901 First NMOS transistor 9 02 second NMOS transistor 903 first PMOS transistor 1001 first NMOS transistor 1002 second NMOS transistor 1003 third NMOS transistor 1004 fourth NMOS transistor 1005 first PMOS transistor 1006 second PMOS transistor 1007 3 PMOS transistor 1008 4th PMOS transistor 1009 1st input signal line 1010 2nd input signal line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H03K 17/10 H03K 17/687 F 17/687

Claims (5)

[Claims] 1. A semiconductor integrated circuit manufactured by integrating a polycrystalline silicon thin film transistor on an insulating substrate,
The gate electrodes are commonly connected to each other, and m (n is an integer of 2 or more) n-type transistors, which are sequentially cascode-connected and have a low-concentration impurity region in the drain region, are commonly connected to each other. A semiconductor integrated circuit comprising at least one of n (n is an integer of 2 or more) p-type transistors sequentially cascoded and having a low-concentration impurity region in a drain region. 2. A semiconductor integrated circuit manufactured by integrating a polycrystalline silicon thin film transistor on an insulating substrate,
The gate electrodes are commonly connected to each other, and m (n is an integer of 2 or more) n-type transistors, which are sequentially cascode-connected and have a low-concentration impurity region in the drain region, are commonly connected to each other. A semiconductor integrated circuit comprising a CMOS circuit comprising n (n is an integer of 2 or more) p-type transistors sequentially connected in cascode and having a low-concentration impurity region in a drain region. 3. The semiconductor integrated circuit according to claim 2, wherein the value of the number m of said n-type transistors is larger than the value of the number n of said p-type transistors. 4. A semiconductor integrated circuit manufactured by integrating a polycrystalline silicon thin film transistor on an insulating substrate,
A CMOS comprising m (m is an integer of 2 or more) n-type transistors having a gate electrode commonly connected to each other and sequentially cascode-connected and having a low-concentration impurity region in a drain region, and one p-type transistor A semiconductor integrated circuit including a circuit. 5. A semiconductor integrated circuit manufactured by integrating a polycrystalline silicon thin film transistor on an insulating substrate,
A CMOS comprising one n-type transistor and n (n is an integer of 2 or more) p-type transistors having a gate electrode connected in common and sequentially cascode-connected and having a low-concentration impurity region in a drain region. A semiconductor integrated circuit including a circuit.