JP2010286711A - Pixel circuit and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pixel circuit durable against a high voltage. <P>SOLUTION: The pixel circuit as one embodiment includes: a first p-type drive transistor having a first electrode and a second electrode connected to a first potential and a pixel electrode, respectively; a first n-type drive transistor having a first electrode and a second electrode connected to the above pixel electrode and a second potential, respectively; a first control transistor having a first electrode, a second electrode, and a gate electrode connected to a first data line, the gate electrode of the first p-type drive transistor, and a first scanning line, respectively; and a second control transistor having a first electrode, a second electrode, and a gate electrode connected to a second data line, the gate electrode of the first n-type drive transistor, and a second scanning line, respectively. The circuit further includes a second p-type drive transistor having a first electrode and a second electrode connected in series between the second electrode of the first p-type drive transistor and the pixel electrode, and the gate electrode of the second p-type drive transistor is connected to a third potential that is a predetermined potential between the first potential and the second potential. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit that can be used as, for example, a pixel circuit used in a display device, and an electronic apparatus.

  Polysilicon thin film transistors (TFTs) are used in circuits for display devices such as electrophoresis devices. For example, a display portion (pixel portion, active matrix portion) and a driver circuit portion arranged around the display portion are constituted by thin film transistors. This thin film transistor can be formed by a relatively low temperature process, and is an important device for reducing the cost of the apparatus.

  On the other hand, since a high voltage may be required to operate the display device, a pixel circuit used in the display device needs to have a high breakdown voltage. As one method for providing a pixel circuit having a high withstand voltage, there is a method of dispersing a load applied to each transistor included in the pixel circuit and suppressing a voltage applied to each transistor.

  For example, Patent Document 1 below discloses a circuit in which NMOS or PMOS transistors having LDD structures are cascade-connected in order to keep the voltage applied to each transistor low, and an input signal is commonly connected to these gate electrodes. ing.

Japanese Patent Laid-Open No. 10-223905

  However, the inventor of the present application has examined in detail, and even if the NMOS or PMOS transistors having the input signals connected in common to the gate electrodes are cascade-connected, the voltages applied to the transistors are not uniform, and the power supply potential or ground potential is It has been found that an excessive voltage still tends to be applied to the transistor connected most remotely, that is, the transistor directly connected to the output terminal VOUT.

  On the other hand, even if the LDD structure effective as a means for increasing the breakdown voltage is employed, the effect is small in the thin film transistor having the low-temperature polysilicon in the semiconductor layer. This is because the impurity concentration of the LDD structure cannot be set low.

  In view of the above, an object of one embodiment of the present invention is to provide a pixel circuit that is mainly used for a display device and can have a high withstand voltage.

  In order to solve such a problem, a pixel circuit according to one embodiment of the present invention includes a first p-type driving transistor in which a first electrode is connected to a first potential and a second electrode is electrically connected to the pixel electrode. The first electrode is electrically connected to the pixel electrode, the second electrode is connected to the second potential, the first n-type driving transistor, the first electrode is connected to the first data line, and the second electrode A first control transistor having an electrode connected to the gate electrode of the first p-type drive transistor, a gate electrode connected to the first scan line, a first electrode connected to the second data line, A second control transistor having two electrodes connected to a gate electrode of the first n-type drive transistor and a gate electrode connected to a second scan line, and a second control transistor of the first p-type drive transistor Between the two electrodes and the pixel electrode or before At least one of the pixel electrode and the first electrode of the first n-type drive transistor further includes a second drive transistor having a first electrode and a second electrode connected in series, and the second drive transistor A gate electrode of the driving transistor is connected to a third potential which is a predetermined potential between the first potential and the second potential.

  According to the pixel circuit having such a configuration, the second driving transistor is connected in series between at least one of the first potential and the pixel electrode, and between the second potential and the pixel electrode, whereby the two transistors are connected. It becomes the structure connected in series. With this configuration, it is possible to reduce the load voltage applied to each of the two transistors connected in series between either the first potential and the pixel electrode or between the second potential and the pixel electrode. Thus, even when transistors having the same breakdown voltage are used, a pixel circuit having a higher breakdown voltage can be configured.

  Moreover, it is possible to adopt a configuration in which only two types of transistors that need to reduce the load voltage among n-type drive transistors and p-type drive transistors are connected in series. According to this configuration, it is possible to prevent an unnecessary increase in cost due to the use of a plurality of transistors up to a type of transistor that has a sufficient withstand voltage and does not need to reduce the load voltage, and is relatively inexpensive. A pixel circuit can be configured.

  Further, the second drive transistor includes a second p-type in which a first electrode and a second electrode are connected in series between the second electrode of the first p-type drive transistor and the pixel electrode. A driving transistor is preferred.

  According to such a configuration, by connecting two p-type drive transistors in series between the first potential and the pixel electrode, it is possible to reduce the load voltage applied to each of the p-type drive transistors.

  The second driving transistor includes a second n-type in which a first electrode and a second electrode are connected in series between the pixel electrode and the first electrode of the first n-type driving transistor. A driving transistor is preferred.

  According to this configuration, by connecting two n-type drive transistors in series between the pixel electrode and the second potential, it is possible to reduce the load voltage applied to each of the n-type drive transistors.

  Further, as the second driving transistor, a second p-type in which a first electrode and a second electrode are connected in series between the second electrode of the first p-type driving transistor and the pixel electrode. A driving transistor; and a second n-type driving transistor having a first electrode and a second electrode connected in series between the pixel electrode and the first electrode of the first n-type driving transistor. It is preferable.

  According to the pixel circuit having such a configuration, two transistors are connected in series with each other between the first potential and the pixel electrode and between the pixel electrode and the second potential. As a result, it is possible to reduce the load voltage applied to each transistor in both the p-type driving transistor group and the n-type driving transistor group connected in series.

  A third p in which the first electrode and the second electrode are connected in series between the second electrode of the first p-type driving transistor and the first electrode of the second p-type driving transistor. It is preferable that a gate electrode of the third p-type drive transistor is further connected to a fourth potential that is a predetermined potential between the first potential and the third potential.

  According to such a configuration, the load voltage applied to each of the three p-type drive transistors can be reduced by connecting the three p-type drive transistors in series between the first potential and the pixel electrode.

  And a third n-type drive transistor having a first electrode and a second electrode connected in series between the pixel electrode and the first electrode of the second n-type drive transistor. Preferably, the gate electrode of the n-type driving transistor 3 is connected to a fourth potential which is a predetermined potential between the first potential and the third potential.

  According to such a configuration, the load voltage applied to each of the three n-type drive transistors can be reduced by connecting the three n-type drive transistors in series between the pixel electrode and the second potential.

  A third p in which the first electrode and the second electrode are connected in series between the second electrode of the first p-type driving transistor and the first electrode of the second p-type driving transistor. And a third n-type drive transistor having a first electrode and a second electrode connected in series between the pixel electrode and the second electrode of the first n-type drive transistor. The gate electrode of the third p-type driving transistor and the gate electrode of the third n-type driving transistor are connected to a fourth potential which is a predetermined potential between the first potential and the third potential. Preferably it is.

  According to the pixel circuit having such a configuration, three transistors are connected in series between the first potential and the pixel electrode and between the pixel electrode and the second potential. Thereby, the load voltage applied to each transistor in both the p-type drive transistor and the n-type drive transistor connected in series can be further reduced.

  Note that it is preferable to connect three or more transistors in series between at least one of the first potential and the pixel electrode and between the pixel electrode and the second potential because the output potential can be stabilized. . Furthermore, it is preferable that the transistor is further prevented from being destroyed by a surge generated between the first potential and the pixel electrode or between the pixel electrode and the second potential.

  Further, it is preferable that the first scanning line and the second scanning line are the same scanning line.

  According to such a configuration, the first and second control transistors can be controlled by one scanning line, and the control of the pixel circuit included in the pixel circuit can be simplified. In addition, the number of scanning lines can be reduced, whereby the wiring of peripheral circuits can be reduced.

  Further, a first capacitor connected between the gate electrode of the first p-type drive transistor and the first potential, and a connection between the gate electrode of the first n-type drive transistor and the second potential. It is preferable to further include a second capacitor.

  According to such a configuration, the voltage supplied to these electrodes can be stably held while no potential is supplied to the gate electrodes of the first p-type drive transistor and the first n-type drive transistor. Is possible. This can prevent malfunction of the pixel circuit.

  An electronic device according to one embodiment of the present invention includes any one of the above pixel circuits.

  According to the electronic apparatus having such a configuration, for example, it is possible to configure an electronic apparatus including a pixel circuit using a high voltage by including any of the characteristics of the pixel circuit.

FIG. 6 is a diagram illustrating a configuration example of a first pixel circuit. FIG. 6 is a waveform diagram of each part during operation of the first pixel circuit. The figure which shows the state of the 1st pixel circuit between T2 and T3. The figure which shows the state of the 1st pixel circuit between T4 to T5 and T6 to T7. The figure which shows the state of the 1st pixel circuit between T5 and T6. FIG. 10 is a diagram illustrating a configuration example of a first modification of the first pixel circuit. FIG. 10 is a diagram illustrating a configuration example of a second modification of the first pixel circuit. FIG. 10 is a diagram illustrating a configuration example of a second pixel circuit. FIG. 10 is a waveform diagram of each part during operation of the second pixel circuit. The figure which shows the state of the 2nd pixel circuit between T2 and T3. The figure which shows the state of the 2nd pixel circuit between T4 to T5 and T6 to T7. The figure which shows the state of the 2nd pixel circuit between T5 and T6. FIG. 10 is a diagram illustrating a configuration example of a third pixel circuit. FIG. 10 is a waveform diagram of each part during the operation of the third pixel circuit. FIG. 10 is a diagram illustrating a configuration example of a fourth pixel circuit. FIG. 10 is a waveform diagram of each part during the operation of the fourth pixel circuit. FIG. 10 is a diagram illustrating a configuration example of a fifth pixel circuit. FIG. 3 is a block diagram illustrating a configuration of an electro-optical device. The perspective view of the television provided with the electro-optical apparatus. The perspective view of the roll-up-type television provided with the electro-optical device. The perspective view of the mobile telephone provided with the electro-optical apparatus. The perspective view of the video camera provided with the electro-optical apparatus. The perspective view of the personal computer provided with the electro-optical apparatus.

An embodiment according to the present invention will be specifically described according to the following configuration with reference to the drawings. However, the embodiment described below is merely an example of the present invention. That is, the present invention is not limited to the configurations and operations illustrated in the following embodiments, and can be arbitrarily modified within the scope of the gist of the present invention. In the drawings, the same components are denoted by the same reference numerals.
1. Definition 2. Embodiment 1
(1) Configuration example of first pixel circuit (2) Description of operation of first pixel circuit (3) Modification example of first pixel circuit Embodiment 2
(1) Configuration example of second pixel circuit (2) Explanation of operation of second pixel circuit Embodiment 3
(1) Configuration example of third pixel circuit (2) Outline of operation of third pixel circuit Embodiment 4
(1) Configuration example of fourth pixel circuit (2) Outline of operation of fourth pixel circuit Embodiment 5
7). 7. Configuration example of electro-optical device including pixel circuit of the present invention Configuration example of electronic device including pixel circuit of the present invention

<1. Definition>
The terms used in this specification are defined as follows.
“Node”: refers to a predetermined location in a circuit. In addition, the potential at the node may be indicated using the same symbol. For example, the potential X refers to the potential of the node X.
“Potential node”: refers to a predetermined location in a circuit and refers to a location configured to be able to supply a potential. The potential at the potential node is also indicated using the same reference numeral. For example, the potential node Y refers to a node that can supply the potential Y, and the potential Y refers to a potential supplied from the potential node Y.
“Vth_n”: refers to the threshold voltage of the n-type transistor.
“Gate voltage”: refers to the potential of the gate electrode with reference to the potential of the source electrode of the transistor. That is, it refers to the voltage (potential difference) between the gate and the source in the transistor.
“Type”: refers to the type of an n-type transistor and a p-type transistor. For example, “any one type of transistor” means either an n-type transistor or a p-type transistor.
“First electrode, second electrode”: The transistor has a drain electrode, a source electrode, and a gate electrode, but the drain electrode and the source electrode may not necessarily be clearly distinguished. In this specification, a drain electrode or a source electrode of a transistor may be referred to as a “first electrode” and the other as a “second electrode”.
“First potential”: refers to a predetermined potential, which may refer to a power supply voltage supplied to a circuit.
“Second potential”: refers to a predetermined potential, and may refer to a ground potential that serves as a reference of potential in a circuit.
“Third potential”: refers to a predetermined potential, and may refer to a predetermined potential (intermediate potential) between the first potential and the second potential.
“Fourth potential”: refers to a predetermined potential, and may refer to a predetermined potential (intermediate potential) between the first potential and the third potential.

<2. Embodiment 1>
<(1) Configuration Example of First Pixel Circuit>
FIG. 1 is a diagram illustrating a configuration example of a first pixel circuit which is one embodiment of the present invention. As shown in FIG. 1, the pixel circuit according to the first embodiment is a semiconductor integrated circuit including a plurality of thin film transistors (TFTs). Hereinafter, the thin film transistor is simply referred to as a “transistor”.

  As shown in FIG. 1, the pixel circuit according to the first embodiment includes n-type drive transistors NT1 and NT2, p-type drive transistors PT1 and PT2, n-type control transistors Tr1 and Tr2, and capacitors Cp1 and Cp2. The The pixel circuit has an output potential node VOUT connected to the pixel electrode. That is, unlike the conventional pixel circuit, the pixel circuit of this embodiment has an n-type drive transistor between the output potential node VOUT and the ground potential node VSS and a p-type transistor between the potential node VDD2 and the output potential node VOUT. Two drive transistors are cascade-connected in series.

  The first embodiment has three potential nodes (potentials) of VSS, VDD1, and VDD2. These potentials have a relationship of VSS <VDD1 <VDD2, and VSS is a ground potential. In the specific description, for simplicity, VDD1 is assumed to be 10V and VDD2 is assumed to be 20V.

(N-type drive transistor NT1)
In the n-type drive transistor NT1, the drain electrode is connected to the node VN1, and the source electrode is connected to the ground potential node VSS. The gate electrode of the n-type drive transistor NT1 is connected to a node ND1 to which the capacitor Cp1 and the n-type control transistor Tr1 are connected.

(N-type drive transistor NT2)
In the n-type drive transistor NT2, the drain electrode is connected to the output potential node VOUT, and the source electrode is connected to the node VN1. The gate electrode of the n-type drive transistor NT2 is connected to the potential node VDD1.

(P-type drive transistor PT1)
In the p-type drive transistor PT1, the source electrode is connected to the potential node VDD2, and the drain electrode is connected to the node VP1. The gate electrode of the p-type drive transistor PT1 is connected to a node ND2 to which the capacitor Cp2 and the n-type control transistor Tr2 are connected.

(P-type drive transistor PT2)
The p-type drive transistor PT2 has a source electrode connected to the node VP1, and a drain electrode connected to the output potential node VOUT. The gate electrode of the p-type drive transistor PT2 is connected to the potential node VDD1.

(Condensers Cp1, Cp2)
Capacitor Cp1 is connected between node ND1 to which the gate electrode of n-type drive transistor NT1 and the source electrode of n-type control transistor Tr1 are connected, and ground potential node VSS. The capacitor Cp2 is connected between the node ND2 to which the gate electrode of the p-type drive transistor PT1 and the source electrode of the n-type control transistor Tr2 are connected, and the potential node VDD2. These capacitors Cp1 and Cp2 prevent the potential from changing and the output potential VOUT from changing while the potential is not supplied from the data driver to the pixel circuit. That is, the capacitor Cp1 holds the potential of the node ND1, and the capacitor Cp2 is provided to hold the potential of the node ND2.

(Control transistors Tr1, Tr2)
The n-type control transistor Tr1 has a source electrode connected to the node ND1, and a drain electrode connected to the data line DL1. The gate electrode of the n-type control transistor Tr1 is connected to the scanning line SL1. The n-type control transistor Tr2 has a source electrode connected to the node ND2, and a drain electrode connected to the data line DL2. The gate electrode of the n-type control transistor Tr2 is connected to the scanning line SL1.

<(2) Explanation of Operation of First Pixel Circuit>
Next, the operation of the first pixel circuit in Embodiment 1 will be described.

  FIG. 2 is a waveform diagram of each part during operation of the first pixel circuit. In FIG. 2, T1 to T7 indicate predetermined timings (time), and potentials corresponding to the dotted lines are shown on the right side of the horizontal dotted lines. Further, as shown in FIG. 2, the waveform diagram shows, in order from the top, the time variation of each signal waveform in the scanning line SL1, the data line DL1, the data line DL2, the node ND1, the node ND2, and the output potential node VOUT. Show.

  3 to 5 are diagrams showing states of the first pixel circuit between T2 and T3, between T4 and T5, between T6 and T7, and between T5 and T6, respectively. In FIG. 3 to FIG. 5, the potential of each node and signal line, and the on / off states of each transistor are shown in parentheses.

  Hereinafter, the operation of the first pixel circuit will be described in detail with reference to FIGS.

(T1-T3)
In FIG. 2, T1 to T3 show the operation when the ground potential VSS is output to the output potential node VOUT.

  First, at T1, a scanning driver (described later) changes the potential supplied to the scanning line SL1 from the ground potential VSS to 20V + Vth_n. Due to this change in potential, the gate voltages (Vgs) of the n-type control transistors Tr1 and Tr2 become higher than the threshold voltage, and the n-type control transistors Tr1 and Tr2 are turned on.

  Next, at T2, the data driver (described later) changes the potential of the data line DL1 from the ground potential VSS to 10V and the potential of the data line DL2 from 10V to 20V. Then, the potential of the node ND1 connected to the gate electrode of the n-type drive transistor NT1 becomes 10V, so that the gate voltage of the n-type drive transistor NT1 becomes higher than the threshold voltage, and the n-type drive transistor NT1 is turned on. When the n-type drive transistor NT1 is turned on, the potential of the node VN1 becomes the ground potential VSS, and the gate voltage of the n-type drive transistor NT2 is also higher than the threshold voltage. Therefore, the n-type drive transistor NT2 is also turned on. On the other hand, when the potential of the node ND2 connected to the gate electrode of the p-type drive transistor PT1 becomes 20 V, the gate voltage is higher than the threshold voltage of the p-type drive transistor PT1, and thus the p-type drive transistor NT2 remains off. . At this time, the node VP1 becomes 10V, and the gate voltage of the p-type drive transistor PT2 is higher than the threshold voltage. Therefore, the p-type drive transistor PT2 also remains off. As a result of the n-type drive transistors NT1 and NT2 being turned on and the p-type drive transistors PT1 and PT2 being turned off in this way, the potential of the output potential node VOUT becomes the ground potential VSS.

  FIG. 3 is a diagram illustrating a state of the first pixel circuit between T2 and T3. As described above, the potential VDD2 (20V) + Vth_n is supplied to the scanning line SL1, the potential VDD1 (10V) is supplied to the data line DL1, and the potential VDD2 (20V) is supplied to the data line DL2. The n-type drive transistors NT1 and NT2 are in the on state, and the p-type drive transistors PT1 and PT2 are in the off state. The node VN1 is at the ground potential VSS, the node VP1 is at the potential VDD1 (10 V), and the output potential node VOUT is at the ground potential VSS.

  Here, as shown in FIG. 3, 10 V, which is a potential difference between the potential VDD2 (20 V) and the potential VDD1 (10 V), is applied between the drain electrode and the source electrode of the p-type drive transistor PT1. . Further, 10 V which is a potential difference between the potential VDD1 (10 V) and the ground potential VSS which is the potential at the output potential node VOUT is applied between the drain electrode and the source electrode of the p-type drive transistor PT2. That is, it can be seen that the load voltage applied to each p-type drive transistor is halved compared to the case where one p-type drive transistor is arranged between the potential node VDD2 and the output potential node VOUT.

(T3-T5)
In FIG. 2, T3 to T5 indicate an operation when the n-type control transistors Tr1 and Tr2 are turned off while maintaining the state where the ground potential VSS is output to the output potential node VOUT.

  First, at T3, the scanning driver changes the potential supplied to the scanning line SL1 from 20 V + Vth_n to the ground potential VSS. Due to the fluctuation of the potential of the scanning line SL1, the n-type control transistors Tr1 and Tr2 that have been turned on until then are turned off. At this time, the potentials of the nodes ND1 and ND2 are held in the previous state by the capacitors Cp1 and Cp2, respectively, and are held at 10V and 20V, respectively. As a result, the n-type drive transistors NT1 and NT2 are kept on, and the p-type drive transistors PT1 and PT2 are kept off.

  Next, at T4, the data driver changes the potentials of the data lines DL1 and DL2 from 10 V to the ground potential VSS and from 20 V to 10 V, respectively. However, since the n-type control transistors Tr1 and Tr2 are in an off state, this potential change is not propagated to either of the nodes ND1 and ND2. That is, the n-type drive transistors NT1 and NT2 are kept on, and the p-type drive transistors PT1 and PT2 are kept off. Therefore, the potential of the output potential node VOUT is held at the ground potential VSS.

  FIG. 4 is a diagram illustrating a state of the first pixel circuit between T4 and T5. As described above, the ground potential VSS is supplied to the scanning line SL1, and the n-type control transistors Tr1 and Tr2 are off. For this reason, the n-type drive transistors NT1 and NT2 and the p-type drive transistors PT1 and PT2 all retain the previous state regardless of fluctuations in the potentials of the data lines DL1 and DL2. Therefore, the potential of the output potential node VOUT is also held at the previous potential, that is, the ground potential VSS.

(T5 to T6)
In FIG. 2, T5 to T6 show the operation when the potential VDD2 is output to the output potential node VOUT.

  First, at T5, the scan driver changes the potential supplied to the scan line SL1 from the ground potential VSS to 20V + Vth_n. The n-type control transistors Tr1 and Tr2 are turned on by the fluctuation of the potential of the scanning line SL1. Here, the data driver supplies the ground potential VSS to the data line DL1. As a result, the potential of the node ND1 changes from 10V to the ground potential VSS. Due to the change in the potential of the node ND1, the gate voltage of the n-type drive transistor NT1 changes from 10V higher than the threshold voltage to the ground potential VSS lower than the threshold voltage, and thereby the n-type drive transistor NT1 is turned off. Since the n-type drive transistor NT1 is turned off, the potential of the node VN1 changes from the ground potential VSS to 10V, and the n-type drive transistor NT2 is also turned off. On the other hand, the data driver supplies 10 V to the data line DL2. As a result, the potential of the node ND2 changes from 20V to 10V. Due to the change in potential of the node ND2, the gate voltage of the p-type drive transistor PT1 becomes lower than the threshold voltage, and the p-type drive transistor PT1 is turned on. When the p-type drive transistor PT1 is turned on, the potential of the node VP1 becomes the potential VDD2 (20V). When the potential of the node VP1 becomes 20V, the gate voltage of the p-type drive transistor PT2 becomes lower than the threshold voltage, so that the p-type drive transistor PT2 is also turned on. As a result of the p-type drive transistors PT1 and PT2 being turned on and the n-type drive transistors NT1 and NT2 being turned off, the potential of the output potential node VOUT becomes the potential VDD2 (20V).

  FIG. 5 is a diagram illustrating a state of the first pixel circuit between T5 and T6. As described above, the potential VDD2 (20 V) + Vth_n is supplied to the scanning line SL1, the ground potential VSS is supplied to the data line DL1, and the potential VDD1 (10 V) is supplied to the data line DL2. The n-type drive transistors NT1 and NT2 are in the off state, and the p-type drive transistors PT1 and PT2 are in the on state. The node VN1 becomes the potential VDD1 (10V), the node VP2 becomes the potential VDD2 (20V), and the output potential node VOUT becomes the potential VDD2 (20V).

  Here, as shown in FIG. 5, 10 V, which is a potential difference between the potential VDD1 (10 V) and the ground potential VSS, is applied between the electrodes of the n-type drive transistor NT1. Further, 10 V that is a potential difference between the potential VDD2 (20 V) that is the potential at the output potential node VOUT and the potential VDD1 (10 V) is applied between the electrodes of the n-type drive transistor NT2. That is, it can be seen that the load voltage applied to each n-type drive transistor is halved compared to the case where one n-type drive transistor is arranged between the output potential node VOUT and the ground potential VSS.

(T6-T7)
In FIG. 2, T6 to T7 show an operation when the n-type control transistors Tr1 and Tr2 are turned off while maintaining the state where the potential VDD2 (20 V) is output to the output potential node VOUT.

  First, at T6, the scan driver changes the potential supplied to the scan line SL1 from 20 V + Vth_n to the ground potential VSS. Then, the n-type control transistors Tr1 and Tr2 that have been turned on until then are turned off due to the fluctuation of the potential of the scanning line SL1. At this time, the potentials of the nodes ND1 and ND2 are held in the previous state by the capacitors Cp1 and Cp2, respectively, and are held at the ground potential VSS and 10V, respectively. Since the potentials of the nodes ND1 and ND2 are held as they were immediately before, the n-type drive transistors NT1 and NT2 are held off, and the p-type drive transistors PT1 and PT2 are held on. As a result, the potential of the output potential node VOUT is held at the potential VDD2 (20V).

  FIG. 4 is a diagram illustrating a state of the first pixel circuit between T6 and T7. FIG. 4 is common with the diagram showing the state of the first pixel circuit between T4 and T5. Both of these states are common in that the potential of the output potential node VOUT is maintained as it was immediately before and that the ground potential VSS is supplied to the scanning line SL1 in order to turn off the n-type control transistors Tr1 and Tr2. .

  As described above, the ground potential VSS is supplied to the scanning line SL1, and the n-type control transistors Tr1 and Tr2 are turned off. For this reason, the n-type drive transistors NT1 and NT2 and the p-type drive transistors PT1 and PT2 all retain the previous state regardless of fluctuations in the potentials of the data lines DL1 and DL2. Therefore, the potential of the output potential node VOUT is also held at the previous potential, that is, the potential VDD2 (20V).

  According to the configuration of the first embodiment, a plurality of transistors are connected in series between the ground potential node VSS and the output potential node VOUT and between the potential node VDD2 and the output potential node VOUT. With this configuration, each of the n-type drive transistors NT1 and NT2 and the p-type drive transistors PT1 and PT2 connected between the ground potential node VSS and the output potential node VOUT and between the potential node VDD2 and the output potential node VOUT. The load voltage applied to can be reduced. This makes it possible to configure a pixel circuit that can use a high voltage, that is, has a high breakdown voltage.

  Further, since the control transistors Tr1 and Tr2 are controlled by one scanning line, the control of the pixel circuits included in the pixel circuit is controlled as compared with the case where the control transistors Tr1 and Tr2 are controlled by independent scanning lines. It can be simplified. In addition, the wiring of peripheral circuits can be reduced.

  In addition, the pixel circuit of Embodiment 1 is configured to include capacitors Cp1 and Cp2. With this configuration, it is possible to stably hold the voltage applied to these electrodes while no voltage is applied to the gate electrodes of the p-type drive transistor PT1 and the n-type drive transistor NT1. This can prevent malfunction of the pixel circuit.

  In the first embodiment, the example in which the potential VDD1 is an intermediate potential between the ground potential VSS and the potential VDD2 has been described. However, the present invention is not necessarily limited thereto. That is, the potential VDD1 can be arbitrarily determined as long as it is a voltage between the ground potential VSS and the potential VDD2. However, it is more preferable to set the potential VDD1 to an intermediate potential between the ground potential VSS and the potential VDD2 because the voltage is applied equally to the two drive transistors connected in series.

  Further, the potentials supplied to the gate electrodes of both the n-type drive transistor NT2 and the p-type drive transistor PT2 are not necessarily the same potential. However, making the potentials supplied to the gate electrodes of both the n-type drive transistor NT2 and the p-type drive transistor PT2 the same can reduce the types of potentials to be supplied to the pixel circuit. preferable. In this case, the power supply circuit can be simplified.

<(3) Modification of First Pixel Circuit>
In the configuration of the first pixel circuit according to Embodiment 1, both the n-type drive transistor and the p-type drive transistor are connected in series, and the load voltage of both drive transistors can be reduced. However, the breakdown voltage of one of the n-type drive transistor and the p-type drive transistor may be low and the breakdown voltage of the other may be high. In this case, it is not necessary to reduce the load voltage for the drive transistor having a higher breakdown voltage, and it may be necessary to reduce the load voltage for each drive transistor for the drive transistor having a lower breakdown voltage.

  FIG. 6 is a diagram illustrating a configuration example of Modification 1 of the first pixel circuit according to the first embodiment. The breakdown voltage of the n-type drive transistor is sufficiently high, but the breakdown voltage of the p-type drive transistor is slightly low. 2 is a configuration example of a pixel circuit. Compared to the first embodiment, the only difference is that the n-type drive transistor connected between the ground potential VSS and the output potential node VOUT is only the n-type drive transistor NT1, and the other configurations are the same. Are given the same reference numerals, and the description thereof is omitted. In the case where the n-type driving transistor can withstand a potential difference between the ground potential VSS and the potential VDD2, the pixel circuit according to the first modification can be configured.

  FIG. 7 is a diagram illustrating a configuration example of Modification Example 2 of the first pixel circuit according to the first embodiment. Contrary to Modification Example 1 illustrated in FIG. 6, the p-type drive transistor has a sufficiently high breakdown voltage. This is a configuration example of a pixel circuit when the breakdown voltage of the n-type drive transistor is low. Compared to the first embodiment, the p-type drive transistor connected between the potential VDD2 and the output potential node VOUT is only the p-type drive transistor NT1, and the other configurations are the same. Are given the same reference numerals, and the description thereof is omitted. When the p-type drive transistor can withstand the potential difference between the ground potential VSS and the potential VDD2, the pixel circuit of the second modification can be configured.

  That is, according to the pixel circuit of the first modification or the second modification, a plurality of n-type drive transistors and p-type drive transistors that are required to reduce the load voltage are connected in series. As a result, it is possible to prevent an unnecessary increase in cost due to the connection of a plurality of drive transistors of a type that does not require a reduction in load voltage, and a pixel circuit can be configured at low cost.

  The type and number of drive transistors to be connected in series are determined by the characteristics of the n-type drive transistor and the p-type drive transistor. More specifically, for example, if it is desired to reduce the load voltage of the n-type drive transistor to 1/3, three n-type drive transistors may be connected in series.

  Thus, one embodiment of the present invention includes a structure in which a plurality of drive transistors are connected in series with respect to at least one of the drive transistors. Further, the embodiments described below also include a configuration in which a plurality of drive transistors are connected in series with respect to at least one of the drive transistors within a range not inconsistent with the spirit of the invention.

<3. Second Embodiment>
<(1) Configuration Example of Second Pixel Circuit>
FIG. 8 illustrates a configuration example of the second pixel circuit which is one embodiment of the present invention. As shown in FIG. 8, the configuration example of the second pixel circuit is obtained by changing a part of the configuration example of the first pixel circuit shown in FIG. That is, the second embodiment has the same configuration and functions as those of the first embodiment except for the n-type control transistor Tr1, the p-type control transistor Tr2, the scanning line SL1, and the scanning line SL2. The description will be omitted. In the following description of the second embodiment, differences from the first embodiment will be mainly described.

  Similar to the pixel circuit of the first embodiment, the pixel circuit of the second embodiment includes n-type drive transistors NT1 and NT2, p-type drive transistors PT1 and PT2, and capacitors Cp1 and Cp2. Here, unlike the pixel circuit of the first embodiment, the pixel circuit of the second embodiment includes an n-type control transistor Tr1 and a p-type control transistor Tr2. In the pixel circuit of the first embodiment, the control transistors Tr1 and Tr2 are both n-type transistors, and the potential is supplied to the control transistors Tr1 and Tr2 only by the scanning line SL1. However, in the second embodiment, Tr1 is an n-type control transistor, Tr2 is a p-type control transistor, the n-type control transistor Tr1 has a scanning line SL1, and the p-type control transistor Tr2 has a scanning line SL2. Connected to be configured.

<(2) Explanation of Operation of Second Pixel Circuit>
Next, the operation of the second pixel circuit in Embodiment 2 will be described.

  FIG. 9 is a waveform diagram of each part during the operation of the second pixel circuit. In FIG. 9, T1 to T7 indicate predetermined timings (time), and potentials corresponding to the dotted lines are shown on the right side of the horizontal dotted lines. Further, as shown in FIG. 9, the waveform diagram shows, in order from the top, signal waveforms at the scanning line SL1, the scanning line SL2, the data line DL1, the data line DL2, the node ND1, the node ND2, and the output potential node VOUT. The time change of is shown.

  10 to 12 are diagrams showing states of the second pixel circuit between T2 and T3, between T4 and T5, between T6 and T7, and between T5 and T6, respectively. 10 to 12, the potential of each node and signal line, and the on / off states of each transistor are shown in parentheses.

  Hereinafter, the operation of the second pixel circuit will be specifically described with reference to FIGS. 9 to 12.

(T1-T3)
In FIG. 9, T1 to T3 show the operation when the ground potential VSS is output to the output potential node VOUT.

  First, at T1, the scan driver changes the potential supplied to the scan line SL1 from the ground potential VSS to 20V, and the potential supplied to the scan line SL2 from 20V to the ground potential VSS. Due to this change in potential, the gate voltage of the n-type control transistor Tr1 becomes higher than the threshold voltage, and the gate voltage of the p-type control transistor Tr2 becomes lower than the threshold voltage. As a result, the n-type control transistor Tr1 and the p-type control transistor Tr2 are turned on.

  Next, at T2, the data driver changes the potential of the data line DL1 from the ground potential VSS to 10V and the potential of the data line DL2 from 10V to 20V. Then, the potential of the node ND1 connected to the gate electrode of the n-type drive transistor NT1 becomes 10V, the gate voltage of the n-type drive transistor NT1 becomes higher than the threshold voltage, and the n-type drive transistor NT1 is turned on. When the n-type drive transistor NT1 is turned on, the potential of the node VN1 becomes the ground potential VSS, and the gate voltage of the n-type drive transistor NT2 becomes higher than the threshold voltage. Therefore, the n-type drive transistor NT2 is also turned on. On the other hand, since the potential of the node ND2 connected to the gate electrode of the p-type drive transistor PT1 is 20 V and the gate voltage of the p-type drive transistor PT1 is higher than the threshold voltage, the p-type drive transistor NT2 remains off. At this time, the node VP1 becomes 10V, and the gate voltage of the p-type drive transistor PT2 is higher than the threshold voltage. Therefore, the p-type drive transistor PT2 also remains off. As a result of the n-type drive transistors NT1 and NT2 being turned on and the p-type drive transistors PT1 and PT2 being turned off in this way, the potential of the output potential node VOUT becomes the ground potential VSS.

  FIG. 10 is a diagram illustrating a state of the second pixel circuit between T2 and T3. As described above, the scan line SL1 has the potential VDD2 (20V), the scan line SL2 has the ground potential VSS, the data line DL1 has the potential VDD1 (10V), and the data line DL2 has the potential VDD2 (20V). Are supplied. The n-type drive transistors NT1 and NT2 are in the on state, and the p-type drive transistors PT1 and PT2 are in the off state. The node VN1 becomes the ground potential VSS, the node VP1 becomes the potential VDD1 (10 V), and the output potential node VOUT becomes the ground potential VSS.

(T3-T5)
In FIG. 9, T3 to T5 show the operation when the n-type control transistor Tr1 and the p-type control transistor Tr2 are turned off while maintaining the state where the ground potential VSS is output to the output potential node VOUT.

  First, at T3, the scan driver changes the potential supplied to the scan line SL1 from 20 V to the ground potential VSS and the potential supplied to the scan line SL2 from the ground potential VSS to 20 V. Due to the fluctuation in the potentials of the scanning lines SL1 and SL2, the n-type control transistor Tr1 and the p-type control transistor Tr2 that have been turned on until then are turned off. At this time, the potentials of the nodes ND1 and ND2 are held in the previous state by the capacitors Cp1 and Cp2, respectively, and are held at 10V and 20V, respectively. As a result, the n-type drive transistors NT1 and NT2 are kept on, and the p-type drive transistors PT1 and PT2 are kept off.

  Next, at T4, the data driver changes the data line DL1 from 10V to the ground potential VSS and the data line DL2 from 20V to 10V. However, since the n-type control transistor Tr1 and the p-type control transistor Tr2 are in an off state, this potential change is not propagated to either the node ND1 or ND2. That is, the n-type drive transistors NT1 and NT2 are kept on, and the p-type drive transistors PT1 and PT2 are kept off. Therefore, the potential of the output potential node VOUT is held at the ground potential VSS.

  FIG. 11 is a diagram illustrating a state of the second pixel circuit between T4 and T5. As described above, the ground potential VSS is supplied to the scanning line SL1, and the potential VDD2 (20 V) is supplied to the scanning line SL2, and the n-type control transistor Tr1 and the p-type control transistor Tr2 are in the off state. For this reason, the n-type drive transistors NT1 and NT2 and the p-type drive transistors PT1 and PT2 all retain the previous state regardless of fluctuations in the potentials of the data lines DL1 and DL2. Therefore, the potential of the output potential node VOUT is also held at the previous potential, that is, the ground potential VSS.

(T5 to T6)
In FIG. 9, T5 to T6 show the operation when the potential VDD2 is output to the output potential node VOUT.

  First, at T5, the scan driver changes the potential supplied to the scan line SL1 from the ground potential VSS to 20V and the potential supplied to the scan line SL2 from 20V to the ground potential VSS. The n-type control transistor Tr1 and the p-type control transistor Tr2 are turned on by the change in potential of the scanning lines SL1 and SL2. Here, the data driver supplies the ground potential VSS to the data line DL1. As a result, the potential of the node ND1 changes from 10V to the ground potential VSS. Due to the change in the potential of the node ND1, the gate voltage of the n-type drive transistor NT1 changes from 10V higher than the threshold voltage to the ground potential VSS lower than the threshold voltage, and thereby the n-type drive transistor NT1 is turned off. Since the n-type drive transistor NT1 is turned off, the potential of the node VN1 changes from the ground potential VSS to 10V, and the n-type drive transistor NT2 is also turned off. On the other hand, the data driver supplies 10 V to the data line DL2. Therefore, the potential of the node ND2 changes from 20V to 10V. Due to the change in potential of the node ND2, the gate voltage of the p-type drive transistor PT1 becomes lower than the threshold voltage, thereby turning on the p-type drive transistor PT1. When the p-type drive transistor PT1 is turned on, the potential of the node VP1 becomes the potential VDD2 (20V). When the potential of the node VP1 becomes 20V, the gate voltage of the p-type drive transistor PT2 becomes lower than the threshold voltage, so that the p-type drive transistor PT2 is also turned on. As a result of the p-type drive transistors PT1 and PT2 being turned on and the n-type drive transistors NT1 and NT2 being turned off, the potential of the output potential node VOUT becomes the potential VDD2 (20V).

  FIG. 12 is a diagram illustrating a state of the second pixel circuit between T5 and T6. As described above, the scanning line SL1 has the potential VDD2 (20V), the scanning line SL2 has the ground potential VSS, the data line DL1 has the ground potential VSS, and the data line DL2 has the potential VDD1 (10V). Have been supplied. The n-type drive transistors NT1 and NT2 are in the off state, and the p-type drive transistors PT1 and PT2 are in the on state. The node VN1 becomes the potential VDD1 (10V), the node VP2 becomes the potential VDD2 (20V), and the output potential node VOUT becomes the potential VDD2 (20V).

(T6-T7)
In FIG. 9, T6 to T7 show the operation when turning off the n-type control transistor Tr1 and the p-type control transistor Tr2 while outputting the potential VDD2 (20 V) to the output potential node VOUT.

  First, at T6, the scan driver changes the potential supplied to the scan line SL1 from 20V to the ground potential VSS and the potential supplied to the scan line SL2 from the ground potential VSS to 20V. Due to the fluctuation in the potentials of the scanning lines SL1 and SL2, the n-type control transistor Tr1 and the p-type control transistor Tr2 that have been turned on until then are turned off. At this time, the potentials of the nodes ND1 and ND2 are held in the previous state by the capacitors Cp1 and Cp2, respectively, and are held at the ground potential VSS and 10V, respectively. Since the potentials of the nodes ND1 and ND2 are held as they were immediately before, the n-type drive transistors NT1 and NT2 are held off, and the p-type drive transistors PT1 and PT2 are held on. As a result, the potential of the output potential node VOUT is held at the potential VDD2 (20V).

  FIG. 11 is a diagram illustrating a state of the second pixel circuit between T6 and T7. FIG. 11 is common with the diagram showing the state of the second pixel circuit between T4 and T5. In any of these states, the ground potential VSS is applied to the scanning line SL1 in order to turn off the n-type control transistor Tr1 and the p-type control transistor Tr2 in that the potential of the output potential node VOUT is maintained as it was immediately before. This is common in that the potential VDD2 (20 V) is supplied to the scanning line SL2.

  As described above, the ground potential VSS is supplied to the scanning line SL1, and the n-type control transistors Tr1 and Tr2 are turned off. For this reason, the n-type drive transistors NT1 and NT2 and the p-type drive transistors PT1 and PT2 all retain the previous state regardless of fluctuations in the potentials of the data lines DL1 and DL2. Therefore, the potential of the output potential node VOUT is also held at the previous potential, that is, the potential VDD2 (20V).

  The configuration of the second embodiment is different from the first embodiment in that a plurality of transistors are connected in series between the ground potential node VSS and the output potential node VOUT and between the potential node VDD2 and the output potential node VOUT. It is the same. However, according to the configuration of the second embodiment, the control transistors to which the gate electrode of the n-type drive transistor NT1 and the gate electrode of the p-type drive transistor PT1 are connected are separated. Then, the types of the control transistors connected to the gate electrode of the n-type drive transistor NT1 and the gate electrode of the p-type drive transistor PT1 are changed to be an n-type control transistor Tr1 and a p-type control transistor Tr2, respectively. With this configuration, in the pixel circuit of the second embodiment, it is not necessary to supply the potential VDD2 (20 V) + Vth_n supplied to the gate electrode of the n-type control transistor Tr2 in the first embodiment, and the p-type control transistor Tr2 The gate electrode is supplied with the potential VDD2 (20V) or the ground potential VSS. That is, the maximum voltage supplied to the pixel circuit can be lowered by Vth_n from the potential VDD2 (20V) + Vth_n to the potential VDD2 (20V). Therefore, the maximum voltage generated by the power supply circuit that supplies a potential to the pixel circuit can be reduced. Further, if the types of voltages to be supplied can be reduced, the power supply circuit can be simplified. The features of the second embodiment are obtained in addition to the features of the first embodiment other than those related to the scanning line.

<4. Embodiment 3>
<(1) Configuration Example of Third Pixel Circuit>
FIG. 13 is a diagram illustrating a configuration example of a third pixel circuit which is one embodiment of the present invention. As shown in FIG. 13, the configuration example of the third pixel circuit is similar to the configuration example of the first pixel circuit shown in FIG. Besides the number of p-type driving transistors, the supplied potentials are different. Therefore, in the following description of the third embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted. The description will focus on differences from the first embodiment.

  Similar to the pixel circuit of the first embodiment, the pixel circuit of the third embodiment includes n-type drive transistors NT1 and NT2, p-type drive transistors PT1 and PT2, n-type control transistors Tr1 and Tr2, and capacitors Cp1 and Cp2. Consists of. However, the pixel circuit of Embodiment 3 further includes an n-type drive transistor NT3 and a p-type drive transistor PT3. That is, in the pixel circuit of Embodiment 3, there are three n-type drive transistors between the ground potential node VSS and the output potential node VOUT, and three p-type drive transistors between the output potential node VOUT and the potential node. They are cascaded in series.

  In the third embodiment, there are four potential nodes (potentials) of VSS, VDD1, VDD2, and VDD3. Compared with the first embodiment, VDD3 is added. These potentials have a relationship of VSS <VDD1 <VDD2 <VDD3, and VSS is a ground potential. In the specific description, for simplicity, VDD1 is 10V, VDD2 is 20V, and VDD3 is 30V.

(N-type drive transistor NT1)
In the n-type drive transistor NT1, the drain electrode is connected to the node VN1, and the source electrode is connected to the ground potential node VSS. The gate electrode of the n-type drive transistor NT1 is connected to a node ND1 to which the capacitor Cp1 and the n-type control transistor Tr1 are connected.

(N-type drive transistor NT2)
N-type drive transistor NT2 has a drain electrode connected to node VN2 and a source electrode connected to node VN1. The gate electrode of the n-type drive transistor NT2 is connected to the potential node VDD1.

(N-type drive transistor NT3)
N-type drive transistor NT3 has a drain electrode connected to output potential node VOUT and a source electrode connected to node VN2. The gate electrode of the n-type drive transistor NT3 is connected to the potential node VDD2.

(P-type drive transistor PT1)
The p-type drive transistor PT1 has a source electrode connected to the potential node VDD3 and a drain electrode connected to the node VP1. The gate electrode of the p-type drive transistor PT1 is connected to a node ND2 to which the capacitor Cp2 and the n-type control transistor Tr2 are connected.

(P-type drive transistor PT2)
The p-type drive transistor PT2 has a source electrode connected to the node VP1 and a drain electrode connected to the node VP2. The gate electrode of the p-type drive transistor PT2 is connected to the potential node VDD2.

(P-type drive transistor PT3)
In the p-type drive transistor PT3, the source electrode is connected to the node VP2, and the drain electrode is connected to the output potential node VOUT. The gate electrode of the p-type drive transistor PT3 is connected to the potential node VDD1.

(Condensers Cp1, Cp2)
Capacitor Cp1 is connected between node ND1 to which the gate electrode of n-type drive transistor NT1 and the source electrode of n-type control transistor Tr1 are connected, and ground potential node VSS. Capacitor Cp2 is connected between node ND2 to which the gate electrode of p-type drive transistor PT1 and the source electrode of n-type control transistor Tr2 are connected, and potential node VDD3. These capacitors Cp1 and Cp2 prevent the potential from fluctuating and changing the output potential VOUT while the potential is not supplied from the data driver to the pixel circuit. That is, the capacitor Cp1 is provided to hold the potential of the node ND1, and the capacitor Cp2 is provided to hold the potential of the node ND2.

(Control transistors Tr1, Tr2)
The n-type control transistor Tr1 has a source electrode connected to the node ND1, and a drain electrode connected to the data line DL1. The p-type control transistor Tr2 has a source electrode connected to the node ND2 and a drain electrode connected to the data line DL2. Further, the gate electrodes of the n-type control transistors Tr1 and Tr2 are both connected to the scanning line SL1.

<(2) Outline of Operation of Third Pixel Circuit>
Next, the operation of the third pixel circuit in Embodiment 3 will be briefly described. The operation of the third pixel circuit in Embodiment 3 is basically the same as the operation of the first pixel circuit in Embodiment 1 except that the voltage is different.

  FIG. 14 is a waveform diagram of each part during the operation of the third pixel circuit. In FIG. 14, T1 to T7 indicate predetermined timings (time), and potentials corresponding to the dotted lines are shown on the right side of the horizontal dotted lines. Further, as shown in FIG. 14, the waveform diagram shows the time variation of each signal waveform in the scanning line SL1, the data line DL1, the data line DL2, the node ND1, the node ND2, and the output potential node VOUT in order from the top. Show.

  As can be seen by comparing FIG. 14 with FIG. 2, the difference is the potential of the scanning line SL1, the data line DL2, the node ND2, and the output potential node VOUT. In other words, in the third embodiment, the ground potential VSS and the potential VDD3 (30V) can be output from the output potential node VOUT, and the load voltage applied to the n-type drive transistor and the p-type drive transistor is designed to be 10V. It is a thing.

  According to the configuration of the pixel circuit in the third exemplary embodiment, three p-type drive transistors are provided between the potential node VDD3 and the output potential node VOUT, and three n-type transistors are provided between the output potential node VOUT and the ground potential node VSS. The driving transistors were all connected in series. As a result, the load voltage applied to each of the p-type drive transistor and the n-type drive transistor connected in series can be reduced.

  As described in the modification of the first pixel circuit, a plurality of n-type driving transistors and p-type driving transistors that are required to reduce the load voltage may be connected in series. it can. As a result, it is possible to prevent an unnecessary increase in cost due to the connection of a plurality of drive transistors of a type that does not require a reduction in load voltage, and a pixel circuit can be configured at low cost.

  However, connecting at least three transistors in series between the potential node VDD3 and the output potential node VOUT and at least one between the output potential node VOUT and the ground potential node VSS can stabilize the output potential. This is preferable because it becomes possible. Further, it is preferable because a risk of destruction of the transistor due to a voltage surge generated between the potential node VDD3 and the output potential node VOUT or between the output potential node VOUT and the ground potential node VSS is reduced.

  Further, since the control transistors Tr1 and Tr2 are controlled by one scanning line, the control of the pixel circuits included in the pixel circuit is controlled as compared with the case where the control transistors Tr1 and Tr2 are controlled by independent scanning lines. It can be simplified. In addition, the wiring of peripheral circuits can be reduced.

<5. Embodiment 4>
<(1) Configuration Example of Fourth Pixel Circuit>
FIG. 15 illustrates a configuration example of the fourth pixel circuit which is one embodiment of the present invention. As shown in FIG. 15, the configuration example of the fourth pixel circuit is similar to the configuration example of the third pixel circuit shown in FIG. 13 described in the third embodiment, but the type of the control transistor Tr2 is different. ing. That is, the n-type control transistor Tr2 is used in the third pixel circuit according to the third embodiment, but the p-type control transistor Tr2 is used in the fourth pixel circuit according to the fourth embodiment. In addition, it can be said that the fourth pixel circuit in Embodiment 4 is a combination of the second pixel circuit in Embodiment 2 and the operation of the third pixel circuit in Embodiment 3. Therefore, regarding the configuration of the following fourth embodiment, the same components as those of the third embodiment will be denoted by the same reference numerals, and the description thereof will be omitted. Differences from the third embodiment will be mainly described.

  Similar to the pixel circuit of the third embodiment, the pixel circuit of the fourth embodiment includes n-type drive transistors NT1, NT2, and NT3, p-type drive transistors PT1, PT2, and PT3, and capacitors Cp1 and Cp2. Is done. Here, unlike the third embodiment, the control transistor in the pixel circuit according to the fourth embodiment includes an n-type control transistor Tr1 and a p-type control transistor Tr2. The scanning lines connected to the respective control transistors are different, and the scanning line SL1 is connected to the n-type control transistor Tr1 and the scanning line SL2 is connected to the p-type control transistor Tr2.

<(2) Outline of Operation of Fourth Pixel Circuit>
Next, the operation of the fourth pixel circuit in Embodiment 4 will be briefly described. The operation of the fourth pixel circuit in the fourth embodiment is basically the same as the operation of the second pixel circuit in the second embodiment shown in FIG. 9 except that the voltage is different.

  FIG. 16 is a waveform diagram of each part during the operation of the fourth pixel circuit. In FIG. 16, T1 to T7 indicate predetermined timings (time), and potentials corresponding to the dotted lines are shown on the right side of the horizontal dotted lines. Further, as shown in FIG. 16, the waveform diagram shows the respective signal waveforms at the scanning line SL1, the scanning line SL2, the data line DL1, the data line DL2, the node ND1, the node ND2, and the output potential node VOUT in order from the top. The time change of is shown.

  As can be seen by comparing FIG. 16 with FIG. 9, the difference is the potential of the scanning line SL2, the data line DL2, the node ND2, and the output potential node VOUT. That is, in the fourth embodiment, the ground potential VSS and the potential VDD3 (30V) can be output from the output potential node VOUT, and the load voltage applied to the n-type driving transistor and the p-type driving transistor is set to 10V. It is a thing.

  According to the configuration of the fourth embodiment, the control transistors to which the gate electrode of the n-type drive transistor NT1 and the gate electrode of the p-type drive transistor PT1 are connected are separated. Then, the types of the control transistors connected to the gate electrode of the n-type drive transistor NT1 and the gate electrode of the p-type drive transistor PT1 are changed to be an n-type control transistor Tr1 and a p-type control transistor Tr2, respectively. With this configuration, in the pixel circuit of the fourth embodiment, it is not necessary to supply the potential VDD3 (30 V) + Vth_n supplied to the gate electrode of the n-type control transistor Tr2 in the third embodiment, and the p-type control transistor Tr2 The potential VDD3 (30V) or the potential VDD1 (10V) is supplied to the gate electrode. According to this, the maximum voltage supplied to the pixel circuit can be lowered by Vth_n from the potential VDD3 (30V) + Vth_n to the potential VDD3 (30V). Therefore, the maximum voltage generated by the power supply circuit that supplies a potential to the pixel circuit can be reduced. Further, if the types of voltages to be supplied can be reduced, the power supply circuit can be simplified. Further, the amplitude of the potential supplied to SL1 and SL2 can be reduced. The features of the fourth embodiment are obtained in addition to the features of the third embodiment other than those related to the scanning line.

<6. Embodiment 5>
FIG. 17 illustrates a configuration example of the fifth pixel circuit which is one embodiment of the present invention. As illustrated in FIG. 17, the configuration example of the fifth pixel circuit is similar to the configuration example of the first pixel circuit illustrated in FIG. 1 described in the first embodiment. Besides the number of p-type transistors, the supplied potentials are different. In the following description of the fifth embodiment, the same components as those of the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

  Similar to the pixel circuit of the first embodiment, the pixel circuit of the fifth embodiment includes n-type control transistors Tr1 and Tr2 and capacitors Cp1 and Cp2. However, the pixel circuit of Embodiment 5 includes four n-type drive transistors NT1, NT2, NT3, and NT4, and four p-type drive transistors PT1, PT2, PT3, and PT4. That is, in the pixel circuit of the fifth embodiment, there are four n-type drive transistors between the ground potential node VSS and the output potential node VOUT, and four p-type drive transistors between the output potential node VOUT and the potential node. They are cascaded in series.

  In the fifth embodiment, there are four potential nodes (potentials) of VSS, VDD1, VDD2, and VDD3. Compared with the first embodiment, VDD3 is added. These potentials have a relationship of VSS <VDD1 <VDD2 <VDD3, and VSS is a ground potential.

(N-type drive transistor NT1)
In the n-type drive transistor NT1, the drain electrode is connected to the node VN1, and the source electrode is connected to the ground potential node VSS. The gate electrode of the n-type drive transistor NT1 is connected to a node ND1 to which the capacitor Cp1 and the n-type control transistor Tr1 are connected.

(N-type drive transistor NT2)
N-type drive transistor NT2 has a drain electrode connected to node VN2 and a source electrode connected to node VN1. The gate electrode of the n-type drive transistor NT2 is connected to the potential node VDD1.

(N-type drive transistor NT3)
In the n-type drive transistor NT3, the drain electrode is connected to the node VN3, and the source electrode is connected to the node VN2. The gate electrode of the n-type drive transistor NT3 is connected to the potential node VDD2.

(N-type drive transistor NT4)
N-type drive transistor NT4 has a drain electrode connected to output potential node VOUT and a source electrode connected to node VN3. The gate electrode of the n-type drive transistor NT4 is connected to the potential node VDD3.

(P-type drive transistor PT1)
The p-type drive transistor PT1 has a source electrode connected to the potential node VDD3 and a drain electrode connected to the node VP1. The gate electrode of the p-type drive transistor PT1 is connected to a node ND2 to which the capacitor Cp2 and the n-type control transistor Tr2 are connected.

(P-type drive transistor PT2)
The p-type drive transistor PT2 has a source electrode connected to the node VP1 and a drain electrode connected to the node VP2. The gate electrode of the p-type drive transistor PT2 is connected to the potential node VDD2.

(P-type drive transistor PT3)
In the p-type drive transistor PT3, the source electrode is connected to the node VP2, and the drain electrode is connected to the node VP3. The gate electrode of the p-type drive transistor PT3 is connected to the potential node VDD1.

(P-type drive transistor PT4)
The p-type drive transistor PT4 has a source electrode connected to the node VP3 and a drain electrode connected to the output potential node VOUT. The gate electrode of the p-type drive transistor PT4 is connected to the ground potential node VSS.

(Condensers Cp1, Cp2)
Capacitor Cp1 is connected between node ND1 to which the gate electrode of n-type drive transistor NT1 and the source electrode of n-type control transistor Tr1 are connected, and ground potential node VSS. Capacitor Cp2 is connected between node ND2 to which the gate electrode of p-type drive transistor PT1 and the source electrode of n-type control transistor Tr2 are connected, and potential node VDD3. These capacitors Cp1 and Cp2 prevent the potential from changing and the output potential VOUT from changing while the potential is not supplied from the data driver to the pixel circuit. That is, the capacitor Cp1 is provided to hold the potential of the node ND1, and the capacitor Cp2 is provided to hold the potential of the node ND2.

(Control transistors Tr1, Tr2)
The n-type control transistor Tr1 has a source electrode connected to the node ND1, and a drain electrode connected to the data line DL1. The p-type control transistor Tr2 has a source electrode connected to the node ND2 and a drain electrode connected to the data line DL2. Further, the gate electrodes of the n-type control transistors Tr1 and Tr2 are both connected to the scanning line SL1.

  According to the configuration of the fifth pixel circuit in the fifth embodiment, the potential output from the output potential node VOUT can be stabilized by providing the p-type drive transistor PT4 and the n-type drive transistor NT4. It becomes.

<7. Configuration Example of Electro-Optical Device Including Pixel Circuit of Present Invention>
FIG. 18 is a block diagram illustrating a configuration of an electro-optical device, which is an application example of the pixel circuit of the above embodiment. The apparatus includes a display unit 10 and a peripheral circuit unit 11. The peripheral circuit unit 11 is provided with, for example, a scanning driver 13, a data driver 14, and a control circuit 12 for controlling them.

  The scan driver 13 is configured to supply a scan line signal to the scan lines of the pixel circuits included in the display unit 10 and to change the potential of the scan lines. The data driver 14 is configured to supply a data line signal to a data line of a pixel circuit included in the display unit 10 and to change the potential of the data line signal. The control circuit 12 is configured to determine a signal to be supplied from the scan driver 13 and the data driver 14 to the display unit 10 and to instruct the scan driver 13 and the data driver 14.

  As the pixel circuit included in the display unit 10, the pixel circuit described in the above embodiment is used. As a result, the withstand voltage of the entire pixel circuit is increased, and as a result, the withstand voltage of the display unit 10 can be increased.

  Examples of electro-optical devices include electrophoretic devices, organic EL devices, display devices such as liquid crystal devices, and the like.

<8. Configuration Example of Electronic Device Including Pixel Circuit of Present Invention>
Next, specific examples of the electronic apparatus including the electro-optical device 100 will be described with reference to FIGS. FIG. 19 shows an application example to a television. The television 550 includes the electro-optical device 100. FIG. 20 shows an application example to a roll-up type television. The roll-up television 560 includes the electro-optical device 100. FIG. 21 shows an application example to a mobile phone. The cellular phone 530 includes an antenna unit 531, an audio output unit 532, an audio input unit 533, an operation unit 534, and the electro-optical device 100. FIG. 22 shows an application example to a video camera. The video camera 540 includes an image receiving unit 541, an operation unit 542, an audio input unit 543, and the electro-optical device 100. FIG. 23 shows a personal computer. The personal computer includes a main body 102 having a keyboard 101 and a display unit 103 using the electro-optical device.

  The electronic device is not limited to the above example, and can be applied to various electronic devices having a display function, for example. In addition to the above, a fax machine with a display function, a finder for a digital camera, a portable TV, an electronic notebook, an electronic bulletin board, a display for advertising, and the like are also included.

  According to the electronic apparatus having such a configuration, for example, it is possible to configure an electronic apparatus including a pixel circuit using a high voltage by including any of the characteristics of the pixel circuit.

DESCRIPTION OF SYMBOLS 10 ... Display part, 11 ... Peripheral circuit part, 12 ... Control circuit, 13 ... Scan driver, 14 ... Data driver, 100 ... Electro-optical device, 101 ... Keyboard, 102 ... Main-body part, 103 ... Display unit, 530 ... Mobile phone 531 ... Antenna unit, 532 ... Audio output unit, 533 ... Audio input unit, 534 ... Operation unit, 540 ... Video camera, 541 ... Image receiving unit, 542 ... Operation unit, 543 ... Audio input unit, 550 ... Television, 560 ... Roll-up television, Cp1, Cp2 ... Capacitor, DL1, DL2 ... Data line, ND1, ND2, VN1, VN2, VN3, VP1, VP2, VP3 ... Node, NT1, NT2, NT3, NT4 ... n-type drive transistor , PT1, PT2, PT3, PT4, p-type drive transistors, SL1, SL2, ... scanning lines, Tr1 Tr2 ... control transistor, VDD1 · VDD2 · VDD3 ... potential and potential node, VOUT ... output potential and output potential node, VSS ... ground potential, ground potential node

Claims (10)

A first p-type drive transistor having a first electrode connected to the first potential and a second electrode electrically connected to the pixel electrode;
A first n-type drive transistor having a first electrode electrically connected to the pixel electrode and a second electrode connected to a second potential;
A first control transistor having a first electrode connected to the first data line, a second electrode connected to the gate electrode of the first p-type drive transistor, and a gate electrode connected to the first scan line; ,
A second control transistor having a first electrode connected to a second data line, a second electrode connected to a gate electrode of the first n-type drive transistor, and a gate electrode connected to a second scan line; With
In series with at least one of the second electrode of the first p-type driving transistor and the pixel electrode, or between the pixel electrode and the first electrode of the first n-type driving transistor, A second driving transistor connected to the first electrode and the second electrode;
The pixel circuit, wherein a gate electrode of the second driving transistor is connected to a third potential which is a predetermined potential between the first potential and the second potential. The second drive transistor is a second p-type drive transistor in which a first electrode and a second electrode are connected in series between a second electrode of the first p-type drive transistor and the pixel electrode. Is,
The pixel circuit according to claim 1. The second drive transistor includes a second n-type drive transistor in which a first electrode and a second electrode are connected in series between the pixel electrode and the first electrode of the first n-type drive transistor. Is,
The pixel circuit according to claim 1. As the second driving transistor,
A second p-type drive transistor having a first electrode and a second electrode connected in series between the second electrode of the first p-type drive transistor and the pixel electrode;
A second n-type drive transistor having a first electrode and a second electrode connected in series between the pixel electrode and the first electrode of the first n-type drive transistor;
The pixel circuit according to claim 1. A third p-type drive in which the first electrode and the second electrode are connected in series between the second electrode of the first p-type drive transistor and the first electrode of the second p-type drive transistor. A transistor,
5. The gate electrode of the third p-type drive transistor is connected to a fourth potential that is a predetermined potential between the first potential and the third potential. 6. Pixel circuit. A third n-type driving transistor having a first electrode and a second electrode connected in series between the pixel electrode and the first electrode of the second n-type driving transistor;
5. The gate electrode of the third n-type driving transistor is connected to a fourth potential that is a predetermined potential between the first potential and the third potential. 6. Pixel circuit. A third p-type drive in which the first electrode and the second electrode are connected in series between the second electrode of the first p-type drive transistor and the first electrode of the second p-type drive transistor. With transistors,
A third n-type drive transistor having a first electrode and a second electrode connected in series between the pixel electrode and the second electrode of the first n-type drive transistor;
The gate electrode of the third p-type driving transistor and the gate electrode of the third n-type driving transistor are connected to a fourth potential that is a predetermined potential between the first potential and the third potential. The pixel circuit according to claim 4. The pixel circuit according to claim 1, wherein the first scanning line and the second scanning line are the same scanning line. A first capacitor connected between a gate electrode of the first p-type drive transistor and a first potential;
9. The pixel circuit according to claim 1, further comprising: a second capacitor connected between a gate electrode of the first n-type driving transistor and a second potential. 10. .   An electronic apparatus comprising the pixel circuit according to claim 1.

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