JP2009094927A - Buffer, level shifting circuit, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability of a buffer by suppressing deterioration and malfunction of a transistor in the buffer comprising transistors of the same conductivity type and using bootstrap effect. <P>SOLUTION: An output signal/02 from a level shifter is supplied to an input terminal in. The output signal/02 is having flotation in Low level and the potential of the Low level is VEE' a little higher than VEE. As a transistor Tr312 which is supplied at its gate with the output signal/02 having the Low-level flotation like this and also supplied at its drain with a potential raised almost to twice as high as a high-potential power source VDD through the bootstrap effect, a TFT having a body structure is employed and its body B is connected to the source S. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a buffer having a one-channel configuration, that is, a transistor having the same conductivity type and using a bootstrap effect, a level shift circuit using the same, and a display device.

For example, as described in Patent Document 1, it is known to configure a level shifter by connecting two stages of single-channel inverters using the bootstrap effect. Such a level shifter uses a plurality of inverters that use a voltage higher than the amplitude level on the Hi side of the input signal as a power source, thereby generating an output signal that has a voltage having a higher amplitude level on the Hi side than the input signal. At this time, the amplitude drop on the Hi side of the output signal can be prevented by the bootstrap effect.
JP 2002-328643 A (refer to FIG. 6 etc.)

  Patent Document 1 does not mention a negative-direction level shifter that shifts the amplitude of an input signal in the negative direction. However, it is assumed that a level shift in the negative direction is performed using a bootstrap inverter configured with an N-channel transistor. When the circuit is configured, for example, a circuit 400 as shown in FIG. That is, the two-input single-channel bootstrap type level shifter 300 and the two-input single-channel bootstrap type buffers 240a and 240b are combined. FIG. 17B shows a circuit configuration of the level shifter 300, and FIG. 17C shows a circuit configuration of the buffer 240a. Note that since the circuit configurations of the buffer 240a and the buffer 240b are the same, only the circuit configuration of the buffer 240a is shown in FIG.

  In FIGS. 17B and 17C, VDD is a positive power supply (about 8V), and VEE is a negative power supply (−0.5VDD = about −4V). The input signal 01 supplied to the level shifter 300 has an amplitude between VDD and GND (0 V). That is, the input signal 01 has a Hi level of VDD and a Low level of GND. Further, an inverted version of the input signal 01 becomes an input signal / 01. Similarly, for the output from the level shifter 300, the output signal 02 is obtained by inverting the output signal 02. Further, all the transistors Tr101 to 106 and Tr201 to 204 constituting the level shifter 300 and the buffers 240a and 240b are N-channel thin film transistors (TFTs).

  In the level shifter 300 shown in FIG. 17B, when the input signal 01 supplied to the input terminal “in” becomes Hi level, VDD−Vth that is lowered from VDD by the threshold voltage Vth of the transistor Tr101 is applied to the gate of the transistor Tr102. Supplied. As a result, the transistor Tr102 is turned on. At this time, the voltage between the gate and the source of the transistor Tr102 is (VDD−−) from GND−VEE held in the capacitor C107 before the input signal 01 is switched to the Hi level, that is, when the input signal 01 is at the Low level. Vth) -VEE. Further, the transistor Tr103 is turned off when the output signal 02 from the output terminal out becomes VDD-2 * Vth and the transistor Tr106 is turned on, so that the gate potential becomes VEE.

  Note that since the charge of the capacitor 107 is held even when the transistor Tr102 is turned on, the potential of the gate of the transistor Tr102 is increased to (VDD−Vth) + VDD and the transistor Tr102 is sufficiently turned on. In other words, the transistor Tr102 has a gate potential of 2 * VDD−Vth due to the bootstrap effect of the capacitor 107, and the output signal 02 from the output terminal out becomes VDD. Note that the transistor Tr101 is turned off when the potential of the gate of the transistor Tr102 becomes higher than VDD.

  On the other hand, the transistor Tr106 is turned on in response to the output signal 02 becoming VDD. At this time, the low level (GND) of the input signal / 01 is supplied to the input terminal / in. In this case, the gate-source voltage becomes GND-VEE (about 4 V), which is slightly higher than the threshold voltage, so it is weakly turned on. In this case, the output signal / 02 from the output terminal / out becomes a potential determined by the on-resistance ratio of the transistor Tr105 and the transistor Tr106, and the Low level of the output signal / 02 becomes VEE 'slightly higher than VEE. That is, a low level float occurs in the output signal / 02.

  This is a problem common to the output signal 02 from the output terminal out. That is, conversely, when the output signal / 02 becomes VDD, the transistor Tr103 is turned on. At this time, the Low level (GND) of the input signal 01 is supplied to the input terminal in. Therefore, the transistor Tr102 is turned on weakly because the gate-source voltage is GND-VEE (about 4 V), which is slightly higher than the threshold voltage. Therefore, the output signal 02 from the output terminal out becomes a potential determined by the ratio of the on-resistance of the transistor Tr102 and the transistor Tr103, and the Low level of the output signal 02 is also slightly higher than VEE '.

  FIG. 18 is a waveform diagram of input / output signals in the negative direction level shift circuit 400. From this figure, it can also be confirmed that low level floating occurs in the output signals 02 and / 02 of the level shifter 300. When the low level floating occurs in the output signals 02 and 02 from the level shifter 300 as described above, the transistors Tr201 and Tr201 that receive the supply of the output signals 02 and / 02 among the transistors Tr201 to 204 provided in the buffers 240a and 240b in the subsequent stage. In 202 and 204, performance degradation and malfunction may occur due to hot carriers.

  That is, in the circuit shown in FIG. 17C, VEE ′ that is slightly higher than VEE is supplied to the gates of the transistors Tr201, 202, and 204 as the low level of the output signals 02 and 02. Therefore, in the case where TFTs having high driving capability and low threshold voltage are used as the transistors Tr201, 202, 204, when the low level (VEE ′) of the output signals 02, 02 is supplied, the transistors Tr201, 202, 204 The gate-source voltage becomes VEE′−VEE, which may take a value near the threshold voltage. In such a case, the gate voltage near the threshold voltage is constantly applied to the transistors Tr201, 202, and 204 while the low level of the output signals 02 and 02 is supplied. For this reason, performance degradation and malfunction due to hot carriers occur.

  Further, in addition to the problem due to hot carriers, the transistor Tr202 is supplied with a potential increased to about twice the VDD due to the bootstrap effect, so that the degree of deterioration further increases. If the transistor Tr202 deteriorates, this deterioration causes the output signals OA and OB of the buffers 240a and 240b to float to a low level, and causes the same deterioration to the TFTs provided in the circuits in the subsequent stages. End up.

  The present invention has been made in view of such circumstances, and an object thereof is to suppress deterioration and malfunction of a transistor included in a buffer having a one-channel configuration using a bootstrap effect and to improve the reliability of the buffer. It is.

  In order to solve the above-described problem, a buffer according to the present invention is a buffer that generates an output signal obtained by inverting the logic level of an input signal, and a first potential is supplied to a drain, and a gate is connected to the drain. A first transistor, a gate connected to the input signal, a drain connected to the source of the first transistor, a source connected to the second potential, and a gate connected to the source of the first transistor. A third transistor whose drain is supplied with the first potential; a first capacitor provided between the source of the third transistor and the gate of the third transistor; and the gate receiving the input signal. , A drain connected to the source of the third transistor, and a fourth transistor to which the second potential is supplied to the source. The output signal is extracted from the source of the third transistor, the first to fourth transistors have the same conductivity type, the second transistor has a body, and connects the body and the source of the second transistor. It is characterized by that.

  According to the present invention, since the body and source of the second transistor are connected, for example, when the conductivity type of the first to fourth transistors is N-type, in the second transistor, the low level of the input signal at the gate. Is supplied, and the gate-source voltage becomes the low potential-second potential (low-potential power supply) of the input signal, and even if this becomes a value near the threshold voltage, While deterioration and malfunction can be suppressed, when the conductivity type of the first to fourth transistors is P-type, the Hi level potential (high potential) of the input signal is supplied to the gate in the second transistor, and the gate Even if the source-to-source voltage becomes the high potential-second potential (high potential power supply) of the input signal and this becomes a value near the threshold voltage, the deterioration of the second transistor due to hot carriers, It is possible to suppress the operation. Therefore, the reliability of the buffer can be improved.

  In the above-described buffer, the fourth transistor may include a body, and the body of the fourth transistor may be connected to the source of the fourth transistor. With this configuration, it is possible to suppress deterioration and malfunction due to hot carriers in the fourth transistor as well.

  According to another aspect of the present invention, there is provided a buffer for generating an output signal obtained by inverting the logic level of an input signal, wherein a first potential is supplied to a drain and a gate is connected to the drain; The input signal is supplied, the drain is connected to the source of the first transistor, the source is supplied with the second potential, the gate is connected to the source of the first transistor, and the drain is connected to the first transistor. A third transistor to which one potential is supplied; a first capacitor provided between a source of the third transistor and a gate of the third transistor; the input signal being supplied to a gate; and a drain being the third transistor A fourth transistor connected to the source of the transistor and supplied with the second potential to the source. The first to fourth transistors have the same conductivity type, and the second transistor includes a back gate in addition to the gate, and the back gate, the source of the second transistor, Are connected.

  According to the present invention, since the back gate and the source of the second transistor are connected, for example, when the conductivity type of the first to fourth transistors is N-type, in the second transistor, the low level of the input signal is applied to the gate. Level potential (low potential) is supplied, and the gate-source voltage becomes the low potential-second potential (low potential power supply) of the input signal, and even if this becomes a value near the threshold voltage, the second transistor due to hot carriers. On the other hand, when the conductivity type of the first to fourth transistors is P type, the Hi level potential (high potential) of the input signal is supplied to the gate in the second transistor, Even if the gate-source voltage becomes the high potential-second potential (high potential power supply) of the input signal, and this becomes a value in the vicinity of the threshold voltage, It is possible to suppress the reduction or malfunction. Therefore, the reliability of the buffer can be improved.

  In the above-described buffer, the fourth transistor may include a back gate in addition to the gate, and the back gate of the fourth transistor may be connected to the source of the fourth transistor. With this configuration, it is possible to suppress deterioration and malfunction due to hot carriers in the fourth transistor as well.

  The buffer according to the present invention is a buffer for generating an output signal obtained by inverting the logic level of an input signal having amplitude levels of a high potential and a low potential, wherein a first potential is supplied to a drain, and a gate is A first transistor connected to a drain; a gate supplied with the input signal; a drain connected to a source of the first transistor; a source supplied with a second potential; and a gate connected to the first transistor A third transistor connected to a source of the transistor and supplied with the first potential to a drain; a first capacitor provided between a source of the third transistor and a gate of the third transistor; A fourth transistor in which an input signal is supplied, a drain is connected to a source of the third transistor, and the second potential is supplied to the source; The output signal is extracted from the source of the third transistor, the first to fourth transistors have the same conductivity type, the second transistor includes a back gate in addition to the gate, and the back transistor When the conductivity type is N type, the gate has a voltage value obtained by subtracting the second potential from the low potential during the period when the amplitude level of the input signal is the low potential. In order to deviate from the threshold voltage, a potential for increasing the threshold voltage is supplied. On the other hand, when the conductivity type is P type, the threshold voltage of the second transistor is applied during the period in which the amplitude level of the input signal is the high potential. Is shifted from a voltage value obtained by subtracting the second potential from the high potential, a potential for lowering the threshold voltage is supplied.

  According to the present invention, the potential supplied to the back gate of the second transistor is controlled so that the threshold voltage of the second transistor in the off state is input when the conductivity type of the first to fourth transistors is N type. While the voltage value obtained by subtracting the second potential (low potential power supply) from the low potential of the signal can be made larger, when the conductivity type of the first to fourth transistors is P type, the second potential is increased from the high potential of the input signal. The potential (high potential power supply) can be made smaller than the reduced voltage value. Therefore, when the conductivity type of the first to fourth transistors is N-type, the low potential of the input signal is supplied to the gate in the second transistor, and the gate-source voltage is the low potential-second potential (second potential) of the input signal ( Even if it is a low-potential power supply), this does not become a value near the threshold voltage, and when the conductivity type of the first to fourth transistors is P-type, the second transistor has a high potential of the input signal at the gate. Even when the gate-source voltage becomes the high potential-second potential (high potential power supply) of the input signal, this does not become a value near the threshold voltage. Therefore, the deterioration and malfunction of the second transistor due to hot carriers can be suppressed, and the occurrence of leakage in the second transistor can be prevented. Therefore, the reliability of the buffer can be improved.

  In the above-described buffer, the back gate and the gate of the second transistor may be connected. With this configuration, it is only necessary to connect the back gate and gate of the second transistor, so that the circuit configuration of the buffer can be simplified.

  In the above-described buffer, the fourth transistor includes a back gate in addition to the gate. When the conductivity type is N type, the amplitude level of the input signal is included in the back gate of the fourth transistor. In order to shift the threshold voltage of the fourth transistor from the voltage value obtained by subtracting the second potential from the low potential in the period of the low potential, a potential for increasing the threshold voltage is supplied. Is P-type, the threshold voltage of the fourth transistor is shifted from the voltage value obtained by subtracting the second potential from the high potential in a period in which the amplitude level of the input signal is the high potential. It is also possible to use a configuration in which a potential for reducing the voltage is supplied. With this configuration, it is possible to suppress degradation and malfunction due to hot carriers in the fourth transistor, and it is also possible to prevent occurrence of leakage in the fourth transistor. In this case, the back gate of the fourth transistor and the gate of the fourth transistor may be connected. With this configuration, the buffer circuit configuration can be simplified.

  In the above-described buffer, the first power supply terminal to which the first potential is supplied, the second power supply terminal to which the second potential is supplied, the gate of the third transistor, the first power supply terminal, or the The structure provided with the 2nd capacitive element provided between 2nd power supply terminals may be sufficient. With this configuration, the potential supplied to the drain of the second transistor can be lowered within a range in which the bootstrap effect can be achieved by capacitive division by the first capacitive element and the second capacitive element. Can be reduced.

  In the above-described buffer, the first transistor is supplied with the first potential at the drain, and the gate is connected to the drain. Instead, the first transistor is supplied with the first potential, and the input signal is supplied to the gate. A configuration may be employed in which an inverted input signal obtained by inverting the logic level is supplied. With this configuration, for example, the present invention can be applied to a 2-input 1-output type buffer as shown in FIG.

  In the above-described buffer, all the transistors constituting the buffer may be thin film transistors.

  In addition, the level shift circuit according to the present invention is configured such that the difference between the amplitude level on the third potential side and the reference potential is different from the first input signal having the amplitude level between the reference potential and the third potential. A level shifter that generates a first output signal having a fourth potential that is higher than the third potential, and any one of the above-described buffers that is connected to the subsequent stage of the level shifter, and all that constitute the level shifter and the buffer The transistors have the same conductivity type, and the first output signal is supplied as the input signal of the buffer. According to the present invention, the reliability of the level shift circuit can be improved.

  The display device according to the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixel circuits provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines. A scanning line driving circuit for supplying a scanning signal to each of the plurality of scanning lines, and a data line driving circuit for supplying a data signal to each of the plurality of data lines, The level shift circuit described above is used for the output stage of the drive circuit. According to the present invention, the reliability of the display device can be improved.

<First Embodiment>
FIG. 1 is a block diagram showing an overall configuration of a negative direction level shift circuit 401 according to the first embodiment. As shown in the figure, the negative direction level shift circuit 401 is configured by connecting a buffer 241 to the level shifter 300. The negative direction level shift circuit 401 shifts the signal level of the input signals 01 and / 01 having an amplitude of VDD-GND in the negative direction, and generates an output signal 03 having an amplitude of VDD-VEE. The magnitude relationship of each voltage is VDD (about 8 V)> GND (0 V)> VEE (about −4 V). Further, all the transistors constituting the level shifter 300 and the buffer 241 are N-channel TFTs.

  In the figure, the same reference numerals are assigned to circuits common to the negative direction level shift circuit 400 shown in FIG. That is, in the negative direction level shift circuit 401 according to the present embodiment, only the buffer 241 is different from the negative direction level shift circuit 400 shown in FIG. The level shifter 300 is the same as the negative direction level shift circuit 400, and its circuit configuration is as shown in FIG.

  As shown in FIG. 1, the level shifter 300 includes a first input terminal in to which an input signal 01 is supplied, a second input terminal / in to which an input signal / 01 obtained by inverting the input signal 01 is supplied, and an input In addition to the first output terminal out that outputs the output signal 02 in phase with the signal 01 and the second output terminal / out that outputs the output signal 02 in phase with the input signal / 01, the first output terminal out is supplied with the high potential power VDD. 1 power supply terminal and a second power supply terminal to which the low potential power supply VEE is supplied. The buffer 241 includes an input terminal in connected to the second output terminal / out of the level shifter 300, an output terminal out for outputting the output signal 03, a first power supply terminal to which the high potential power supply VDD is supplied, And a second power supply terminal to which the low potential power supply VEE is supplied.

FIG. 2 is a circuit diagram showing a configuration of the buffer 241 according to the first embodiment.
The buffer 241 according to the present embodiment is an inverter that generates an output signal 03 obtained by inverting the logic level using the output signal 02 from the level shifter 300 as an input signal. Further, the buffer 241 according to the present embodiment is a one-input one-output type buffer, unlike the buffer 240a shown in FIG. This is different from the buffer 240a shown in FIG. 17C in that the transistor Tr201 is diode-connected. In addition, the buffer 241 according to the present embodiment is such that the transistor Tr202 shown in FIG. 17C is replaced with an N-channel transistor Tr312 (TFT) having a body structure, and the body B is connected to the source S. This is different from the buffer 240a shown in FIG. A structure of the transistor Tr312 is illustrated in FIG.

  As shown in FIG. 3, the transistor Tr312 has a semiconductor layer 12 (for example, a polysilicon film body) formed on the surface of an insulating substrate. A gate electrode 13 (gate G in FIG. 2) is formed so as to face the semiconductor layer 12 with a gate insulating film (not shown) covering the semiconductor layer 12 interposed therebetween. A source region 12S, a drain region 12D, and a channel contact region A are formed in the semiconductor layer 12 after the gate electrode 13 is formed. The source region 12S and the drain region 12D are regions into which N-type impurities are introduced. On the other hand, the channel contact region A is a region into which a P-type impurity having a conductivity type opposite to that of the channel of the transistor Tr312 is introduced.

  An interlayer insulating layer (not shown) is formed so as to cover the semiconductor layer 12 and the gate electrode 13, and a plurality of through holes H1, H2, and H3 are formed in the interlayer insulating layer. A source electrode 14 (source S in FIG. 2) is connected to the source region 12S of the semiconductor layer 12 through a through hole H1, and a drain electrode 15 (drain in FIG. 2 is connected to the drain region 12D through a through hole H2. D) is connected. A body electrode (body B in FIG. 2) 16 is connected to the channel contact region A of the semiconductor layer 12 through the through hole H3.

Next, the operation of the buffer 241 shown in FIG. 2 will be described.
The output signal 02 of the level shifter 300 is supplied to the input terminal in of the buffer 241. When the output signal / 02 supplied to the input terminal in becomes Hi level (VDD), the two transistors Tr312 and 204 on the pull-down side are both turned on. Further, since the transistor Tr201 is diode-connected, the potential of the node α is a value determined by the ratio of the on-resistance of the transistor Tr201 and the transistor Tr312. For example, if the on-resistance of the transistor Tr201 is extremely smaller than the on-resistance of the transistor Tr312, the potential of the node α is approximately VDD−Vth (the threshold voltage of the transistor Tr201), and the transistor Tr203 is turned on.

  Therefore, the potential of the output signal 03 output from the output terminal out becomes a value determined by the ratio of the on-resistance of the transistor Tr203 and the transistor Tr204. However, the driving capability of the transistor Tr204 is set higher than that of the transistor Tr203, and the on-resistance of the transistor Tr204 is extremely smaller than the on-resistance of the transistor Tr203. For this reason, the potential of the output signal 03 becomes ≈VEE. Further, since the potential of the node α becomes ≈VDD−Vth, while the potential of the output signal 03 becomes ≈VEE, the capacitor 205 holds a charge corresponding to ≈ (VDD−Vth) −VEE.

  On the other hand, when the output signal / 02 supplied to the input terminal in becomes Low level (VEE ′), the two transistors Tr312 and 204 on the pull-down side have a gate-source voltage of VEE′−VEE, which is higher than the threshold voltage. Since it takes a slightly high value, it cannot be completely turned off, but is almost turned off. Therefore, of the two transistors Tr203 and 204 in the output stage, only the transistor Tr203 is completely turned on, and the potential of the output signal 03 starts to rise.

  Further, since the charge corresponding to ≈ (VDD−Vth) −VEE is held in the capacitor 205, it is supplied to the potential of the node α, that is, the gate of the transistor Tr203 as the potential of the output signal 03 rises. Increase the potential further. Due to the bootstrap effect of the capacitor 205, the transistor Tr203 is sufficiently turned on. Note that the transistor Tr201 is turned off when the potential of the node α becomes higher than VDD. The potential of the output signal 03 is VDD ′ slightly lower than VDD because the transistor Tr204 is not completely turned off. Further, due to the bootstrap effect of the capacitor 205, the potential of the node α is increased to approximately {(VDD−Vth) −VEE} + VDD ′, that is, slightly more than twice the high potential power supply VDD.

  By the way, as described above, low level floating occurs in the output signal 02 of the level shifter 300, and the low level potential is VEE ′ slightly higher than VEE. In the buffer 241, the output signal / 02 is supplied to the gate G of the transistor Tr312 and the gate of the transistor Tr204. Therefore, when a TFT having a high driving capability and a low threshold voltage is used as the transistors Tr312, 204, when the low level (VEE ′) of the output signal / 02 is supplied to the input terminal in, the transistors Tr312, 204 The source-to-source voltage becomes VEE'-VEE, which may take a value near the threshold voltage. In such a case, since the gate voltage near the threshold voltage is constantly applied to the transistors Tr312 and 204 while the low level of the output signal / 02 is supplied, performance degradation or malfunction due to hot carriers is applied. Will occur.

  Furthermore, in addition to the problem due to hot carriers, the transistor Tr312 is applied with a drain voltage that has been increased to more than twice that of the high potential power supply VDD by the bootstrap effect as described above. Becomes even larger. If the transistor Tr312 deteriorates, this deterioration causes a low level floating in the output signal 03 of the buffer 241, and the same deterioration occurs in the TFTs provided in the circuits in the subsequent stages.

  As described above, in this embodiment, the transistor Tr312 is a TFT having the body structure shown in FIG. 3, and the body B is connected to the source S, thereby reducing deterioration and malfunction of the transistor Tr312 due to hot carriers. In addition, the reliability of the buffer 241 is increased. Note that there are various theories about the reason why deterioration and malfunction due to hot carriers can be suppressed by connecting the body B to the source S in the TFT, and the definite thing has not yet been elucidated. However, it has been confirmed by simulations and experiments that the deterioration and malfunction due to hot carriers are reduced by connecting the body B to the source S in the TFT.

  As described above, according to the present embodiment, among the four transistors Tr201, 312, 203, and 204 provided in the buffer 241, the output signal / 02 from the level shifter 300 is supplied to the gate, and the high potential power supply is generated by the bootstrap effect. Since the transistor Tr312 to which the potential increased to slightly higher than VDD is supplied to the drain is a TFT having a body structure, and the body B is connected to the source S, the output signal / 02 of the level shifter 300 is low. Even if the level is lifted, deterioration or malfunction of the transistor Tr312 due to hot carriers can be suppressed. Therefore, the reliability of the buffer 241 and the negative direction level shift circuit 401 can be improved.

  Since the output signal 02 from the level shifter 300 is also supplied to the gate of the transistor Tr204, the transistor Tr204 shown in FIG. 2 is also replaced with a transistor Tr312 (FIG. 3) having a body structure, and its body B is replaced by It may be configured to connect to the source S. In this way, the transistor Tr204 can also be prevented from being deteriorated or malfunctioning due to hot carriers.

Second Embodiment
FIG. 4 is a circuit diagram showing a configuration of the buffer 242 according to the second embodiment.
In the figure, components common to the buffer 241 described in the first embodiment are denoted by the same reference numerals. The buffer 242 according to the present embodiment is different from the buffer 241 according to the first embodiment in that a capacitor 206 is connected between the node α (the gate of the transistor Tr203) and the second power supply terminal (VEE).

  When the capacitor 206 is added in this way, when the Hi level (VDD) of the output signal 02 is supplied to the input terminal in, the capacitor 205 and the capacitor 206 have a charge corresponding to ≈ (VDD−Vth) −VEE. Is retained. On the other hand, when the low level (VEE ′) of the output signal / 02 is supplied to the input terminal in, the potential of the output signal 03 starts to rise. At this time, the transistor Tr204 is shifted to an almost OFF state. The charges held in the capacitors 205 and 206 are redistributed in a manner inversely proportional to the capacitance values (capacitance division). Therefore, the potential of the node α can be set to a lower value as long as the bootstrap operation is sufficiently possible. That is, in the first embodiment, the potential of the node α becomes {(VDD−Vth) −VEE} + VDD ′ due to the bootstrap effect, but in this embodiment, the potential of the node α is within a range where the bootstrap operation is possible. Therefore, it can be lowered to a value lower than {(VDD−Vth) −VEE} + VDD ′. Therefore, the potential applied to the drain D of the transistor Tr312 can be lowered, and deterioration of the transistor Tr312 can be reduced as compared with the case of the first embodiment.

  In FIG. 4, the capacitor 206 may be connected not between the node α and the second power supply terminal (VEE) but between the node α and the first power supply terminal (VDD). In FIG. 4, the transistor Tr204 may be replaced with the transistor Tr312 (FIG. 3) having a body structure, and the body B may be connected to the source S.

<Third Embodiment>
FIG. 5 is a circuit diagram showing a configuration of the buffer 243 according to the third embodiment.
In the figure, components common to the buffer 241 described in the first embodiment are denoted by the same reference numerals. The buffer 243 according to the present embodiment is different from the buffer 241 (FIG. 2) according to the first embodiment in that an N-channel transistor having a back gate structure is used instead of the N-channel transistor Tr312 (TFT) having a body structure. The Tr322 (TFT) is used and the back gate BG is connected to the source S. A structure of the transistor Tr322 is illustrated in FIG.

  As shown in FIG. 6, the transistor Tr322 is formed on the surface of the insulating substrate 20. A back gate BG is formed on the surface of the base layer 21 covering the substrate 20. The back gate BG is covered with a gate insulating film 23, and a semiconductor layer 25 (for example, a polysilicon film body) is formed on the surface of the gate insulating film 23. A gate G is formed so as to face the channel region of the semiconductor layer 25 with the gate insulating film 27 on the surface of the semiconductor layer 25 interposed therebetween. A source S is connected to the source region of the semiconductor layer 25 through a through hole of the interlayer insulating layer 29, and a drain D is connected to the drain region of the semiconductor layer 25 through a through hole of the interlayer insulating layer 29.

  As described above, in this embodiment, the transistor Tr322 having the back gate structure is used instead of the transistor Tr312 having the body structure, and the back gate BG is connected to the source S. However, as in the case of the first embodiment, deterioration and malfunction of the transistor Tr322 due to hot carriers can be reduced. As to the reason why deterioration and malfunction due to hot carriers can be suppressed by connecting the back gate BG to the source S in the TFT, as with the case where the body B is connected to the source S, the definite thing has not yet been elucidated. Not. However, it has been confirmed by simulations and experiments that the deterioration and malfunction due to hot carriers are reduced by connecting the back gate BG to the source S in the TFT.

  Further, under the premise of having an LDD (Lightly Doped Drain) region, the improvement in the breakdown voltage between the source and the drain can be explained as follows. That is, when the potential of the back gate electrode is fixed to a potential close to the source potential and the voltage between the source and the drain is set to a large value, a voltage difference is generated between the drain region and the back gate electrode. The electric field at this time works to lower the effective carrier concentration in the low concentration impurity region. Therefore, it can be considered that the breakdown voltage between the source and the drain is improved by the same effect as when the impurity concentration is lowered when the back gate structure is not provided (the carrier concentration is newly added to the low concentration region close to the high concentration region). A small part is generated, and a part of the voltage between the source and the drain is applied to this part, and the voltage between the source and the drain concentrated on the gate electrode end in the low concentration region is dispersed).

  As described above, according to the present embodiment, among the four transistors Tr201, 322, 203, and 204 provided in the buffer 243, the output signal / 02 from the level shifter 300 is supplied to the gate, and the high potential power supply is generated by the bootstrap effect. Since the transistor Tr322 to which the potential increased to slightly higher than VDD is supplied to the drain is a TFT having a back gate structure, and the back gate BG is connected to the source S, the output signal 02 of the level shifter 300 Even when a low level float occurs, deterioration or malfunction of the transistor Tr322 due to hot carriers can be suppressed. Therefore, the reliability of the buffer 243 and the negative direction level shift circuit configured using the buffer 243 can be improved.

  Since the output signal 02 from the level shifter 300 is also supplied to the gate of the transistor Tr204, the transistor Tr204 shown in FIG. 5 is also replaced with a transistor Tr322 (FIG. 6) having a back gate structure, and its back gate. The BG may be connected to the source S. In this way, the transistor Tr204 can also be prevented from being deteriorated or malfunctioning due to hot carriers.

<Fourth embodiment>
FIG. 7 is a circuit diagram showing a configuration of the buffer 244 according to the fourth embodiment.
In the figure, components common to the buffer 243 described in the third embodiment are denoted by the same reference numerals. The buffer 244 according to the present embodiment is different from the buffer 243 according to the third embodiment in that a capacitor 206 is connected between the node α and the second power supply terminal (VEE). When the capacitor 206 is added in this way, as described in the second embodiment, the potential of the node α is set to a lower value within the range in which the bootstrap operation can be performed by dividing the capacitor 205 and the capacitor 206. Can do. Therefore, the potential applied to the drain D of the transistor Tr322 can be lowered, and the deterioration of the transistor Tr322 can be reduced as compared with the case of the third embodiment.

  In FIG. 7, the capacitor 206 may be connected not between the node α and the second power supply terminal (VEE) but between the node α and the first power supply terminal (VDD). In FIG. 7, the transistor Tr204 may be replaced with the transistor Tr322 (FIG. 6) having a back gate structure, and the back gate BG may be connected to the source S.

<Fifth Embodiment>
FIG. 8 is a circuit diagram showing a configuration of the buffer 245 according to the fifth embodiment.
In the figure, components common to the buffer 243 described in the third embodiment are denoted by the same reference numerals. The buffer 245 according to the present embodiment is different from the buffer 243 (FIG. 5) according to the third embodiment in that the input signal V _BG is applied to the back gate BG instead of connecting the back gate BG of the transistor Tr322 to the source S. This is the point of supply. Since the input signal V _BG is supplied in this way, the buffer 245 is provided with the second input terminal in2.

FIG. 9 shows the relationship between the voltage V _G (horizontal axis) applied to the gate G and the drain current I _D (vertical axis) flowing between the source S and the drain D in the N-channel transistor Tr322 as the back gate BG. It is the graph shown for every applied voltage _VBG . As is apparent from this graph, when a positive voltage is applied to the back gate BG, the threshold voltage shifts in the left (minus) direction, while when a negative voltage is applied to the back gate BG, the threshold voltage shifts in the right (plus) direction. To do. As described above, in the N-channel transistor Tr322 having the back gate structure, the threshold voltage increases as the voltage V _BG applied to the back gate BG decreases, and the transition to the ON state becomes difficult.

Figure 10 is an output signal / 02 of the level shifter 300 is supplied to the first input terminal in, a timing chart of the input signal V _BG to be supplied to the second input terminal in2. As shown in the figure, the input signal _VBG has a waveform in phase with the output signal / 02, and only the values of the Low level and the Hi level are different. As is clear from the timing chart shown in FIG. 8 and the circuit diagram shown in FIG. 8, in the buffer 245 according to this embodiment, the Hi level (VDD) of the output signal / 02 is supplied to the first input terminal in. the, Hi level of the input signal V _BG to the back gate BG of the transistor Tr322 (VEE = about -4 V) is supplied. On the other hand, when the Low level of the output signal / 02 to the first input terminal in (VEE ') is supplied, the Low level of the input signal V _BG to the back gate BG of the transistor Tr322 (VEE-VDD = about -12V) Is supplied.

In this way the buffer 245, controlled by using an input signal V _BG the voltage applied to the back gate BG of the transistor Tr322, the transistor Tr322, and the threshold voltage _{Vth ON} when turned on, when turned off By making the threshold voltage Vth _OFF different and setting threshold voltage Vth _OFF > threshold voltage Vth _ON , it is difficult to turn on the transistor Tr322 in the off state.

Further, in the buffer 245 according to the present embodiment, Low level of the input signal V _BG, i.e., the potential applied to the back gate BG of the transistor Tr322 in the OFF state, by the VEE-VDD (about -12V) The threshold voltage Vth _OFF is changed to a value larger than VEE′−VEE.

Note that the potential that must be applied to the back gate BG in order to change the threshold voltage Vth _OFF to a value larger than VEE′−VEE is the characteristics of the transistor used as the transistor Tr322 (the threshold voltage Vth and the back gate BG). It _depends on the relationship with the applied back gate voltage _VBG . The VEE-VDD described above is merely an example, and a back gate voltage V _BG that can make the threshold voltage Vth _OFF larger than VEE′-VEE is appropriately selected according to the characteristics of the transistor to be used. It may be applied to the back gate BG of the transistor Tr322 during a period in which 02 is at a low level.

When the threshold voltage Vth _OFF of the transistor Tr322 in the off state is made larger than VEE′−VEE in this way, the transistor Tr322 supplies the gate G with the low level (VEE ′) of the output signal / 02, and the gate source Even if the inter-voltage becomes VEE′−VEE, this does not become a value in the vicinity of the threshold voltage Vth _OFF , so that deterioration or malfunction due to hot carriers can be suppressed.

According to this embodiment, controlled by using an input signal V _BG the voltage applied to the back gate BG of the transistor Tr322, the threshold voltage _{Vth OFF} of the transistor Tr322 in the OFF state, the output signal / 02 Low level (VEE ′) — Because it can be shifted to a value larger than the low-potential power supply VEE, even if a low level float occurs in the output signal 02 of the level shifter 300, deterioration or malfunction of the transistor Tr322 due to hot carriers is caused. Can be suppressed. In addition, occurrence of leakage in the transistor Tr322 can be prevented. Therefore, the reliability of the buffer 245 and the negative direction level shift circuit configured using the buffer 245 can be improved.

Since the output signal 02 from the level shifter 300 is also supplied to the gate of the transistor Tr204, the transistor Tr204 shown in FIG. 8 is also replaced with a transistor Tr322 (FIG. 6) having a back gate structure, and its back gate. The input signal _VBG may be supplied to the _BG . Further, in FIG. 8, a capacitor is connected between the node α and the first power supply terminal (VDD) or the second power supply terminal (VEE), and the potential applied to the drain D of the transistor Tr322 is changed to the bootstrap operation. It may be lowered to a lower value as much as possible.

<Sixth Embodiment>
FIG. 11 is a circuit diagram showing a configuration of the buffer 246 according to the sixth embodiment.
In the figure, components common to the buffer 245 in the fifth embodiment are denoted by the same reference numerals. The buffer 246 according to the present embodiment is different from the buffer 245 according to the fifth embodiment in that the back gate BG of the transistor Tr322 is connected to the gate G. Further, since the output signal / 02 of the level shifter 300 is also supplied to the back gate BG of the transistor Tr322 by connecting the back gate BG to the gate G, the input signal V _BG is different from the case of the fifth embodiment. Is no longer necessary. For this reason, the buffer 246 does not have the second input terminal in2. An output signal 02 of the level shifter 300 supplied to the input terminal in of the buffer 246 is shown in FIG.

  In the buffer 246 according to this embodiment, when the Hi level (VDD) of the output signal / 02 is supplied to the input terminal in, the Hi level (VDD) of the output signal / 02 is also applied to the back gate BG of the transistor Tr322. Supplied. On the other hand, when the low level (VEE ′) of the output signal 02 is supplied to the input terminal in, the low level (VEE ′) of the output signal 02 is also supplied to the back gate BG of the transistor Tr322.

As described above, in the buffer 246 according to the present embodiment, by applying VDD (8 V) to the back gate BG, the threshold voltage Vth _ON value of the transistor Tr322 in the on state is set, while the VEE is applied to the back gate BG. By applying '(about -4V), the threshold voltage Vth _OFF of the transistor Tr322 in the off state is changed to a value larger than VEE'-VEE. When the threshold voltage Vth _OFF of the transistor Tr322 in the off state is made larger than VEE′−VEE in this way, the transistor Tr322 supplies the gate G with the low level (VEE ′) of the output signal / 02, and the gate source Even if the inter-voltage becomes VEE′−VEE, this does not become a value in the vicinity of the threshold voltage Vth _OFF , so that deterioration or malfunction due to hot carriers can be suppressed.

As described above, also in the buffer 246 according to the present embodiment, the threshold voltage Vth _OFF of the transistor Tr322 in the off state is set to a value larger than the low level (VEE ′) of the output signal / 02−the low potential power supply VEE. Since it can be shifted, the same effect as in the case of the fifth embodiment described above can be obtained. Further, since it is only necessary to connect the back gate BG of the transistor Tr322 to the gate G, the circuit configuration can be simplified as compared with the case of the fifth embodiment.

The characteristic of the transistor used as a transistor Tr322 some (and the threshold voltage Vth, the relationship between the back gate voltage V _BG that is applied to the back gate BG), and it supplies an output signal / 02 to the back gate BG of the transistor Tr322 However, the threshold voltage Vth _OFF may not be changed to a value larger than VEE′−VEE. That is, even if the back gate voltage V _{BG is set} to the low level of the output signal / 02, the threshold voltage Vth _OFF of the transistor Tr322 may not be made larger than VEE′−VEE.

  In FIG. 11, the transistor Tr204 may be replaced with a transistor Tr322 (FIG. 6) having a back gate structure and connected to the gate G of the back gate BG. In FIG. 11, a capacitor is connected between the node α and the first power supply terminal (VDD) or the second power supply terminal (VEE), and the potential applied to the drain D of the transistor Tr322 is changed to the bootstrap operation. It may be lowered to a lower value as much as possible.

<Seventh embodiment>
Next, an electronic apparatus using the level shifter 300 and the negative direction level shift circuit X configured by any of the buffers 241 to 246 described in the first to sixth embodiments will be described. In this example, the negative direction level shift circuit X is applied to a display device using a liquid crystal or an organic light emitting diode element. The display device includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixel circuits arranged in a matrix corresponding to the intersections. The pixel circuit includes a switching transistor that captures a data signal supplied via the data line in accordance with a scanning signal supplied via the scanning line. In addition, the display device includes a scanning line driving circuit that drives a plurality of scanning lines and a data line driving circuit that drives a plurality of data lines. The negative direction level shift circuit X described above can be applied to a scanning line driving circuit and a data line driving circuit. Hereinafter, a case where the negative direction level shift circuit X is used in the scanning line driving circuit of the liquid crystal display device will be described. Note that the entire display device is composed of TFTs of the same conductivity type.

FIG. 13 shows part of the configuration of the scanning line driving circuit 100.
The scanning line driving circuit 100 includes a shift register 110 that sequentially transfers the start pulse SP according to the Y clock signal YCK and outputs transfer signals y1, y2,... Ym, and m drivers U1 to Um. The pixel circuit P includes a switching transistor 40 and a liquid crystal element 41. The liquid crystal element 41 includes a pixel electrode connected to the switching transistor 40 and a counter electrode, and is configured by sandwiching liquid crystal between the pixel electrode and the counter electrode. The data signal Vdata supplied through the data line 30 is taken into the pixel circuit P and applied to the liquid crystal element when the scanning signal Y is at the Hi level. The applied voltage is held by the liquid crystal capacitance even when the scanning signal Y transitions to the low level. Note that a storage capacitor may be provided in parallel with the liquid crystal element 41.

  Here, the data signal Vdata changes between GND and VDD. In this case, in order to sufficiently turn on the switching transistor 40 and to turn it off sufficiently, it is preferable that the amplitude of the scanning signal Y is changed from VEE (<GND) to VDH (> VDD). In the shift register 110, a transfer signal y having an amplitude of VEE-VDH can be generated and used as the scanning signal Y. However, in such a case, the power consumption of the shift register 110 increases. Therefore, the high potential power supply VDD and the low potential power supply GND are supplied to the shift register 110, and the transfer signal y having the amplitude GND-VDD is generated.

  The drivers U1 to Um generate the scanning signals Y1 to Ym based on the transfer signals y1 to ym supplied from the shift register 110. The drivers U1 to Um are configured by the above-described negative direction level shift circuit X, and VDH (> VDD) is supplied to the level shifter and the buffer constituting the negative direction level shift circuit X as a high potential power source. VEE (<GND) is supplied as a potential power source.

  In the negative direction level shift circuit X, in the level shifter, the signal level of the input signals 01 and / 01 (transfer signal y) whose amplitude is VDD-GND is shifted in the negative direction, the Hi level is VDH, and the Low level is from VEE. Output signals 02 and / 02 that are slightly higher VEE ′ are generated. Further, the buffer inverts the logic level of the output signal / 02 from the level shifter, and generates an output signal 03 (scanning signal Y) in which the Low level is VEE and the Hi level is VDH 'slightly lower than VDH. Therefore, the amplitudes of the scanning signals Y1 to Ym output from the drivers U1 to Um are VDH ′ whose Low level is VEE (<GND) and whose Hi level is slightly lower than VDH.

  Thus, in the negative direction level shift circuit X, the low level floating generated in the output signals 02 and 02 of the level shifter and the drop in the Hi level generated in the buffer output signal 03 cannot be eliminated. As described in the sixth embodiment, since the pull-down transistors Tr312, 322, and 204 provided in the buffers 241 to 246 are suppressed from deterioration and malfunction due to hot carriers, the reliability of the display device is also improved. can do. The negative direction level shift circuit X described above may be incorporated in a data line driving circuit or a shift register. These can be applied to display devices, in particular, liquid crystal display devices using amorphous TFTs and liquid crystal display devices using low-temperature polysilicon TFTs.

<Modification>
(1) In the above-described embodiments, the case where the present invention is applied to the 1-input 1-output type buffers 241 to 246 has been described. However, the present invention can also be applied to a 2-input 1-output type buffer. . For example, in the buffer 240a shown in FIG. 17C, the transistor Tr201 is not diode-connected, and the output signal 02 (a signal obtained by inverting the output signal / 02) from the level shifter 300 is supplied to the gate of the transistor Tr201. The

  In the buffer 240a shown in FIG. 17C, the transistor Tr202 may be replaced with a transistor Tr312 (FIG. 3) having a body structure, and the body B may be connected to the source S (first embodiment). In this case, a capacitor may be added between the gate of the transistor Tr203 and the first power supply terminal (VDD) or the second power supply terminal (VEE) (second embodiment). Since the output signals 02 and / 02 from the level shifter 300 are also supplied to the gates of the transistors Tr201 and 204, the transistor Tr201 and the transistor Tr204 are also replaced with a transistor Tr312 having a body structure, and the body B May be connected to the source S.

  Further, in the buffer 240a shown in FIG. 17C, the transistor Tr202 may be replaced with a transistor Tr322 (FIG. 6) having a back gate structure, and the back gate BG may be connected to the source S (third embodiment). ). In this case, a capacitor may be added between the gate of the transistor Tr203 and the first power supply terminal (VDD) or the second power supply terminal (VEE) (fourth embodiment). Further, the transistor Tr201 and the transistor Tr204 may be replaced with the transistor Tr322 having a back gate structure, and the back gate BG may be connected to the source S.

Further, in the buffer 240a shown in FIG. 17C, the transistor Tr202 may be replaced with a transistor Tr322 (FIG. 6) having a back gate structure, and the input signal V _BG may be supplied to the back gate BG (fifth). Embodiment). In this case, a capacitor may be added between the gate of the transistor Tr203 and the first power supply terminal (VDD) or the second power supply terminal (VEE). As for the transistor Tr201 and transistor Tr204, replaced by a transistor Tr322 having a back gate structure this may be configured to supply an input signal V _BG to the back gate BG.

  In the buffer 240a shown in FIG. 17C, the transistor Tr202 may be replaced with a transistor Tr322 (FIG. 6) having a back gate structure, and the back gate BG may be connected to the gate G (sixth embodiment). ). In this case, a capacitor may be added between the gate of the transistor Tr203 and the first power supply terminal (VDD) or the second power supply terminal (VEE). Further, the transistor Tr201 and the transistor Tr204 may be replaced with the transistor Tr322 having a back gate structure, and the back gate BG may be connected to the gate G.

  Further, a negative direction level shift circuit is configured by using the 2-input 1-output type buffer configured as described above and the level shifter 300 shown in FIG. 17B, or configured in this way. The negative direction level shift circuit may be incorporated in a scanning line driving circuit or a data line driving circuit of the display device.

(2) In each of the embodiments and the modification example (1) described above, the negative direction level shifter circuit constituted by N-channel transistors has been described. However, the present invention relates to a positive direction level shifter constituted by P-channel transistors. It can also be applied to circuits. That is, all the transistors included in the buffer may be P-channel transistors. The case where the present invention is applied to a buffer composed of P-channel transistors will be described below.

  FIG. 14 is a circuit diagram in a case where the circuit shown in FIG. 2 (buffer 241 configured by N-channel transistors: the first embodiment) is configured by P-channel transistors. In the figure, the first to fourth transistors are all P-channel TFTs, but only the second transistor has a body structure. Further, an output signal 02 from the level shifter 300 is supplied as an input signal to the gate of the second transistor, but a drop in the Hi level occurs in the output signal 02, and the potential of the Hi level Becomes VDD ′ slightly lower than VDD, while the low-level potential becomes VEE.

  In FIG. 14, when a P-channel TFT having no body structure is used as the second transistor, when the Hi level (VDD ′) of the input signal is supplied to the gate of the second transistor, The source voltage is VDD′−VDD, but when a TFT having a high driving capability and a low threshold voltage is used as the second transistor, this may take a value near the threshold voltage. In such a case, since the gate voltage near the threshold voltage is constantly applied to the second transistor while the Hi level of the output signal / 02 is supplied, performance degradation or malfunction due to hot carriers is caused. It will occur. Furthermore, since the drain voltage, which is increased to slightly more than twice that of the high-potential power supply VDD due to the bootstrap effect by the capacitive element, is applied to the second transistor, the progress of deterioration is further increased. As described above, even in the buffer 251 configured with a P-channel transistor, the second transistor is a TFT having a body structure, and the body B is connected to the source S. And the reliability of the buffer 251 can be increased.

FIG. 15 is a circuit diagram in the case where the circuit shown in FIG. 8 (buffer 245 configured by N-channel transistors: the fifth embodiment) is configured by P-channel transistors. In the figure, the first to fourth transistors are all P-channel TFTs, but only the second transistor has a back gate structure. Further, the output signal / 02 from the level shifter 300 is supplied to the gate of the second transistor, but a drop in the Hi level occurs in the output signal / 02, and the Hi level potential is higher than VDD. Slightly lower VDD '. Note that as shown in FIG. 16, in a P-channel transistor having a back gate structure, the threshold voltage decreases as the voltage V _BG applied to the back gate BG increases, and the transition to the on state becomes difficult.

In the buffer 255 shown in FIG. 15, a TFT having a back gate structure is used as the second transistor, and the potential applied to the back gate BG is controlled using the input signal V _BG . Then, in a period in which the amplitude level of the input signal is Hi level (VDD ′), the threshold voltage of the second transistor is set to VDD′−VDD [Hi level (high potential) of input signal−high]. A potential that can be made smaller than the potential power supply VDD (second potential)] is supplied. As a result, the threshold voltage of the second transistor is shifted to a voltage value smaller than VDD′−VDD during the period when the input signal is at the Hi level (high potential). Therefore, when the Hi level (VDD ′) of the input signal is supplied to the gate of the second transistor, even if the gate-source voltage becomes VDD′−VDD in the second transistor, this is a value near the threshold voltage. Therefore, deterioration and malfunction of the second transistor due to hot carriers can be suppressed. This can also prevent the occurrence of leakage in the second transistor.

  As described above, the present invention can also be applied to a buffer composed of P-channel transistors. That is, in each of the embodiments and the modification example (1) described above, the present invention can also be applied to the case where the buffer configured with an N-channel transistor is replaced with a buffer configured with a P-channel transistor.

It is a block diagram which shows the whole structure of the negative direction level shift circuit 401 which concerns on 1st Embodiment. 3 is a circuit diagram showing a configuration of a buffer 241 according to the same embodiment. FIG. FIG. 10 is a plan view illustrating a structure of a transistor Tr312. It is a circuit diagram which shows the structure of the buffer 242 which concerns on 2nd Embodiment. It is a circuit diagram which shows the structure of the buffer 243 which concerns on 3rd Embodiment. 7 is a cross-sectional view illustrating a structure of a transistor Tr322. It is a circuit diagram which shows the structure of the buffer 244 which concerns on 4th Embodiment. It is a circuit diagram which shows the structure of the buffer 245 concerning 5th Embodiment. 6 is a graph showing that a threshold voltage changes according to a voltage V _BG applied to a back gate BG in an N-channel transistor Tr322. And the output signal / 02 of the level shifter 300 is supplied to the first input terminal in the buffer 245 is a timing chart of the input signal V _BG to be supplied to the second input terminal in2. It is a circuit diagram which shows the structure of the buffer 246 which concerns on 6th Embodiment. 6 is a waveform diagram of an output signal / 02 of the level shifter 300 supplied to an input terminal in of a buffer 246. FIG. It is a block diagram which shows the structure of the scanning line drive circuit 100 which concerns on 7th Embodiment. It is a circuit diagram which shows the structure of the buffer 251 which concerns on a modification (2). It is a circuit diagram which shows the structure of the buffer 255 which concerns on a modification (2). 5 is a graph showing that a threshold voltage changes according to a voltage V _BG applied to a back gate BG in a P-channel transistor. It is a figure which shows an example of a negative direction level shift circuit. FIG. 18 is a waveform diagram of input / output signals in the negative direction level shift circuit shown in FIG. 17.

Explanation of symbols

  400, 401 ... negative direction level shift circuit, 300 ... level shifter, 240a, 240b, 241-246, 251, 255 ... buffer, Tr101-106, Tr201-204 ... transistor, 312 ... transistor (with body), 322 ... transistor ( G ... gate, S ... source, D ... drain, B ... body, BG ... back gate, C107, 108, 205, 206 ... capacitance, 100 ... scanning line drive circuit, 110 ... shift register, U1- Um ... driver (negative direction level shift circuit), 30 ... data line, P ... pixel circuit, 40 ... switching transistor, 41 ... liquid crystal element.

Claims (13)

A buffer for generating an output signal obtained by inverting the logic level of an input signal,
A first transistor in which a first potential is supplied to a drain and a gate is connected to the drain;
A second transistor having the gate supplied with the input signal, the drain connected to the source of the first transistor, and the source supplied with a second potential;
A third transistor having a gate connected to a source of the first transistor and a drain supplied with the first potential;
A first capacitive element provided between a source of the third transistor and a gate of the third transistor;
A fourth transistor having the gate supplied with the input signal, the drain connected to the source of the third transistor, and the source supplied with the second potential;
Taking the output signal from the source of the third transistor;
The first to fourth transistors have the same conductivity type,
The second transistor includes a body,
Connecting the body and the source of the second transistor;
A buffer characterized by that. The fourth transistor includes a body,
Connecting the body of the fourth transistor and the source of the fourth transistor;
The buffer according to claim 1. A buffer for generating an output signal obtained by inverting the logic level of an input signal,
A first transistor in which a first potential is supplied to a drain and a gate is connected to the drain;
A second transistor having the gate supplied with the input signal, the drain connected to the source of the first transistor, and the source supplied with a second potential;
A third transistor having a gate connected to a source of the first transistor and a drain supplied with the first potential;
A first capacitive element provided between a source of the third transistor and a gate of the third transistor;
A fourth transistor having the gate supplied with the input signal, the drain connected to the source of the third transistor, and the source supplied with the second potential;
Taking the output signal from the source of the third transistor;
The first to fourth transistors have the same conductivity type,
The second transistor includes a back gate in addition to the gate,
Connecting the back gate and the source of the second transistor;
A buffer characterized by that. The fourth transistor includes a back gate in addition to the gate,
Connecting the back gate of the fourth transistor and the source of the fourth transistor;
The buffer according to claim 3. A buffer for generating an output signal obtained by inverting the logic level of an input signal having amplitude levels of a high potential and a low potential,
A first transistor in which a first potential is supplied to a drain and a gate is connected to the drain;
A second transistor having the gate supplied with the input signal, the drain connected to the source of the first transistor, and the source supplied with a second potential;
A third transistor having a gate connected to a source of the first transistor and a drain supplied with the first potential;
A first capacitive element provided between a source of the third transistor and a gate of the third transistor;
A fourth transistor having the gate supplied with the input signal, the drain connected to the source of the third transistor, and the source supplied with the second potential;
Taking the output signal from the source of the third transistor;
The first to fourth transistors have the same conductivity type,
The second transistor includes a back gate in addition to the gate,
In the back gate, when the conductivity type is N type, the threshold voltage of the second transistor is reduced from the low potential to the second potential in a period in which the amplitude level of the input signal is the low potential. In order to deviate from the voltage value, a potential for increasing the threshold voltage is supplied. On the other hand, when the conductivity type is P-type, the amplitude of the input signal is set to the high potential during the period of the second transistor. In order to shift the threshold voltage from a voltage value obtained by subtracting the second potential from the high potential, a potential for reducing the threshold voltage is supplied.
A buffer characterized by that. Connecting the back gate and the gate of the second transistor;
The buffer according to claim 5. The fourth transistor includes a back gate in addition to the gate,
In the back gate of the fourth transistor, when the conductivity type is N type, the threshold voltage of the fourth transistor is changed from the low potential to the second potential during a period in which the amplitude level of the input signal is the low potential. In order to deviate from the voltage value obtained by reducing the potential, a potential for increasing the threshold voltage is supplied. On the other hand, when the conductivity type is P-type, the amplitude level of the input signal is the high potential in the period. In order to shift the threshold voltage of the fourth transistor from the voltage value obtained by subtracting the second potential from the high potential, a potential for reducing the threshold voltage is supplied.
The buffer according to claim 5. Connecting the back gate of the fourth transistor and the gate of the fourth transistor;
The buffer according to claim 7. A first power supply terminal to which the first potential is supplied;
A second power supply terminal to which the second potential is supplied;
A second capacitor provided between the gate of the third transistor and the first power supply terminal or the second power supply terminal;
The buffer according to claim 1, wherein the buffer is a buffer. The first transistor includes:
Instead of the first potential being supplied to the drain and the gate being connected to the drain,
A first potential is supplied to the drain, and an inverted input signal obtained by inverting the logic level of the input signal is supplied to the gate.
The buffer according to claim 1, wherein the buffer is a buffer. All the transistors constituting the buffer are thin film transistors.
The buffer according to claim 1, wherein the buffer is a buffer. With respect to a first input signal having an amplitude level between a reference potential and a third potential, a potential having an amplitude level on the third potential side is set to a fourth potential at which a difference from the reference potential is larger than the third potential. A level shifter for generating a first output signal that
The buffer according to any one of claims 1 to 11 connected to a subsequent stage of the level shifter,
The conductivity types of all the transistors constituting the level shifter and the buffer are the same,
The first output signal is provided as the input signal of the buffer;
A level shift circuit characterized by that. A display device comprising a plurality of scanning lines, a plurality of data lines, and a plurality of pixel circuits provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines,
A scanning line driving circuit for supplying a scanning signal to each of the plurality of scanning lines;
A data line driving circuit for supplying a data signal to each of the plurality of data lines,
The level shift circuit according to claim 12 is used for an output stage of the scanning line driving circuit.
A display device characterized by that.

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