JP2014153532A - Display device and drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device and a drive circuit that can suppress power consumption even when a transistor to be put into a depletion type operation is used.SOLUTION: The display device includes: a plurality of display pixels PX that are arranged in a matrix; a plurality of drive lines G and S that extend along a row and column where the plurality of display pixels are arrayed; and at least one of drive circuits 21 and 31 that outputs a drive signal to the plurality of drive lines. The drive circuit comprises: a plurality of shift registers 22 and 32 that shift a phase of a signal to be input, and output the signal as a drive signal; an output circuit SROC that is provided on each shift register. The output circuit includes: at least one transistor T1 that forms the drive signal; a capacitor element Ca that has one end connected to a control electrode of the transistor, and the other end to which a voltage for controlling intermittence of the transistor is applied; and a control circuit T10 that controls whether to impart a predetermined voltage to the control electrode of the transistor or float the control electrode thereof.

Description

  Embodiments described herein relate generally to a display device and a driving circuit.

  A display device typified by a liquid crystal display device is thin, lightweight, and has low power consumption, and is therefore used as a display for various devices. In particular, an active matrix liquid crystal display device in which a transistor is arranged for each pixel is becoming widespread as a display for a notebook personal computer or a portable information terminal.

  In recent years, research and development of thin film transistors using oxide semiconductor films, which have higher electron mobility than amorphous silicon thin film transistors (TFTs) used in conventional liquid crystal display devices, have become active. As a result, a pixel portion having a transistor disposed at each intersection of a plurality of scanning lines and a plurality of signal lines and a driving circuit for driving each transistor are integrally formed on the electrode substrate by the same manufacturing process. Can now.

JP 2012-19108 A

  By the way, it has been reported that, in the oxide semiconductor film, an electrically shallow impurity level is formed due to the ingress of hydrogen gas or the like, resulting in low resistance. When such an oxide semiconductor film is used for a thin film transistor, a normally-on type, that is, a depletion type operation in which a drain current flows even when a gate voltage is not applied, and a threshold voltage increases as the defect level increases. It becomes smaller and the leakage current increases.

  Not only when an oxide semiconductor film is used for a thin film transistor, but when a driver circuit using a transistor that operates in a depletion mode is used, current also flows to a transistor that should normally be turned off, which increases power consumption of the driver circuit. Problems occur. In particular, in an output circuit that drives an output unit such as a scanning line with a large load, it is necessary to set the channel width (W value) of a transistor larger than that of other transistors, which is a major factor in increasing power consumption.

  The present invention has been made in view of such circumstances, and provides a display device and a driving circuit capable of suppressing power consumption even when a transistor having a depletion type operation is used. is there.

  A display device according to one embodiment of the present invention is driven by a plurality of display pixels arranged in a matrix, a plurality of drive lines extending along rows and columns in which the plurality of display pixels are arranged, and the plurality of drive lines. A plurality of shift registers that output a signal as a drive signal by shifting the phase of the input signal, and an output circuit provided in each of the shift registers. And the output circuit includes at least one transistor for forming the drive signal, a capacitor element having one end connected to a control electrode of the transistor and a voltage applied to the other end for controlling the on / off of the transistor. And a control circuit for controlling whether to apply a predetermined voltage to the control electrode of the transistor or to make the control electrode floating.

It is a circuit diagram which shows the structure of the display apparatus in one embodiment. It is a circuit diagram which shows the internal structure of the drive circuit of the display apparatus in one Embodiment. 3 is a circuit diagram of a shift register provided in a drive circuit of a display device in one embodiment. FIG. 6 is a timing chart of signals of a shift register of the display device in one embodiment. It is a figure which shows the electric potential of each node of the period of the time t2-t3 of the shift register of the display apparatus in one Embodiment. It is a figure which compares and shows the Vgs-Ids characteristic of an nMOS enhancement type transistor and a depletion type transistor. It is a figure which shows the electric potential of each node after time t3 (before time t1) of the shift register of the display apparatus in one embodiment. 3 is a circuit diagram of a shift register provided in a drive circuit of a display device in one embodiment. FIG.

  FIG. 1 is a circuit diagram illustrating a configuration of a display device according to an embodiment. Here, an active matrix liquid crystal display device will be described as an example. The display device shown in the figure includes a pixel portion 11, a scanning line driving circuit 21, and a signal line driving circuit 31 on a transparent substrate 10.

  In the pixel unit 11, a plurality of scanning lines G1, G2,... Gn (hereinafter collectively referred to as “G”) and a plurality of signal lines S1, S2,. Are arranged so as to cross each other, and each intersection includes a switching element 12, a pixel electrode 13, a liquid crystal capacitor 14, and an auxiliary capacitor 15. As an example, an oxide semiconductor thin film transistor is used for the switching element.

  The scanning line driving circuit 21 includes a vertical shift register 22 including a plurality of shift registers electrically connected in cascade. The signal line drive circuit 31 connects a horizontal shift register 32 including a plurality of electrically connected shift registers, a video signal line 34 to which a video signal is supplied, and a video signal line 34 to each signal line S. And a plurality of analog switches 35.

  A start pulse signal (STP), a clock signal (CK), and a set signal (SET) are input to the vertical shift register 22 and the horizontal shift register 32. Here, the start pulse signal input to the vertical shift register 22 is referred to as STV, and the start pulse signal input to the horizontal shift register 32 is referred to as STH. The clock signal input to the vertical shift register 22 is referred to as CKV, and the clock signal input to the horizontal shift register 32 is referred to as CKH. The set signal input to the vertical shift register 22 is referred to as SETV, and the set signal input to the horizontal shift register 32 is referred to as SETH.

  The vertical shift register 22 and the horizontal shift register 32 shift the phase of the input start pulse signal STP and output it. The scanning line driving circuit 21 outputs a vertical scanning pulse from each internal shift register to each scanning line G while shifting the phase by one stage. The signal line driving circuit 31 outputs a horizontal scanning pulse while shifting the phase one step at a time from each internal shift register to the analog switch 35 provided on each signal line S to turn on the analog switch 35, and The video signal supplied to the video signal line 34 is output to each signal line S through the analog switch 35.

Each drive circuit is preferably configured using only one of an nMOS transistor and a pMOS transistor in order to shorten the manufacturing process and realize cost reduction. FIG. 2 illustrates driving of a display device according to an embodiment. It is a circuit diagram which shows the internal structure of a circuit. The scanning line drive circuit 21 and the signal line drive circuit 31 have basically the same configuration. Of course, only one of the drive circuits may have the configuration shown in FIG. This drive circuit includes a plurality of shift registers SR1, SR2,... SRn (hereinafter collectively referred to as SR) electrically connected in cascade, and three clock signals CK1, CK2, shifted in phase with respect to each shift register SR. This is a configuration including a clock line 36 for inputting any two of CK3. The clock signals CK1 to CK3 are the vertical clock signal CKV in the vertical shift register 22 and the horizontal clock signal CKH in the horizontal shift register 32. The set signal SET is set to SETV in the vertical register 22 and set to set in the horizontal shift register 32.

  Each shift register SR has a first clock terminal 41 and a second clock terminal 42. In the shift register SR1, the first clock signal CK1 is input to the first clock terminal 41, and the second clock signal CK2 is input to the second clock terminal. In the shift register SR2, the second clock signal CK2 is input to the first clock terminal 41, and the third clock signal CK3 is input to the second clock terminal. Each shift register SR has a set terminal 47. In this configuration example, it is assumed that each shift register SR is controlled by a common set signal. However, a configuration in which each shift register SR is provided with an individual set signal or a set of a plurality of shift registers SR is set. A configuration in which a signal is given is also possible.

  Each shift register SR shifts the phase of the input signal IN inputted so as to be synchronized with the two clock signals, and outputs it as an output signal OUT. As the input signal IN, the start pulse signal STP is input to the first-stage shift register SR1, and the output signal OUT of the previous-stage shift register SR is input to the second-stage and subsequent shift registers SR.

  The scanning line driving circuit 21 outputs the output signal OUT from each shift register SR to each scanning line G as a vertical scanning pulse, and the signal line driving circuit 31 uses the output signal OUT from each shift register SR as a horizontal scanning pulse. Output to the control electrode of each analog switch 35.

  FIG. 3 is a circuit diagram of the shift register SR provided in the drive circuit of the display device according to the embodiment. Hereinafter, the circuit configuration of the shift register SR will be described with reference to FIGS.

  An input signal IN is input to the input terminal 43. Also, any two of the three clock signals CK1 to CK3 whose phases are shifted are input to the clock terminal. In FIG. 3, as an example, the first clock signal CK 1 is input to the first clock terminal 41 and the second clock signal CK 2 is input to the second clock terminal 42. An output signal OUT is output from the output terminal 44. As an example, all the transistors included in the shift register SR are nMOS transistors.

  The shift register SR includes an input circuit SRIC, an inverter SRIN, a reset circuit SRST, and an output circuit SROC. The shift register SR is provided with nodes n1,..., Node n4.

[Input circuit]
The input circuit SRIC includes a third transistor T3 and a fourth transistor T4. The drain of the third transistor T3 is electrically connected to the power supply electrode 45, the gate is electrically connected to the input terminal 43, and the source is electrically connected to the node n4. The drain of the fourth transistor is electrically connected to the node n1, the gate is electrically connected to the input terminal 43, and the source is electrically connected to the power supply electrode 46.

  The power supply electrode 45 is supplied with a high level power supply voltage VGH, and the power supply electrode 46 is supplied with a low level power supply voltage VGL. The input circuit SRIC receives the input signal IN through the input terminal 43, and supplies the high level voltage VGH to the node n4 and the low level voltage VGL to the node n1.

[Inverter]
The inverter SRIN is configured by a fifth transistor T5 and a sixth transistor T6. Specifically, the gate and drain of the fifth transistor T5 are connected to the power supply electrode 45. The drain of the sixth transistor T6 is electrically connected to the source electrode of the fifth transistor T5, the gate is electrically connected to the node n4, and the source is electrically connected to the power supply electrode 46. The source of the fifth transistor T5 (the drain of the sixth transistor T6) is electrically connected to the node n1.

[Reset circuit]
The reset circuit SRST includes a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The seventh transistor T7 has a gate electrically connected to the second clock terminal 42, a source electrically connected to the output terminal 44, and a drain electrically connected to the node n4. The ninth transistor T9 has a gate electrically connected to the node n1, a source electrically connected to the output terminal 44, and a drain electrically connected to the node n4. The gate of the eighth transistor T8 is connected to the power supply electrode 45, the source is electrically connected to the node n4, and the drain is electrically connected to the node n2.

[Output circuit]
The output circuit SROC includes a first transistor T1, a second transistor T2, a tenth transistor T10, and a first capacitor Ca. The drain of the first transistor T1 is electrically connected to the first clock terminal 41, the source is electrically connected to the output terminal 44, and the gate is electrically connected to the node n3. The drain of the second transistor T2 is electrically connected to the output terminal 44, the source is electrically connected to the power supply electrode 46, and the gate is electrically connected to the node n1. A first clock signal CK 1 is input to the first clock terminal 41, and a low-level power supply voltage VGL is supplied to the power supply electrode 46. When the first transistor T1 is on and the second transistor T2 is off, the first clock signal CK1 is output to the output terminal 44. When the first transistor T1 is off and the second transistor T2 is on, the power supply voltage VGL is output. Output to terminal 44.

  One terminal of the first capacitive element Ca is electrically connected to the node n3 (the gate of the first transistor T1). The other terminal of the first capacitive element Ca is electrically connected to the node n2. The source of the tenth transistor T10 is connected to the power supply electrode 48, the drain is connected to the node n3, and the gate is electrically connected to the set terminal 47.

  A power supply voltage GVSS is input to the power supply electrode 48. The power supply voltage GVSS is set to be lower than the voltage supplied to the node n2 when supplied to the node n3 via the tenth transistor T10. A set signal SET is input to the gate of the tenth transistor T10. The set signal SET is a binary voltage of a high level voltage VGH and a low level voltage VGLL. The low level voltage VGLL is set to a value lower than GVSS (VGLL <GVSS) so that the tenth transistor T10 can be sufficiently turned off.

  The present drive circuit is characterized in that the output circuit SROC is provided with the first capacitive element Ca and the tenth transistor T10 to control the gate voltage of the tenth transistor T10. This point will be described in detail with reference to FIG.

FIG. 4 is a timing chart of each signal of the shift register of the display device according to the embodiment.
4 is a timing chart showing the relationship among the input signal IN, the clock signals CK1 to CK3, the nodes n1 to n4, the set signal SET, and the output signal OUT of the shift register in the shift register SR. The output signal OUT of the shift register is a signal obtained by shifting the phase of the input signal IN. The other shift registers SR operate in the same manner as the shift register SR according to the timing chart of FIG.

[Time t0-t0 ']
The period from time t0 to t0 ′ is a period in which all shift registers are not selected as in the vertical blanking period. At this time, since the high level voltage VGH is applied to the node n1 via the fifth transistor T5, the second transistor T2 is turned on, and the voltage of the output signal OUT becomes the low level voltage VGL. Further, since the ninth transistor T9 is also turned on, the voltages at the nodes n4 and n2 are the low level voltage VGL.

  During this period, the set signal SET is set to the high level, and the power supply voltage GVSS is supplied to the node n3 via the tenth transistor T10. At this time, since the power supply voltage VGL is supplied to the node n2 as described above, the potential at one end on the node n2 side of the first capacitive element Ca is VGL, and the potential at the other end on the node n3 side is GVSS. A potential difference is generated between the terminals of the first capacitive element Ca. After time t0 ', the set signal SET becomes a low level and the tenth transistor T10 is turned off, so that the potential difference is held between the terminals of the first capacitive element Ca. Here, the potential difference between VGL and GVSS is α (= VGL−GVSS).

[Time t1-t2]
When the potential of the input signal IN changes from the low level voltage VGL to the high level voltage VGH in the period of time t1-t2, the third transistor T3 and the fourth transistor T4 are turned on. At this time, since the second clock signal CK2 is a low level voltage, the seventh transistor T7 is in an OFF state. Accordingly, the potential of the node n1 becomes low level when the low level power supply voltage VGL is supplied through the fourth transistor T4, and the second transistor T2 and the ninth transistor T9 are turned off. Further, the potential of the node n4 is supplied with the high level power supply voltage VGH through the third transistor T3 and becomes high level, and the sixth transistor T6 is turned on.

  The fifth transistor T5 and the sixth transistor T6 form an inverter circuit. When the sixth transistor T6 is on, the low level voltage VGL is output to the node n1. As a result, the second transistor T2 is turned off. Further, since the potential of the node n4 is high level, the potential of the node n2 becomes high level through the eighth transistor T8. The potential of the node n3 is lower than that of the node n2 by the potential difference α held in the first capacitor element Ca. However, since the potential of the node n3 at this time is set to be higher than the low level, and the first clock signal CK1 is at the low level, the first transistor T1 is turned on. The low level of the first clock signal CK1 is output as the output signal OUT.

[Time t2-t3]
In the period from time t2 to time t3, the potential of the input signal IN changes from the high level voltage VGH to the low level voltage VGL, and at the same time, the potential of the first clock signal CK1 is inverted from the low level voltage VGL to the high level voltage VGH. When the potential of the input signal IN becomes low level, the third transistor T3 is turned off, and the node n4 enters a floating state in which no voltage is supplied. As a result, the node n3 receives the influence that the potential of the first clock signal CK1 is inverted to the high level via the first transistor T1, and becomes a potential (+ x) higher than the high level voltage VGH. This is because the gate portion of the first transistor T1 has a channel capacitance, and therefore, when the gate, that is, the node n3 is in a floating state, and the first transistor T1 is in an on state, the potential fluctuation of the drain and source of the first transistor T1 occurs. This is because the potential of the node n3 varies accordingly. In this way, a phenomenon in which the potential of the gate in the floating state varies under the influence of the potential variation in the connected transistor is referred to as a bootstrap, and the node at this time is referred to as a bootstrap node.

  When the node n3 becomes a potential (+ x) higher than the high level voltage VGH, the first transistor T1 is sufficiently turned on, and the high level voltage VGH that is the potential of the first clock signal CK1 is output to the output terminal OUT. Further, the node n2 is affected by the node n3 via the first capacitive element Ca, and becomes a potential higher than the node n3 by the potential difference α.

  FIG. 5 is a diagram illustrating the potential of each node in the period from time t2 to time t3 of the shift register of the display device according to the embodiment. At time t2-t3, the low level voltage VGL is supplied to the node n1 from the inverter circuit configured by the fifth transistor T5 and the sixth transistor T6. The gate-source voltage (Vgs) of the second transistor T2 constituting the output circuit is 0V.

FIG. 6 is a diagram comparing the Vgs-Ids characteristics of an nMOS enhanced transistor and a depletion transistor. As shown in FIG. 6, in the enhancement type, when the gate-source potential difference is 0V, almost no current flows between the source and drain, but in the depletion type, when the gate-source potential difference is 0V, Current flows between the drains. Thus, when the second transistor T2 is a depletion type, an off current flows. However, in the shift register of this embodiment, since this period is shorter than the entire driving period, there is substantially no problem.

[After time t3]
At time t3, the potential of the first clock signal CK1 becomes the low level voltage VGL, and the output signal OUT becomes the low level voltage VGL. Further, the potential of the second clock signal CK2 becomes the high level voltage VGH. When the potential of the second clock signal CK2 becomes high level, the seventh transistor T7 is turned on. At this time, since the third transistor T3 is in the off state, the potential of the node n4 becomes the low level voltage VGL through the seventh transistor T7.

  When the potential of the node n4 becomes VGL, the high level voltage VGH is supplied to the node n1 from the inverter circuit composed of the fifth transistor T5 and the sixth transistor T6, and the second transistor T2 and the ninth transistor T9 are turned on. Further, the low-level voltage VGL is supplied to the node n2 from the node n4, and the node n3 becomes a potential lower than the VGL that is the potential of the node n2 by the potential difference α stored in the first capacitor element Ca.

  FIG. 7 is a diagram illustrating the potential of each node after time t3 (before time t1) of the shift register of the display device according to the embodiment. The second transistor T2 constituting the output circuit is turned on to supply the low level voltage VGL to the output terminal OUT. At this time, the gate-source voltage (Vgs) of the first transistor T1 is −α due to the presence of the first capacitive element Ca.

  For this reason, as shown in FIG. 6, the gate-source voltage (Vgs) is set to −α, which is a value smaller than 0V, and therefore the off-state current can be kept small even if the first transistor T1 is a depletion type.

  In a period after time t3, the first clock signal CK1 and the second clock signal CK2 change between the high level and the low level at the respective timings before the next input IN is input. VGL is always output. This is because the first transistor T1 is off and the potentials of the node n4 and the node n1 corresponding to the drain and source of the seventh transistor T7 are equal to VGL, so that the potential of the internal node of the shift register SR does not change. is there.

  In this embodiment, an nMOS transistor is used as a shift register, and a drive circuit that transmits a start pulse signal STP in which a convex pulse is directed upward has been described. However, the present invention is not limited to this. For example, as shown in FIG. 8, a shift register and a buffer may be configured using pMOS transistors, and a drive circuit that transmits a start pulse signal STP in which a convex pulse is directed downward may be used. In this case, the voltage of the power supply GVDD that supplies a voltage to the node n3 via the tenth transistor T10 in order to give a potential difference between both ends of the capacitive element Ca is applied to the node n2 at the timing when the tenth transistor T10 is turned on by the set signal SET. Set higher than the supplied voltage. In this case, the same effect as described above can be obtained.

  In this embodiment, the case where the driving circuit of the present invention is applied to a liquid crystal display device has been described as an example. However, the driving of the present invention is applied to other display devices such as a display device using an organic EL. It goes without saying that the circuit can be applied.

  The output circuit SROC shown in FIG. 3 can be expressed as follows.

(1) An output circuit SROC provided in a shift register SR that outputs an output signal OUT obtained by shifting the phase of an input signal IN.
A first transistor having a first electrode to which a clock signal for driving the shift register SR is input, a control electrode, and a second electrode for outputting an output signal OUT;
A second transistor having a first electrode connected to the second electrode of the first transistor and having a control electrode and a second electrode to which a first power supply voltage is applied;
A capacitive element having one end connected to the control electrode of the first transistor and a voltage applied to the other end for controlling the on / off of the first transistor;
A first electrode connected to the control electrode of the first transistor, and a tenth transistor having a control electrode and a second electrode to which a second power supply voltage is applied.

(2) When the second power supply voltage is supplied to the control electrode of the first transistor via the tenth transistor, a potential difference is generated between the second power supply voltage and the voltage applied to the other end of the capacitive element. The output circuit according to (1).

(3) When the shift register is configured by an nMOS transistor and the shift register is not selected, the gate-source voltage of the first transistor is smaller than 0. The output of (2) circuit.

  As described above, according to the present embodiment, the signal line for supplying a signal to the gate terminal of the transistor T1 constituting the output circuit of the shift register is connected via the capacitive element, and a predetermined line is connected to the gate terminal. Since a circuit for supplying a potential is provided, even when a depletion type transistor is used, off-leakage current flowing in the output circuit can be reduced and power consumption can be reduced.

  Note that the shift register is not limited to the one shown in FIG. 3 and may have any configuration as long as the phase of the input signal can be shifted.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  T1 ... transistor, T2 ... transistor, T10 ... transistor, Ca ... capacitance element, GVSS ... power supply voltage, VGLL ... voltage, VGL ... low level power supply voltage, VGH ... high level power supply voltage, SR ... shift register, CK ... clock signal, DESCRIPTION OF SYMBOLS 10 ... Transparent substrate, 11 ... Pixel part, 12 ... Switching element, 13 ... Pixel electrode, 14 ... Liquid crystal capacity, 15 ... Auxiliary capacity, 21, 31 ... Drive circuit, 22 ... Vertical shift register, 31 ... Signal line drive circuit, 32 ... Horizontal shift register, 36 ... Clock line, 41 ... Clock terminal, 42 ... Clock terminal, 43 ... Input terminal, 44 ... Output terminal, 45 ... Power electrode, 46 ... Power electrode, 47 ... Set terminal, 48 ... Power electrode .

Claims (5)

A plurality of display pixels arranged in a matrix;
A plurality of drive lines extending along rows and columns in which the plurality of display pixels are arranged;
And at least one drive circuit that outputs a drive signal to the plurality of drive lines,
The drive circuit is
A plurality of shift registers that shift the phase of the input signal and output it as drive signals;
An output circuit provided in each of the shift registers,
The output circuit is
At least one transistor forming the drive signal;
A capacitive element having one end connected to the control electrode of the transistor and a voltage applied to the other end for controlling the on / off of the transistor;
And a control circuit that controls whether a predetermined voltage is applied to the control electrode of the transistor or the control electrode is floated.   The display device according to claim 1, wherein the predetermined voltage is a value that causes the transistor to conduct when supplied to a control electrode of the transistor. Each transistor constituting the shift register and the output circuit is an nMOS transistor,
The display device according to claim 2, wherein the control circuit controls a voltage applied to the control electrode to be lower than a voltage applied to the other end of the capacitive element. Each transistor constituting the shift register and the output circuit is a pMOS transistor,
The display device according to claim 2, wherein the control circuit controls a voltage applied to the control electrode to be higher than a voltage applied to the other end of the capacitive element.   The drive circuit provided in the display device according to claim 1.

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