JP2010238323A - Shift register and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption of a shift register, and also to stabilize the operation. <P>SOLUTION: By transistors T13-T16, an inverter INV is constituted, in which the potential Va of a node A is inverted to a potential Vb of a node B. When an input signal IN(k) of High level is supplied from a shift circuit of a preceding stage, the potential Va of the node A becomes High level and the transistor T13 is turned on to make the potential Vb of the node B Low level. A current flows into an anode line La of voltage VLW from a line of voltage VHI through the transistors T14, T15, T13. A voltage between a second terminal P2 to which the voltage VHI is applied, and the node B is divided by the transistors T14, T15 and a bias voltage of each transistor is divided. A through-current flowing into the inverter INV is reduced by increase of a resistance between the second terminal P2 and the node B, and the power consumption is reduced, and also a shift of threshold voltages of the transistors T14, T15 is suppressed to stabilize the operation of a shift circuit 21_k. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a shift register and an electronic apparatus including the shift register.

  As an electronic device, a display device has been developed in which an organic EL element or LCD is actively driven and displayed by a gate driver shift register using a TFT (for example, see Patent Document 1).

  Specifically, the active drive type display device includes a gate driver that selects a pixel circuit that switches each pixel arranged in each row, and a shift register circuit is usually used as the gate driver.

  This shift register circuit includes, for example, a shift circuit including an inverter INV as shown in FIG. 10 in each stage, and is configured by connecting a plurality of shift circuits in series.

  The inverter INV is composed of transistors T51 and T52. The transistors T51 and T52 are polysilicon or amorphous silicon thin film transistors (TFTs) constituted by n-channel FETs (Field Effect Transistors).

  The inverter INV inverts the potential of the node A and sets the inverted potential as the potential of the node B.

Japanese Patent Laid-Open No. 2001-052494 (5th page, FIGS. 4 and 5)

  However, in the conventional shift circuit, since the transistors T51 and T52 are constituted by TFTs, the transistors T51 and T52 are relatively large in the input period and the output period in which the Hi-level input signal is supplied to the inverter INV. A bias voltage is applied.

  For this reason, a large amount of current flows as a through current from the power supply of the voltage VHI to the power supply of the voltage VLW via the transistors T51 and T52. For this reason, power consumption increases.

  Further, it is known that the transistors T51 and T52 are deteriorated with time due to voltage application between the gate and the source, and the threshold voltage gradually increases. It is also known that when an excessive current flows between the drain and source, the deterioration with time is promoted.

  Here, when the transistor T51 is deteriorated with time and the threshold voltage is increased, the voltage of the node B that should be originally at the Hi level in the non-selection period is decreased, and the operation of the circuit connected to the inverter INV becomes unstable. End up.

  The present invention has been made in view of such a conventional problem, and an object of the present invention is to provide a shift register and an electronic apparatus that can reduce power consumption and stabilize operation.

In order to achieve this object, a shift register according to the first aspect of the present invention provides:
A multi-stage shift register comprising a plurality of cascaded shift circuits,
Each of the shift circuits is
An input terminal to which the output signal of the previous stage is supplied as an input signal, a reset terminal to which the output signal of the next stage is supplied as a reset signal, and a first node, and the input signal is supplied to the input terminal An input circuit for setting the potential of the first node to a potential according to the level of the input signal when
A second node; a first terminal; and a second terminal, to which the potential of the first node is supplied, and the potential of the second node is set to the potential of the first node. An inverter circuit having an inverted potential;
An output terminal for outputting the output signal; and a third terminal to which a first clock signal is supplied, and the potential of the first node and the potential of the second node are supplied, An output circuit for setting the potential of the output signal to a potential based on the first clock signal,
The inverter circuit is
A current path is connected between the first terminal and the second node, and a potential of the first node is supplied to a control terminal, and one end of the current path is connected to the second node A second transistor connected to the node, and one end of a current path connected to the other end of the current path of the second transistor, and the other end of the current path connected to the second terminal or the third terminal. And a third transistor connected to either one of the transistors.

  The control terminal of the second transistor is connected to the other end of the current path of the second transistor, and the control terminal of the third transistor is connected to the other end of the current path of the third transistor. Good.

  In the inverter circuit, one end of a current path is connected to the second node, the other end of the current path is connected to the second terminal, the reset signal is supplied to a control terminal, and the second circuit A fourth transistor for controlling the potential of the node may be provided.

  The first terminal may be set to a constant reference potential, and a constant voltage having a potential higher than the reference potential may be supplied to the second terminal.

  A second clock signal having a phase opposite to that of the first clock signal may be supplied to the second terminal.

An electronic device according to a second aspect of the present invention is:
A plurality of pixel circuits arranged in a matrix with light emitting elements;
A row selection driver that includes the shift register described above, supplies an output signal of each shift circuit included in the shift register as a row selection signal for selecting a row for each row, and selects the plurality of pixel circuits for each row. It is characterized by having.

  According to the present invention, in the shift register, power consumption can be reduced and operation can be stabilized.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the structure of the display apparatus which concerns on the 1st Embodiment of this invention, (a) is a block diagram which shows the whole structure of a display apparatus, (b) is a circuit which shows the structure of each pixel circuit. FIG. It is a figure which shows the structure of the shift register in the gate driver shown in FIG. FIG. 3 is a circuit diagram showing a configuration of each shift circuit shown in FIG. 2. 3 is a timing chart for explaining operations of the shift circuit and the shift register according to the first embodiment. It is a circuit diagram which shows the shift circuit which concerns on the 2nd Embodiment of this invention. FIG. 6 is a diagram illustrating a configuration of a shift register including the shift circuit illustrated in FIG. 5. 7 is a timing chart for explaining operations of the shift circuit shown in FIG. 5 and the shift register shown in FIG. 6. It is a circuit diagram which shows the modification of the shift circuit in 2nd Embodiment. FIG. 9 is a timing chart for explaining operations of the shift circuit shown in FIG. 8 and a shift register including the shift circuit. It is a circuit diagram which shows the conventional inverter.

  Hereinafter, electronic devices according to embodiments of the present invention will be described with reference to the drawings. In the present embodiment, the electronic apparatus is described as a display device having a plurality of pixels and each pixel including an organic electroluminescence element (hereinafter abbreviated as “organic EL element”) as a light emitting element.

<First Embodiment>
FIG. 1 shows the configuration of the display device according to the first embodiment of the present invention.
As shown in FIG. 1A, the display device 1 according to this embodiment includes a plurality of pixel circuits 11 (i, j) (i = 1 to m, j = 1 to n, m) in n rows and m columns. , N are each a natural number), a gate driver (row selection driver) 12, an anode driver 13, a data driver 14, and a controller 15.

  The pixel circuit 11 (i, j) corresponds to each pixel of the image and is arranged in a matrix. As shown in FIG. 1B, the pixel circuit 11 (i, j) includes an organic EL element OLED 101, transistors T1 and T2, and a capacitor C1.

  The capacitor C1 is a capacitor provided between the gate and source of the transistor T2.

  The organic EL element OLED 101 is a display element having a structure in which a pixel electrode (anode electrode), an organic EL layer composed of one or a plurality of carrier transport layers, and a counter electrode are stacked, and the counter electrode (cathode electrode) has a cathode potential. Vcath is applied.

  The transistors T1 and T2 are TFTs formed of polysilicon or amorphous silicon constituted by n-channel FETs (Field Effect Transistors), and have a drain, a source and a gate, and between the drain and the source. Is provided with a semiconductor layer, and when a predetermined bias voltage is applied between the drain and the source, and when a voltage higher than the threshold voltage is applied to the gate, a channel is formed in the semiconductor layer. This is the current path between the sources.

  The transistor T1 is a transistor for applying a gradation signal Vdata indicating the gradation of the image data Data to one end of the capacitor C1. The source of the transistor T1 of each pixel circuit 11 (i, j) is connected to the gate of the transistor T2 and one end of the capacitor C1.

  The drains of the transistors T1 of the pixel circuits 11 (i, 1),..., 11 (i, n) are connected to the i-th data line Ldi. The gates of the respective transistors T1 of the pixel circuits 11 (1, j),..., 11 (m, j) are connected to the gate line Lgj of the j-th row.

  When high level signals are sequentially output to the gate lines Lg1,..., Lgn, the respective transistors T1 of the pixel circuits 11 (1, j),. Then, the gradation signal Vdata input to each of the data lines Ld1,..., Ldm is output to the gate of the transistor T2 and one end of the capacitor C1.

  The transistor T2 is a transistor that supplies current to the organic EL element OLED101 while controlling the amount of current based on the gradation signal Vdata. The gate of the transistor T2 is connected to the source of the transistor T1 and one end of the capacitor C1. Connected to the anode line Laj, the source is connected to the other end of the capacitor C1 and the anode of the organic EL element OLED101.

  The gate driver 12 is a driver for selecting the pixel circuit 11 (i, j) for each row. The gate driver 12 receives the voltages VHI and VLW (VHI> VLW) from the controller 15 and is supplied with the start signal St and the clock signals CK1, CK2 and end signals, and starts its operation.

  The gate driver 12 is supplied with the start signal St and starts operating, and sequentially outputs the output signals OUT (1) to (n) to the gate lines Lg1 to Lgn according to the clock signals CK1 and CK2.

  In this way, the gate driver 12 selects the pixel circuits 11 (1, 1) to 11 (m, 1),..., 11 (1, n) to 11 (m, n).

  The gate driver 12 has a shift register as shown in FIG. Note that the gate driver 12 may be provided with a buffer at the output end of the shift register. The shift register starts to operate in response to the start signal St supplied from the controller 15, transfers the start signal St in synchronization with the clock signals CK1 and CK2, and sequentially outputs the output signals OUT (1) to OUT (n). To do.

  The shift register includes first to n-th shift circuits 21_1 to 21_n, and the shift circuits 21_1 to 21_n are connected in series.

  The shift circuits 21_1 to 21_n are supplied with the input signal IN (including the start signal St) and the clock signal CK1 or CK2, shift the supplied input signal IN according to the clock signal CK1 or CK2, and output the shifted signal as an output signal. It is output as OUT (k) (k = 1 to n).

  As shown in FIG. 3, the shift circuit 21_k (k = 1 to n) functions as an input terminal Pin, an output terminal Pout, a reset terminal Prest, a first terminal P1 that functions as a voltage terminal, and a voltage terminal. And a third terminal P3 functioning as a clock terminal.

  The input terminal Pin is a terminal to which an input signal IN (k) is supplied. The start signal St is supplied as the input signal IN (1) from the controller 15 to the input terminal Pin of the shift circuit 21_1.

  The output terminal Pout is a terminal that outputs an output signal OUT (k), and is connected to the gate line Lgk. The input terminals Pin of the shift circuits 21_2 to 21_n are connected to the output terminals Pout of the preceding shift circuits 21_1 to 21_ (n−1), respectively.

  The reset terminal Prst is a terminal to which a reset signal RST (k) is supplied. The reset terminals Prst of the shift circuits 21_1 to 21_ (n-1) are respectively connected to the output terminals Pout of the shift circuits 21_2 to 21_n of the next stage, and the output signals OUT (2) to OUT (n) are reset signals RST ( 1) to RST (n-1). Further, the end signal is supplied from the controller 15 to the shift circuit 21_n.

  The third terminal P3 is a terminal to which a clock signal (first clock signal) CK1 or CK2 is supplied. The third terminal P3 of the odd-numbered shift circuit 21_k is supplied from the controller 15 to the clock signal CK1. Is supplied.

  The clock signal CK2 is supplied from the controller 15 to the third clock terminal P3 of the shift circuit 21_ (k + 1) which is an even number stage.

  The second terminal P2 is a terminal to which a voltage VHI is applied, and the first terminal P1 is a terminal to which a voltage VLW as a reference voltage is applied.

  The shift circuit 21_k includes transistors T11 to T18. The transistors T11 to T18 are transistors configured by n-channel FETs.

  The transistors T11 to T18 may be single crystal silicon transistors, or may be configured by polysilicon TFTs or amorphous silicon TFTs (a-TFTs) in order to be integrated with the pixel circuit 11 (i, j).

  The transistors T11 to T18 have a drain, a source, and a gate, a semiconductor layer is provided between the drain and the source, a predetermined bias voltage is applied between the drain and the source, and a voltage larger than the threshold voltage is applied to the gate. When applied, a channel is formed in the semiconductor layer, and this channel becomes a current path between the drain and the source.

  The transistor T11 is a transistor for determining the potential Va of the node A in accordance with the signal level of the input signal IN (k) supplied to the input terminal Pin. The gate and drain of the transistor T11 are connected to the input terminal Pin. The node A is a connection point connected to the source of the transistor T11 as a signal output terminal.

  The transistor T12 is a transistor for resetting the shift circuit 21_k with the high level reset signal RST (k) supplied to the reset terminal Prst.

  The gate of the transistor T12 is connected to the reset terminal Prst, the drain is connected to the source of the transistor T11 and the node A, and the source is connected to the first terminal P1. Transistors T11 and T12 correspond to an input circuit.

  The transistors T13 to T16 are transistors that constitute an inverter INV that inverts the potential of the node A. The inverter INV corresponds to an inverter circuit.

  The transistor T13 is a transistor for controlling the potential Vb of the node B in accordance with the potential Va of the node A. The gate of the transistor T13 is connected to the node A, the drain as the current upstream end is connected to the node B, and the source as the current downstream end is connected to the first terminal P1. Node B is a connection point between the source of the transistor T15 and the drain of the transistor T13.

  The transistors T14 and T15 are semiconductor elements that are diode-connected and function as resistors, and the drain and gate of the transistor T14 are connected to the second terminal P2. The transistor T14 is supplied with a voltage VHI and supplies current to the transistors T15 and T13 while limiting the amount of current.

  The gate and drain of the transistor T15 are connected to the source of the transistor T14, and the source is connected to the node B. The transistor T15 is a transistor that is connected in series with the transistor T14, the source serving as the current downstream end is connected to the node B, and divides the voltage between the second terminal P2 and the node B.

  Thus, since the diode-connected transistors T14 and T15 are connected in series between the second terminal P2 to which the voltage VHI is applied and the node B, the bias voltage of each of the transistors T14 and 15 is divided ( Stress voltage is distributed). As a result, the resistance value between the second terminal P2 and the node B increases compared to the conventional configuration, and the current value of the through current decreases compared to the conventional configuration.

  The transistor T16 is a transistor for suppressing a decrease in the rising speed of the potential Vb of the node B. The drain of the transistor T16 is connected to the drain (and gate) of the transistor T14 and to the second terminal P2, and the source is connected to the node B so that the transistor T16 is connected in parallel with the transistors T14 and T15. The

  The gate of the transistor T16 is connected to the reset terminal Prst, and the transistor T16 controls the potential of the node B in accordance with the signal level of the reset signal RST (k).

  Since the transistor T16 operates with a high level reset signal RST (k), the transistor T16 receives voltage stress (gate-source voltage) only transiently when the reset signal RST (k) rises. It is an element with relatively little deterioration.

  By the inverter INV constituted by the transistors T13 to T16, the potential Va of the node A and the potential Vb of the node B are complementarily switched to High (on level) and Low (off level), and if one of them is High, The other becomes Low.

  The transistor sizes of the transistors T13 to T16 may be set to the same value when the channel length is the same value. On the other hand, in the conventional inverter INV shown in FIG. 10, there are two transistors T51 and T52 connected between the voltage VHI and the voltage VLW. The transistor sizes of T51 and T52 have to be the same channel length, and the channel width needs to be about 1: 3, for example.

  However, in the inverter INV shown in FIG. 3, since the transistor T15 is interposed, even if the transistor size of the transistor T13 is made as small as T14 and T15, the potential Vb of the node B can be sufficiently reduced. .

  Further, since the rise of the voltage at the node B is accelerated by the presence of T16 as compared with the conventional configuration including the diode-connected transistor T51, the transistor sizes of the transistors T14 and T15 are made smaller than the transistor size of the T51. be able to. As described above, although two transistors are added to the conventional configuration, the size of each transistor can be made relatively small, and an increase in circuit area can be suppressed.

  The transistor T17 is supplied with the clock signal CK1 to the drain and is turned on / off according to the potential Va of the node A. When the transistor T17 is turned on, the transistor T17 outputs the output signal OUT (k) as the shift signal in synchronization with the clock signal CK1. It is a transistor.

  The transistor T17 has a gate connected to the node A, a drain connected to the third terminal P3, and a source connected to the output terminal Pout. A capacitor Cx1 for providing a bootstrap effect is connected between the gate and source of the transistor T17.

  The transistor T18 is turned on / off according to the potential Vb of the node B, and is turned on during a non-selection period of the pixel circuit 11 (i, k) in the k-th row, and the output signal OUT (k) is fixed to the voltage VLW as a reference voltage. This is a transistor for stabilizing the output signal OUT (k).

  The gate of the transistor T18 is connected to the node B, the drain is connected to the source of the transistor T17 and the output terminal Pout, and the source is connected to the first terminal P1. Transistors T17 and T18 correspond to an output circuit.

  1A and 1B, the anode driver 13 outputs signals Vsource (1) to Vsource (n) of the voltage VL or VH to the anode lines La (1) to La (n), respectively. It is a driver. The anode driver 13 is connected to the drain of the transistor T3 of each pixel circuit 11 (i, j) via the anode line Laj (j = 1 to n).

  The anode driver 13 starts to operate in response to the start signal St supplied from the controller 15 and operates according to the clock signal CK1 supplied from the controller 15.

  Then, the anode driver 13 outputs voltage signals Vsource (1) to Vsource (n) of the voltage VL or VH. The voltage VL is a voltage for bringing the organic EL element OLED 101 of each pixel circuit 11 (i, j) into a non-light emitting state during a writing process or the like.

  In the present embodiment, the cathode voltage Vcath of the organic EL element OLED101 is set to 0V, and the voltage VL is set to 0V or a potential lower than 0V. The voltage VH is a voltage for setting the organic EL element OLED 101 of each pixel circuit 11 (i, j) to a light emitting state, and is set to + 15V, for example.

  The data driver 14 is a driver that writes a gradation signal Vdata of a display signal based on the image data Data supplied to each capacitor C1 of the pixel circuit 11 (i, j).

  The data driver 14 is supplied with image data Data from the controller 15 and generates a gradation signal Vdata for each row based on the image data Data.

  The data driver 14 sends the generated gradation signal Vdata to the pixel circuits 11 (1, j) to 11 (m, j) in the j-th row selected by the gate driver 12 via the data lines Ld1 to Ldm, respectively. Supply.

  The controller 15 controls the gate driver 12 and the data driver 14, and includes a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like (all not shown).

  The controller 15 outputs the start signal St for starting the operation in the state where the clock signal CK1 is output to the odd-numbered stages of the shift circuits 21_1 to 21_n and the clock signal CK2 is output to the even-numbered stages. To supply. In this way, the controller 15 causes the gate driver 12 to start operation.

  Further, the controller 15 supplies the gate driver 12 with an end signal as a reset signal RST (n) of the last-stage shift circuit 21_n.

  The controller 15 supplies the data driver 14 with a start signal St, image data Data, a clock signal CK1, and the like.

  Next, the operation of the display device 1 according to this embodiment will be described. FIG. 4 is a timing chart for explaining operations of the shift circuit 21_k and the shift register in the gate driver 12. Note that Va, Vb, and Vc indicate the potentials of the nodes A, B, and C of the first-stage shift circuit 21_1.

  As shown in FIG. 4, the controller 15 supplies the gate driver 12 with clock signals CK <b> 1 and CK <b> 2 having a phase difference of 180 ° and a high-level start signal St.

  At time t10 when the clock signal CK1 becomes low level, the high-level start signal St is supplied as the input signal IN (1) to the input terminal Pin of the first-stage shift circuit 21_1.

  The period during which the high-level start signal St is supplied is defined as the input period Tin, and the transistor T11 of the shift circuit 21_1 is turned on in the input period Tin.

  When the transistor T11 is turned on, the potential Va of the node A becomes a high level, and the transistor T13 is also turned on when a high level signal is supplied to the gate.

  When the transistor T13 is turned on, since the transistors T14 and T15 are diode-connected, the current flows from the voltage VHI line to the second terminal P2, the drain-sources of the transistors T14, T15, and T13, the first It flows to the line of the voltage VLW via the terminal P1.

  As the current flows in this way, the potential Vb of the node B becomes the low level in the input period Tin as shown in FIG. 4, and the transistor T18 is turned off.

  However, the transistors T14 and T15 function as resistance elements, and the amount of flowing current is limited by the transistors T14 and T15, and the amount of heat generated by the transistor T13 is also reduced. Further, the voltage applied between the drain and source of the transistors T14 and T15 is (VHI−VLW) / 3, which is reduced as compared with the conventional case.

  As shown in FIG. 4, after the elapse of the input period Tin, in the output period Tout in which the clock signal CK1 becomes High level, the input signal IN (1) becomes Low level and the transistor T11 is turned off.

  Even if the transistor T11 is turned off, the potential Va of the node A is held at a high level because the transistors T17 and T18 are turned off.

  In this output period Tout, when the clock signal CK1 becomes High level, the potential Va of the node A further rises due to the bootstrap effect of the capacitor Cx1, and the transistor T17 is reliably turned on.

  When the transistor T17 is turned on, the shift circuit 21_1 outputs a high level output signal OUT (1) from the output terminal Pout.

  The high level output signal OUT (1) is output to the gate line Lg1 and supplied to the shift circuit 21_2 as the input signal IN (2).

  The shift circuit 21_2 shifts the input signal IN (2) in synchronization with the clock signal CK2, and outputs a high-level output signal OUT (2).

  The high level output signal OUT (2) is supplied to the reset terminal Prst of the shift circuit 21_1 as the high level reset signal RST (1).

  When this high level reset signal RST (1) is supplied, the transistor T12 is turned on. When the transistor 12 is turned on, the potential Va of the node A falls to the low level.

  When the potential Va at the node A falls to the low level, the transistor T13 is turned off, and the potential Vb at the node B becomes the high level.

  When the high level reset signal RST (1) is supplied, the transistor T16 is also turned on.

  Since the transistor T15 is interposed between the second terminal P2 and the first terminal P1, if the transistor T16 is not provided, the rising speed of the potential Vb of the node B is caused by the parasitic capacitance of the transistor T15. Compared to the conventional system, it becomes slower.

  However, the shift circuit 21_1 includes the transistor T16. When the transistor T16 is turned on, the second terminal P2 and the node B are short-circuited, and the delay in the rising speed of the potential Vb is eliminated. The potential Vb immediately becomes High level.

  When the potential Vb of the node B becomes the high level, the transistor T18 is turned on, and the output signal OUT (1) falls to the low level.

  Similarly, the shift circuit 21_k (k = 2 to n) receives the output signal OUT (k−1) output from the shift circuit 21_ (k−1) in synchronization with the clock signals CK1 and CK2, respectively. This input signal IN (k) is shifted as IN (k). Then, the shift circuit 21_k outputs the shifted signal as the output signal OUT (k).

  The gate driver 12 outputs the high level output signal OUT (1) of the shift circuit 21_1 to the gate line Lg1. The transistors T1 of the pixel circuits 11 (1,1) to 11 (m, 1) are turned on by the high level output signal OUT (1).

  During this period, the data driver 14 supplies the gradation signal Vdata to the pixel circuits 11 (1, 1) to 11 (m, 1) selected by the gate driver 12 via the data lines Ld1 to Ldm.

  This gradation signal Vdata is written to each capacitor C1 of the pixel circuits 11 (1,1) to 11 (m, 1) via each transistor T1.

  Similarly, the gate driver 12 sequentially outputs the high level output signals OUT (2) to OUT (n) of the shift circuits 21_2,..., 21_n to the gate lines Lg2,.

  When the high level output signal OUT (1) is sequentially output to the gate lines Lg2,..., Lgn, the pixel circuits 11 (1, 2) to 11 (m, 2),. 1, n) to 11 (m, n) are selected.

  The data driver 14 applies gradation signals Vdata based on the supplied image data to the data lines Ld1 to Ldm, respectively, and the selected pixel circuits 11 (1,2) to 11 (m, 2),. .., 11 (1, n) to 11 (m, n), the gradation signal Vdata is written to each capacitor C1.

  When the writing operation is completed in this way, the controller 15 controls the light emitting operation.

  The anode driver 13 outputs signals Vsource (1) to Vsource (n) having a voltage VH (= + 15V) to the anode lines La (1) to La (n).

  When the voltage of the anode lines La (1) to La (n) becomes VH, the transistor T2 of each pixel circuit 11 (i, j) uses the voltage held by each capacitor C1 as the gate voltage Vgs, and the gate voltage Vgs. A corresponding current is supplied to the organic EL element OLED101.

  And each organic EL element OLED101 light-emits with the brightness | luminance corresponding to the electric current value of this electric current, when this electric current flows.

  As described above, according to the present embodiment, the transistor T15 is connected between the transistor T14 of the inverter INV and the node B, and the bias voltage between the voltage VHI and the voltage VLW is divided.

  Accordingly, since the bias voltage of each of the transistors T13 to T15 is dispersed, the bias voltage applied to each of the transistors T14 and T15 in the input period Tin and the output period Tout is almost halved compared to the conventional configuration. And the current can be greatly reduced.

  For this reason, occurrence of a threshold Vth shift due to deterioration of the transistors T14 and T15 can be suppressed.

  Further, by connecting the transistor T16 in parallel with the transistors T14 and T15, a delay in the rising speed of the potential Vb of the node B due to the insertion of the transistor T15 can be prevented.

<Second Embodiment>
Next, the configuration of the shift circuit according to the second embodiment of the present invention is shown in FIG.
In the first embodiment, in the shift circuit 21_k, the voltage VHI having a constant voltage value is applied to the second terminal P2 connected to the drain of the transistor T14. However, even if the voltage VHI is not applied to the drain of the transistor T14 of the inverter INV during the output period Tout shown in FIG. 4, the shift circuit 21_k operates substantially in the same manner.

  Therefore, in the second embodiment, as shown in FIG. 5, a clock signal (positive phase clock signal (first phase) applied to the second terminal P2 instead of the voltage VHI is applied to the third terminal P3. The clock signal (second clock signal) CK− of the opposite phase is supplied to the clock signal CK +).

  In this case, the gate driver 12 supplies clock signals CK1 and CK2 to all the shift circuits 21_1 to 21_n, as shown in FIG. Clock signals CK1 and CK2 are supplied to the odd-numbered shift circuit 21_k as the positive-phase and reverse-phase clock signals CK + and CK-, respectively, and the clock signals CK1 and CK2 are supplied to the even-numbered shift circuit 21_k. These are supplied as anti-phase and positive-phase clock signals CK− and CK +, respectively.

  Here, the operations of the shift circuit 21_k and the shift register in the present embodiment are the same as those shown in FIG. 4 except for Vc which is the potential of the node C, as shown in FIG.

  Since the clock signal CK− having the opposite phase is applied to the second terminal P2, the potential Vc of the node C changes in response to the clock signal CK2 in the first-stage shift circuit 21_1.

  By doing so, since the voltage VHI is not used, the wiring of the voltage VHI line becomes unnecessary, and the circuit area can be reduced. Further, the bias voltage applied to the transistors T14 and T15 can be reduced, the period during which the bias voltage is applied to the transistors T14 and T15 is limited to the input period Tin, and the transistors T14 and T15 are biased during the output period Tout. Since no voltage is applied, the period during which the bias voltage is applied can be shortened, and deterioration of the transistors T14 and T15 can be further suppressed.

  Further, by supplying the opposite phase clock signal CK− to the second terminal P2, no current is supplied to the inverter INV in the output period Tout, so that the current consumption can be reduced.

  Next, a modification of this embodiment will be described. In the configuration shown in FIG. 5, the drain of the transistor T16 and the drain of the transistor T14 are connected to the second terminal P2. However, as shown in FIG. 8, the second terminal P2 has the drain of the transistor T16. Only the drain may be connected, and the drain of the transistor T13 and the drain of the transistor T17 may be connected to the third terminal P3.

  Here, the operations of the shift circuit 21_k and the shift register in the present embodiment are the same as those shown in FIG. 4 except for Vb and Vc which are the potentials of the nodes B and C, as shown in FIG.

  When the start signal St is supplied, the transistor T16 is in an off state, and the transistors T13 and T14 are also in an off state. Therefore, the potential Vb of the node B becomes a low level near the voltage VLW in the input period Tin, and in the output period Tout. A high level clock signal is applied to the third terminal P3, and its Low level rises. The potential Vc of the node C changes according to the change of the potential Vb of the node B.

  Also in this case, since the voltage VHI is not used, the wiring of the voltage VHI line becomes unnecessary, and the circuit area can be reduced. Further, the bias voltage applied to the transistors T14 and T15 can be reduced, and the period during which the bias voltage is applied to the transistors T14 and T15 is limited to the output period Tout, and the transistors T14 and T15 are biased during the input period Tin. Since no voltage is applied, the period during which the bias voltage is applied can be shortened, and deterioration of the transistors T14 and T15 can be further suppressed.

  In the above-described embodiment, the electronic device is described as a display device including an organic EL element. However, the electronic device is not limited to this, and the present embodiment can be used as long as the electronic device includes a light-emitting element. The form is not limited. The electronic device may be a liquid crystal display device including a liquid crystal element, for example.

  DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 11 ... Pixel circuit, 12 ... Gate driver, 13 ... Anode driver, 14 ... Data driver, 15 ... Controller, 21_k (k; 1-n). ..Shift circuit 101 ... Organic EL element OLED, T1, T2, T11 to T18 ... Transistor, C1 ... Capacitor, INV ... Inverter

Claims (6)

A multi-stage shift register comprising a plurality of cascaded shift circuits,
Each of the shift circuits is
An input terminal to which the output signal of the previous stage is supplied as an input signal, a reset terminal to which the output signal of the next stage is supplied as a reset signal, and a first node, and the input signal is supplied to the input terminal An input circuit for setting the potential of the first node to a potential according to the level of the input signal when
A second node; a first terminal; and a second terminal, to which the potential of the first node is supplied, and the potential of the second node is set to the potential of the first node. An inverter circuit having an inverted potential;
An output terminal for outputting the output signal; and a third terminal to which a first clock signal is supplied, and the potential of the first node and the potential of the second node are supplied, An output circuit for setting the potential of the output signal to a potential based on the first clock signal,
The inverter circuit is
A current path is connected between the first terminal and the second node, and a potential of the first node is supplied to a control terminal, and one end of the current path is connected to the second node A second transistor connected to the node, and one end of a current path connected to the other end of the current path of the second transistor, and the other end of the current path connected to the second terminal or the third terminal. A third transistor connected to either one of
A shift register characterized by that.   The control terminal of the second transistor is connected to the other end of the current path of the second transistor, and the control terminal of the third transistor is connected to the other end of the current path of the third transistor. The shift register according to claim 1. In the inverter circuit, one end of a current path is connected to the second node, the other end of the current path is connected to the second terminal, the reset signal is supplied to a control terminal, and the second circuit A fourth transistor for controlling the potential of the node;
The shift register according to claim 1 or 2, wherein   4. The shift register according to claim 3, wherein the first terminal is set to a constant reference potential, and a constant voltage having a potential higher than the reference potential is supplied to the second terminal. .   4. The shift register according to claim 3, wherein a second clock signal having a phase opposite to that of the first clock signal is supplied to the second terminal. 5. A plurality of pixel circuits arranged in a matrix with light emitting elements;
6. The shift register according to claim 1, wherein an output signal of each shift circuit included in the shift register is supplied for each row as a row selection signal for selecting a row, and the plurality of pixels With a row selection driver that selects circuits by row
An electronic device characterized by that.

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