JP2010238323A5 - - Google Patents
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- JP2010238323A5 JP2010238323A5 JP2009087287A JP2009087287A JP2010238323A5 JP 2010238323 A5 JP2010238323 A5 JP 2010238323A5 JP 2009087287 A JP2009087287 A JP 2009087287A JP 2009087287 A JP2009087287 A JP 2009087287A JP 2010238323 A5 JP2010238323 A5 JP 2010238323A5
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Claims (8)
前記各シフト回路は、
前段の出力信号が入力信号として供給される入力端子と、次段の出力信号がリセット信号として供給されるリセット端子と、第１のノードと、を有し、前記入力端子に前記入力信号が供給されたときに前記第１のノードの電位を前記入力信号のレベルに従った電位に設定する入力回路と、
第２のノードと、第１の端子と、第２の端子と、を有し、前記第１のノードの電位が供給され、前記第２のノードの電位を、前記第１のノードの電位を反転した電位とするインバータ回路と、
前記出力信号を出力する出力端子と、第１のクロック信号が供給される第３の端子と、を有し、前記第１のノードの電位と前記第２のノードの電位とが供給され、前記出力信号の電位を、前記第１のクロック信号に基づく電位とする出力回路と、を備え、
前記インバータ回路は、
前記第１の端子と前記第２のノードとの間に電流路が接続され、制御端子に前記第１のノードの電位が供給される第１のトランジスタと、電流路の一端が前記第２のノードに接続される第２のトランジスタと、電流路の一端が前記第２のトランジスタの前記電流路の他端に接続され、電流路の他端が前記第２の端子又は前記第３の端子のいずれか一方に接続される第３のトランジスタと、を備えた、
ことを特徴とするシフトレジスタ。 A multi-stage shift register comprising a plurality of cascaded shift circuits,
Each of the shift circuits is
An input terminal to which the output signal of the previous stage is supplied as an input signal, a reset terminal to which the output signal of the next stage is supplied as a reset signal, and a first node, and the input signal is supplied to the input terminal An input circuit for setting the potential of the first node to a potential according to the level of the input signal when
A second node; a first terminal; and a second terminal, to which the potential of the first node is supplied, and the potential of the second node is set to the potential of the first node. An inverter circuit having an inverted potential;
An output terminal for outputting the output signal; and a third terminal to which a first clock signal is supplied, and the potential of the first node and the potential of the second node are supplied, An output circuit for setting the potential of the output signal to a potential based on the first clock signal,
The inverter circuit is
A current path is connected between the first terminal and the second node, and a potential of the first node is supplied to a control terminal, and one end of the current path is connected to the second node A second transistor connected to the node, and one end of a current path connected to the other end of the current path of the second transistor, and the other end of the current path connected to the second terminal or the third terminal. A third transistor connected to either one of
A shift register characterized by that.
ことを特徴とする請求項２に記載のシフトレジスタ。 In the inverter circuit, one end of a current path is connected to the second node, the other end of the current path is connected to the second terminal, the reset signal is supplied to a control terminal, and the second circuit A fourth transistor for controlling the potential of the node;
The shift register according to claim 2 .
シフトレジスタを含み、当該シフトレジスタに含まれる各シフト回路の出力信号を、行を選択する行選択信号として各行毎に供給し、前記複数の画素回路を行毎に選択する行選択ドライバを備え、
前記シフトレジスタは、縦続接続された複数のシフト回路を有し、
前記各シフト回路は、
前段の出力信号が入力信号として供給される入力端子と、次段の出力信号がリセット信号として供給されるリセット端子と、第１のノードと、を有し、前記入力端子に前記入力信号が供給されたときに前記第１のノードの電位を前記入力信号のレベルに従った電位に設定する入力回路と、
第２のノードと、第１の端子と、第２の端子と、を有し、前記第１のノードの電位が供給され、前記第２のノードの電位を、前記第１のノードの電位を反転した電位とするインバータ回路と、
前記出力信号を出力する出力端子と、第１のクロック信号が供給される第３の端子と、を有し、前記第１のノードの電位と前記第２のノードの電位とが供給され、前記出力信号の電位を、前記第１のクロック信号に基づく電位とする出力回路と、を備え、
前記インバータ回路は、
前記第１の端子と前記第２のノードとの間に電流路が接続され、制御端子に前記第１のノードの電位が供給される第１のトランジスタと、電流路の一端が前記第２のノードに接続される第２のトランジスタと、電流路の一端が前記第２のトランジスタの前記電流路の他端に接続され、電流路の他端が前記第２の端子又は前記第３の端子のいずれか一方に接続される第３のトランジスタと、を備えた、
ことを特徴とする電子機器。 A plurality of pixel circuits arranged in a matrix with light emitting elements;
Includes a shift register, an output signal of each shift circuit included in the shift register, and supplied to each row as a row selection signal for selecting the row, with a row select driver for selecting the plurality of pixel circuits in each row ,
The shift register includes a plurality of shift circuits connected in cascade,
Each of the shift circuits is
An input terminal to which the output signal of the previous stage is supplied as an input signal, a reset terminal to which the output signal of the next stage is supplied as a reset signal, and a first node, and the input signal is supplied to the input terminal An input circuit for setting the potential of the first node to a potential according to the level of the input signal when
A second node; a first terminal; and a second terminal, to which the potential of the first node is supplied, and the potential of the second node is set to the potential of the first node. An inverter circuit having an inverted potential;
An output terminal for outputting the output signal; and a third terminal to which a first clock signal is supplied, and the potential of the first node and the potential of the second node are supplied, An output circuit for setting the potential of the output signal to a potential based on the first clock signal,
The inverter circuit is
A current path is connected between the first terminal and the second node, and a potential of the first node is supplied to a control terminal, and one end of the current path is connected to the second node A second transistor connected to the node, and one end of a current path connected to the other end of the current path of the second transistor, and the other end of the current path connected to the second terminal or the third terminal. A third transistor connected to either one of
An electronic device characterized by that.
ことを特徴とする請求項７に記載の電子機器。The electronic apparatus according to claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009087287A JP2010238323A (en) | 2009-03-31 | 2009-03-31 | Shift register and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009087287A JP2010238323A (en) | 2009-03-31 | 2009-03-31 | Shift register and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2010238323A JP2010238323A (en) | 2010-10-21 |
| JP2010238323A5 true JP2010238323A5 (en) | 2011-11-17 |
Family
ID=43092508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009087287A Pending JP2010238323A (en) | 2009-03-31 | 2009-03-31 | Shift register and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2010238323A (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101911872B1 (en) | 2011-11-18 | 2018-10-26 | 삼성디스플레이 주식회사 | Scan driving device and driving method thereof |
| JP6239918B2 (en) * | 2013-09-27 | 2017-11-29 | 株式会社ジャパンディスプレイ | Gate signal line driving circuit and display device |
| JP2015197543A (en) | 2014-03-31 | 2015-11-09 | ソニー株式会社 | Packaging substrate and electronic apparatus |
| JP2015197544A (en) | 2014-03-31 | 2015-11-09 | ソニー株式会社 | Mounting board and electronic apparatus |
| JP6128046B2 (en) | 2014-03-31 | 2017-05-17 | ソニー株式会社 | Mounting board and electronic equipment |
| CN104485065B (en) | 2014-12-30 | 2017-02-22 | 上海天马有机发光显示技术有限公司 | Shifting register, driving method and gate driving circuit |
| KR20160092584A (en) | 2015-01-27 | 2016-08-05 | 삼성디스플레이 주식회사 | Gate driving circuit |
| KR102555084B1 (en) * | 2015-12-30 | 2023-07-13 | 엘지디스플레이 주식회사 | Module for driving gate and gate in panel |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100752602B1 (en) * | 2001-02-13 | 2007-08-29 | 삼성전자주식회사 | Shift resister and liquid crystal display using the same |
| JP4912023B2 (en) * | 2006-04-25 | 2012-04-04 | 三菱電機株式会社 | Shift register circuit |
| JP5079301B2 (en) * | 2006-10-26 | 2012-11-21 | 三菱電機株式会社 | Shift register circuit and image display apparatus including the same |
| JP2008140489A (en) * | 2006-12-04 | 2008-06-19 | Seiko Epson Corp | Shift register, scanning line drive circuit, data line drive circuit, electro-optical device, and electronic device |
-
2009
- 2009-03-31 JP JP2009087287A patent/JP2010238323A/en active Pending
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