JP2016110684A5

JP2016110684A5 -

Info

Publication number: JP2016110684A5
Application number: JP2015156162A
Authority: JP
Filing date: 2015-08-06
Publication date: 2018-09-06
Anticipated expiration: 2035-08-06

Claims

A shift register circuit composed of a single conductivity type transistor,
A shift register unit having a first output transistor connecting the output terminal and the first power supply;
A first gate control circuit having an output terminal connected to the gate terminal of the first output transistor;
The first gate control circuit includes a timing generation unit and a buffer unit,
The buffer unit is a bootstrap circuit,
An output of the timing generation unit to which an input signal is input is an input of the buffer unit, and an output of the buffer unit is an output of the first gate control circuit.

The buffer unit is at least
A second transistor connecting the output of the buffer unit and the first clock signal;
The shift register circuit according to claim 1, wherein the shift register circuit is a bootstrap circuit including a third transistor that connects a gate terminal of the second transistor and an output of the timing generation unit.

The buffer unit is at least
The second transistor for connecting the output of the buffer unit and the first clock signal;
A third transistor connected between a gate terminal of the second transistor and an output of the timing generator and gate-controlled by a second clock signal;
3. The shift according to claim 2, wherein the shift is a bootstrap circuit that includes a fourth transistor that connects an output of the buffer unit and the first power supply and is gate-controlled by the second clock signal. Register circuit.

The timing generator
A fifth transistor that is gate-controlled by an input of the first gate control circuit and connects the first power supply and the input of the buffer;
The shift register circuit according to claim 3, comprising a first capacitor that connects an input of the buffer unit and the second clock signal.

The timing generator
A sixth transistor that is gate-controlled by an input of the first gate control circuit and connects the first power supply and the input of the buffer;
4. The shift register circuit according to claim 3, comprising: a seventh transistor that connects an input of the buffer unit to a second power supply and has a gate terminal connected to the second power supply. 5.

The shift register unit is
Connects the output terminal of the shift register circuit to the source terminal, and an eighth output transistor connected to a second power source to the drain terminal,
A first clock signal is input to the gate terminal , another input signal different from the input signal is input to the drain terminal, and a ninth transistor having a source terminal connected to the gate terminal of the eighth output transistor; The shift register circuit according to claim 1, further comprising:

A shift register circuit comprising the single conductivity type transistor according to claim 1,
The shift register unit includes a tenth output transistor that connects the output terminal and the first power source;
A second gate control circuit having an output terminal connected to the gate terminal of the tenth output transistor;
The second gate control circuit includes a timing generation unit and a buffer unit;
An output of the timing generation unit to which an input signal is input is an input of the buffer unit, and an output of the buffer unit is an output of the second gate control circuit.

The buffer unit constituting the first gate control circuit is a bootstrap circuit that outputs the first clock signal according to claim 2, and the buffer unit constituting the second gate control circuit is claim 3. The shift register circuit according to claim 7, which is a bootstrap circuit that outputs the second clock signal according to claim 8.

A gate driver in which a plurality of stages of the shift register circuit according to claim 7 are connected,
The output of the shift register circuit at the (n-2) th stage (where n is an integer of 3 or more) is used as the input of the shift register unit at the (n-1) th stage and the first or second gate control circuit,
The output of the first or second gate control circuit at the (n−1) th stage is used as the input to the shift register section at the (n−1) th stage and the shift register section at the nth stage. A gate driver.

The buffer section of the first gate control circuit has at least a second output;
An eleventh transistor connecting the second output of the buffer unit and the first power supply;
A twelfth transistor connecting the second output of the buffer unit and the first output of the buffer unit;
A thirteenth transistor connecting the gate terminal of the twelfth transistor and the output of the (n + 2) th stage shift register;
The eleventh transistor is controlled by the second clock signal;
The shift register circuit according to claim 3, wherein the thirteenth transistor is a bootstrap circuit controlled by a second power supply.

11. A shift register circuit comprising the gate control circuit according to claim 10, wherein the second output terminal is connected to the gate terminal of the first output transistor.

A gate driver in which a plurality of stages of the shift register circuit according to claim 10 are connected,
The output of the shift register circuit of the (n-2) th stage (n is an integer of 3 or more) is used as the input of the shift register unit and the gate control circuit of the (n-1) th stage,
The output of the (n + 2) th stage shift register circuit is used as the input of the (n-1) th stage gate control circuit,
The first output of the (n−1) th stage gate control circuit is used as an input to the (n−1) th stage shift register unit and the nth stage shift register unit,
The gate driver, wherein the second output of the gate control circuit at the (n-1) th stage is used as an input of the shift register unit at the nth stage.

A matrix type display device equipped with the gate driver according to claim 9 or 12,
A display portion in which pixel elements are arranged at intersections of a plurality of gate lines and a plurality of data lines,
Connecting the output of the gate driver to the gate line;
Overlap scanning having a period for simultaneously selecting a plurality of gate lines,
The display device, wherein a selection period of the gate line is controlled by a pulse width of a start signal.

The buffer section of the first gate control circuit has at least a second output;
A twelfth transistor connecting the second output of the buffer unit and the first output of the buffer unit;
A thirteenth transistor connecting the gate terminal of the twelfth transistor and the output of the shift register of the (n + 2) th stage;
The thirteenth transistor is a bootstrap circuit controlled by a second power supply
The shift register circuit according to claim 2.