WO2023240513A1

WO2023240513A1 - Shift register, shift register circuit, display panel, and electronic device

Info

Publication number: WO2023240513A1
Application number: PCT/CN2022/099033
Authority: WO
Inventors: Keitaro Yamashita
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2022-06-15
Filing date: 2022-06-15
Publication date: 2023-12-21

Abstract

Embodiments of this application provide a shift register, a shift register circuit, a display panel, and an electronic device. The shift register includes an input circuit, a bootstrapping circuit, and an output circuit, wherein the input circuit is configured to obtain a first input signal and output a first voltage control signal according to the first input signal, wherein the first voltage control signal is used to adjust a voltage of a first node connecting to the input circuit; the bootstrapping circuit is configured to obtain a second input signal and output a second voltage control signal according to the second input signal, wherein the second voltage control signal is used to adjust the voltage of the first node connecting to the bootstrapping circuit; the output circuit is configured to obtain a third input signal and output an output signal according to the third input signal, wherein the third input signal includes a voltage signal from the first node, and wherein the voltage signal includes: a first voltage and a second voltage, and wherein the second voltage is lower than a low voltage of the first input signal and the low voltage of the first input signal is lower than the first voltage. According to the above-mentioned technical solution, a bias voltage of a terminal of the output circuit may be deep, thereby making output rising and falling time faster, and allowing smaller transistors to maintain a narrower border.

Description

SHIFT REGISTER, SHIFT REGISTER CIRCUIT, DISPLAY PANEL, AND ELECTRONIC DEVICE

TECHNICAL FIELD

Embodiments of the present application relate to the field of displaying technologies, and more specifically, to a shift register, a shift register circuit, a display panel, and an electronic device.

BACKGROUND

An active matrix organic light emitting diode (AMOLED) display is a display technology that is widely used in many applications such as smartphones, tablets, smart-watches, and notebook displays. The AMOLED display generally consists of an active area with a plurality of pixels arranged in an array with rows and columns, and a data driver configured to sequentially provide displaying data to data lines arranged in column directions. Gate driver on array (GOA) is a data driver technology in which data driver circuits are integrated on an array substrate of a display panel. The GOA technology may offer low manufacturing costs for driving circuits and narrow borders.

The data driver circuit utilizing the GOA is also called a GOA circuit or a shift register circuit. The shift register circuit includes several shift registers, and each of the shift registers includes several transistors. There are some shift register circuits that can generate positive pulses or negative pulses. However, the shift registers in these shift register circuits include a plurality of transistors, which is disadvantageous for narrowing the border of the display.

SUMMARY

Embodiments of this application provide a shift register, a shift register circuit, a display panel, and an electronic device. The technical solution could provide a narrow border for a display panel.

According to a first aspect, an embodiment of this application provides a shift register, including an input circuit, a bootstrapping circuit, and an output circuit, wherein the input circuit is configured to obtain a first input signal and output a first voltage control signal according to the first input signal, wherein the first voltage control signal is used to adjust a voltage of a first node connecting to the input circuit; the bootstrapping circuit is configured to obtain a second input signal and output a second voltage control signal according to the second input signal, wherein the second voltage control signal is used to adjust the voltage of the first node connecting to the bootstrapping circuit; the output circuit is configured to obtain a third input signal and output an output signal according to the third input signal, wherein the third input signal includes a voltage signal from the first node, and wherein the voltage signal includes: a first voltage and a second voltage, and wherein the second voltage is lower than a low voltage of the first input signal and the low voltage of the first input signal is lower than the first voltage.

According to the above-mentioned technical solution, the output circuit is deeply biased with the bootstrapping circuit. With the bootstrapping circuit, the input voltage of the output circuit may be pushed down to the second voltage that is lower than the low voltage of the first input signal. The bias voltage of the output circuit may be lower than the second voltage. The absolute value of the bias voltage Vgs is proportional to the output rising and falling time. Therefore, a lower Vgs (i.e., a larger absolute value) may make output rising and falling time faster. Further, according to the fundamental equation given the transistor on resistance (Ron) , when the absolute value of Vgs have got small (small gate bias voltage) , then the transistor channel width should be bigger in order to keep the same Ron value. Therefore, according to the present application, the size of the transistor in the output circuit may be small. Correspondingly, a border of a display panel including the shift register in the first aspect of the present disclosure may be narrow.

By convention, the high level signal of input signals is referred as VGH, and the low level signal of the input signals is referred as VGL, and a threshold voltage which is used to turn on a transistor in the input circuit is referred as Vth. Therefore, a first voltage Vn1 ₁, a second voltage Vn1 ₂, and VGL satisfy: Vn1 ₂<VGL<Vn1 ₃.

For example, Vn1 ₁, Vn2, VGL, and VGH may satisfy:

Vn1 ₁=VGH;

Vn1 ₂= = VGL-Vth- (VGH-VGL) ,

and the bias voltage of output circuit Vgs may be Vgs= 2 (VGL-VGH) -Vth. Therefore, if VGL=-5V, VGH=7V, Vth=-2V, then the Vgs=2 (-5-7) +2= -22V. The bias voltage of the output circuit is much deeper than the low level signal of the input signal, thereby making output rising and falling time faster, and allowing smaller transistors to maintain a narrower border.

In a possible design, the input circuit includes a first transistor, and the first input signal includes a first start pulse input signal and a first control signal, wherein a source terminal of the first transistor is configured to obtain the first start pulse input signal, a gate terminal of the first transistor is configured to obtain the first control signal, and a drain terminal of the first transistor is configured to output the first voltage control signal.

In a possible design, the input circuit includes a first transistor and a second transistor, and the first input signal includes a first start pulse input signal, a first control signal and a fourth control signal, wherein a source terminal of the first transistor is configured to obtain the first start pulse input signal, a gate terminal of the first transistor is configured to obtain the first control signal, a gate terminal of the second transistor is configured to obtain the fourth control signal; a drain terminal of the first transistor is coupled to a source terminal of the second transistor; and a drain terminal of the second transistor is configured to output the first voltage control signal.

According to the above-mentioned technical solution, the input unit includes more than one transistors. Therefore, gate bias voltage stress to each of the transistors may be reduced. For example, if the input circuit only includes one transistor, than the gate bias voltage of the transistor may be 2 (VGH-VGL) +Vth. If VGL=-5V, VGH=7V, then the gate bias voltage of the transistor may be 22V. However, if the input circuit comprises two transistors, e.g., the first transistor and the second transistor, then the gate bias voltage of the first transistor may be VGH- (VGL-Vth) , and the gate bias voltage of the second transistor may be VGL- {VGL-Vth- (VGH-VGL) } . If VGL=-5V, VGH=7V, then the bias voltage of the first transistor may be 10V, and the bias voltage of the second transistor may be 10V. Clearly, the gate bias voltage of the transistor in the input circuit is decreased. Therefore, the design difficulty of the input circuit may be reduced.

In a possible design, the bootstrapping circuit includes a third transistor and a first capacitor, the second input signal includes a second control signal and the voltage signal wherein a first terminal of the first capacitor is coupled to a gate terminal of the third transistor; a second terminal of the first capacitor is coupled to a drain terminal of the third transistor; the gate terminal of the third transistor is configured to obtain the voltage signal; a source terminal of the third transistor is configured to obtain the second control signal.

In a possible design, the second terminal of the first capacitor is configured to output a second start pulse input signal.

In a possible design, wherein the output circuit includes a fourth transistor, and the third input signal further includes a third control signal, wherein a gate terminal of the fourth transistor is configured to obtain the voltage signal, a source terminal of the fourth transistor is configured to obtain the third control signal; and a drain terminal of the fourth transistor is configured to output the output signal.

In a possible design, the shift register further includes a charge-pump circuit, wherein the charge-pump circuit is configured to obtain a fourth input signal and output a third voltage control signal according to the fourth input signal; the third input signal further includes the third voltage control signal, the third voltage control signal includes: a third voltage and a fourth voltage, and wherein the fourth voltage is lower than the low voltage of the first input signal and the low voltage of the first input signal is lower than the third voltage.

The charge-pump unit may generate an extra lower voltage to drive the low-side buffer transistor in the output unit. The output signal of the shift register is periodically discharged to VGL through the transistor. This stabilizes the shift-register function in a variable refresh rate (VRR) , especially in 1Hz which is a super low refresh rate drive.

In some embodiments, the third voltage may be the same as the first voltage, the fourth voltage may be the same as the second voltage.

In some embodiments, the voltage signal further include a fifth voltage which equals to VGL-Vth. The third voltage control signal further includes a sixth voltage which equals to the fifth voltage.

In a possible design, the output circuit includes a fourth transistor and a fifth transistor, and the third input signal further includes a third control signal and a fourth control signal, wherein a drain terminal of the fourth transistor is coupled to a drain terminal of the fifth transistor, a gate terminal of the fourth transistor is configured to obtain the voltage signal; a source terminal of the fourth transistor is configured to obtain the third control signal; the drain terminal of the fourth transistor is configured to output the output signal; a gate terminal of the fifth transistor is configured to obtain the third voltage control signal; and a source terminal of the fifth transistor is configured to obtain the fourth control signal.

In a possible design, a width of the fourth transistor may be 50 to 200μm. In some embodiments, the width of the fourth transistor may be 50 to 120μm. In some embodiments, the width of the fourth transistor may be 60 to 80μm. In some embodiments, the width of the fourth transistor may be 70 to 80μm, e.g. 72μm, 75μm, or 77μm.

In a possible design, a width of the fifth transistor may be 10 to 20μm. In some embodiments, the width of the fifth transistor may be 15 to 20μm e.g. 18μm, or 20μm.

The output unit includes a path-gate structure including the fourth transistor and the fifth transistor. The fourth transistor contributes both to charging and discharging of the load. The fifth transistor only needs a small driving capability to keep the output signal of the shift register during a low state to be VGL. The size of the fifth transistor is minimized, thereby maintaining a narrow border.

In a possible design, the charge-pump circuit includes: a sixth transistor, a seventh transistor, an eighth transistor, and a second capacitor, and the fourth input signal includes a second start pulse input signal, a second control signal, a third control signal, a fourth control signal and a fifth control signal: wherein a gate terminal of the seventh transistor is configured to obtain the second start pulse input signal; a drain terminal of the sixth transistor is coupled to the gate terminal of the seventh transistor; a source terminal of the sixth transistor and a source terminal of the seventh transistor are configured to obtain the fifth control signal; a gate terminal of the eighth transistor is configured to obtain the third control signal; a first terminal of the second capacitor is configured to obtain the second control signal; a source terminal of the eighth transistor is configured to obtain the fourth control signal; a drain terminal of the eighth transistor is coupled to a drain terminal of the seventh transistor and a second terminal of the second capacitor; the second terminal of the second capacitor is configured to output the third voltage control signal.

According to a second aspect, an embodiment of this application provides a shift register, including an input circuit, a bootstrapping circuit, and an output circuit, wherein the input circuit is configured to obtain a first input signal and output a first voltage control signal, a second voltage control signal and a third voltage control signal according to the first input signal, wherein the first voltage control signal is used to adjust a voltage of a first node, the second voltage control signal is used to adjust a voltage of a second node, and the third voltage control signal is used to adjust a voltage of a third node; the bootstrapping circuit is configured to obtain a second input signal and output a fourth voltage control signal, wherein the fourth voltage control signal is used to adjust the voltage of the second node; and the output circuit is configured to obtain a third input signal and output an output signal according to the third input signal, wherein the third input signal comprises a voltage signal from the second node and a voltage signal from the third node.

The above-mentioned shift register may be an emission driver on array (EOA) unit in an EOA sub-circuit. A display panel including the EOA sub-circuit may be narrow.

In a possible design, the input circuit comprises a input sub-circuit and a charge-pump sub-circuit, the first input signal comprises a first start pulse input signal and a second start pulse input signal, wherein the input sub-circuit is configured to output the first voltage control signal according to the first start pulse signal, the charge-pump sub-circuit is configured to output the second voltage control signal and the third voltage control signal according to the second start pulse input signal.

In a possible design, the input sub-circuit comprises a first transistor, the first input signal further comprises a first control signal, wherein a source terminal of the first transistor is configured to obtain the first start pulse input signal, a gate terminal of the first transistor is configured to obtain the first control signal, and a drain terminal of the first transistor is configured to output the first voltage control signal.

In a possible design, the charge-pump sub-circuit comprises: a second transistor, a third transistor, and a first capacitor, and the first input signal further comprises a first control signal and a second control signal: wherein a source terminal of the second transistor is configured to obtain the second start pulse input signal; a source terminal of the third transistor is configured to obtain the second control signal; a gate terminal of the second transistor is configured to obtain the first control signal; a drain terminal of the third transistor is configured to output the second voltage control signal; a drain terminal of the second transistor is coupled to a gate terminal of the third transistor and a first terminal of the first capacitor; the first terminal of the first capacitor is configured to output the third voltage control signal, and a second terminal of the first capacitor is configured to obtain the first control signal.

In a possible design, the output circuit comprises a fourth transistor and a fifth transistor, and the third input signal further comprises a second control signal and a fourth control signal, a gate terminal of the fourth transistor is coupled to the second node; a gate terminal of the fifth transistor is coupled to the third node; a source terminal of the fourth transistor is configured to obtain the second control signal; a source terminal of the fifth transistor is configured to obtain the fourth control signal; a drain source of the fourth transistor is coupled to a drain source of the fifth transistor; and the drain source of the fourth transistor is configured to output the output signal.

In a possible design, a width of the transistor may be 50 to 200μm. In some embodiments, the width of the fourth transitory may be 50 to 120μm. In some embodiments, the width of the fourth transistor may be 60 to 80μm. In some embodiments, the width of the fourth transistor may be 70 to 80μm, e.g. 72μm, 75μm, or 77μm.

In a possible design, the bootstrapping circuit comprises a sixth transistor and a second capacitor, and the second input signal comprises a voltage signal from the first node and a third control signal, wherein a first terminal of the second capacitor is coupled to a gate terminal of the sixth transistor; a second terminal of the second capacitor is coupled to a drain terminal of the sixth transistor; the gate terminal of the sixth transistor is configured to obtain the voltage signal from the first node; the drain terminal of the sixth transistor is coupled to the second node; and a source terminal of the sixth transistor is configured to obtain the third control signal.

According to a third aspect, an embodiment of this application provides a shift register, wherein including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seven transistor, a first capacitor, and a second capacitor, wherein a first terminal of the first capacitor is coupled to a drain terminal of the first transistor, a gate terminal of the second transistor, and a gate terminal of the third transistor; a second terminal of the first capacitor is coupled to a drain terminal of the second transistor, a drain terminal of the sixth transistor, and a gate terminal of the fourth transistor; a first terminal of the second capacitor is coupled to a drain terminal of the fourth transistor, a drain terminal of the fifth transistor, a gate terminal of the sixth transistor, and a gate terminal of the seventh transistor; a drain terminal of the seventh transistor is coupled to a drain terminal of the third transistor.

By convention, the high level signal of input signals is referred as VGH, and the low level signal of the input signals is referred as VGL, and a threshold voltage which is used to turn on a transistor in the input circuit is referred as Vth. Therefore, a first voltage Vn11, a second voltage Vn12, and VGL satisfy: Vn12<VGL<Vn13.

For example, Vn11, Vn2, VGL, and VGH may satisfy:

Vn11=VGH;

Vn12= = VGL-Vth- (VGH-VGL) ,

In a possible design, a width of the third transistor may be 50 to 200μm. In some embodiments, the width of the third transistor may be 50 to 120μm. In some embodiments, the width of the third transistor may be 60 to 80μm. In some embodiments, the width of the third transistor may be 70 to 80μm, e.g. 72μm, 75μm, or 77μm.

In a possible design, a width of the seventh transistor may be 10 to 20μm. In some embodiments, the width of the seventh transistor may be 15 to 20μm e.g. 18μm, or 20μm.

Furthermore, the shift register merely includes 7 transistors and 2 capacitors (hereinafter referred as to “7T2C shift register” ) , which will also result in a narrow border.

In a possible design, the shift register further includes an eighth transistor, a drain terminal of the eighth transistor is coupled to a source terminal of the first transistor.

Although the shift register includes an extra transistor (that is, 8 transistors and 2 capacitors, hereinafter referred as to “8T2C shift register” ) , the gate bias voltage of the first transistor and the eighth transistor may be reduced. For example, for the 7T2C shift register, the gate bias voltage of the first transistor may be 2 (VGH-VGL) +Vth. If VGL=-5V, VGH=7V, then the gate bias voltage of the transistor may be 22V. However, for the 8T2C shift register, the gate bias voltage of the first transistor may be VGL- {VGL-Vth- (VGH-VGL) } , and the gate bias voltage of the eighth transistor may be VGH- (VGL-Vth) . If VGL=-5V, VGH=7V, then the gate bias voltage of the first transistor and the eight transistor may be 10V.

According to a fourth aspect, an embodiment of this application provides a shift register, including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor, wherein a first terminal of the first capacitor is coupled to a drain terminal of the first transistor, and a gate terminal of the third transistor; a second terminal of the first capacitor is coupled to a drain terminal of the third transistor, a drain terminal of the second transistor, and a gate terminal of the fifth transistor; a first terminal of the second capacitor is coupled to a gate terminal of the second transistor, a drain terminal of the fourth transistor, and a gate terminal of the sixth transistor; a drain terminal of the fifth transistor is coupled to a drain terminal of the sixth transistor.

The above-mentioned shift register may be an emission driver on array (EOA) unit in an EOA sub-circuit. The EOA sub-circuit only include 6 transistors and 2 capacitors. Therefore, a display panel including the EOA sub-circuit may be narrow.

In a possible design, a width of the fifth transistor may be 50 to 200μm. In some embodiments, the width of the fifth transistor may be 50 to 120μm. In some embodiments, the width of the fifth transistor may be 60 to 80μm. In some embodiments, the width of the fifth transistor may be 70 to 80μm, e.g. 72μm, 75μm, or 77μm.

In a possible design, a width of the sixth transistor may be 10 to 20μm. In some embodiments, the width of the sixth transistor may be 15 to 20μm e.g. 18μm, or 20μm.

According to a fifth aspect, an embodiment of this application provides a shift register circuit, including at least one stage of the shift register according to any one of possible designs in the first aspect or the third aspect, wherein a first stage of the shift register is coupled to a start pulse input signal line, and the start pulse input signal line is used to supply a start pulse input signal, each of remaining stages of shift registers is coupled to a start pulse output terminal of its corresponding previous stage of a shift register, wherein the start pulse output terminal is used to output a corresponding start pulse input signal, and the shift register circuit further including: a first external control signal line, configured to supply a first external control signal to each of stages of shift registers, a second external control signal line, configured to supply a second external control signal to each of the stages of the shift registers; a first clock signal line, configured to supply a first clock signal to each of the stages of the shift registers; a second clock signal line, configured to supply a second clock signal to each of the stages of the shift registers; a third clock signal line, configured to supply a third clock signal to odd-numbered stages of the shift registers; and a fourth clock signal line, configured to supply a fourth clock signal to even-numbered stages of the shift registers.

The shift register circuit can also be called a GOA circuit. Corresponding, the shift register in the first aspect and the third aspect may be called a GOA sub-circuit or a GOA unit.

According to a sixth aspect, an embodiment of this application provides a display panel including the shift register circuit according to the fifth aspect.

According to a seventh aspect, an embodiment of this application provides an electronic device including the display panel according to the sixth aspect.

According to an eighth aspect, an embodiment of this application provides a shift register circuit, including at least one stage of the shift register according to any one of possible designs in the second aspect or the fourth aspect, wherein a first stage of the shift register is coupled to start pulse input signal lines, and the start pulse input signal lines are used to supply start pulse input signals, each of remaining stages of shift registers is coupled to start pulse output terminals of its corresponding previous stage of a shift register, wherein the start pulse output terminals are used to output corresponding start pulse input signals, and the shift register circuit further including: a first external control signal line, configured to supply a first external control signal to each of stages of shift registers, a second external control signal line, configured to supply a second external control signal to each of the stages of the shift registers; a first clock signal line, configured to supply a first clock signal to each of the stages of the shift registers; and a second clock signal line, configured to supply a second clock signal to each of the stages of the shift registers.

The shift register circuit can also be called an EOA circuit. Corresponding, the shift register in the second aspect and the fourth aspect may be called an EOA sub-circuit or an EOA unit.

According to a ninth aspect, an embodiment of this application provides a display panel including the shift register circuit according to the eighth aspect.

According to a tenth aspect, an embodiment of this application provides an electronic device including the display panel according to the ninth aspect.

In a possible design, the above-mentioned transistor may be a P-type metal oxide semiconductor (PMOS) transistor.

In a possible design, the above-mentioned transistor may be a thin-film transistor (TFT) . The TFT may be made through a semiconductor process such as low temperature polysilicon (LTPS) , low temperature polycrystalline oxide (LTPO) , indium gallium zinc oxide (IGZO) , or amorphous silicon (aSi) .

In a possible design, a width of a border of the display panel maybe 0.8 to 1.2mm, e.g., 1.0mm, or 1.1mm.

DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic structure diagram of a shift register according to an embodiment of the present application.

FIG. 2 shows schematic structure diagrams of an input circuit.

FIG. 3 shows schematic structure diagrams of a bootstrapping circuit.

FIG. 4 shows a schematic structure diagram of an output circuit.

FIG. 5 shows a shift register.

FIG 6 is a schematic structure diagram of a shift register according to another embodiment of the present application.

FIG. 7 shows schematic structure diagrams of a charge-pump circuit.

FIG. 8 shows a schematic structure diagram of an output circuit.

FIG. 9 shows a shift register.

FIG. 10 shows a shift register.

FIG. 11 shows another shift register.

FIG. 12 shows a timing chart corresponding to a shift register according to an embodiment of the present application.

FIG. 13 shows another timing chart corresponding to a shift register according to an embodiment of the present application.

FIG. 14 is a schematic structure diagram of another shift register according to an embodiment of the present application.

FIG. 15 is a schematic structure diagram of a charge-pump circuit.

FIG. 16 is a schematic structure diagram of an EOA sub-circuit.

FIG. 17 shows a timing chart corresponding to the EOA sub-circuit shown in FIG. 16.

FIG. 18 is a schematic structure diagram of a shift register circuit according to an embodiment of the present application.

FIG. 19 shows an example of even-numbered stages of the shift registers.

FIG. 20 is a schematic structure diagram according to an embodiment of the present application.

DESCRIPTION OF EMBODIMENTS

The following describes the technical solutions in this application with reference to the accompanying drawings.

As shown in FIG. 1, a shift register 100 includes an input circuit 110, a bootstrapping circuit 120, and an output circuit 130.

The input circuit 110 includes three terminals, that is, a terminal T11, a terminal T12, and a terminal T13.

The terminal T11 is used to obtain a start pulse input signal GA (n-1) . If the shift register 100 is a first shift register in a shift register circuit including a plurality of shift registers, the terminal T11 may obtain a start pulse input signal GA (0) from a start pulse input signal line; and if the shift register 100 is one of remaining shift registers in the shift register circuit, the terminal T11 may obtain the start pulse input signal GA (n-1) from a previous shift register. For example, if the shift register 100 is a second shift register in the shift register circuit, the shift register 100 may obtain a start pulse input signal GA (1) from the first shift register in the shift register circuit through the terminal T11; and if the shift register 100 is a third shift register in the shift register circuit, the shift register 100 may obtain a start pulse input signal GA (2) from the second shift register in the shift register circuit through the terminal T11. In some embodiments, the terminal T11 of the input circuit 110 may be called an input terminal of the shift register 100.

The terminal T12 is used to obtain a control signal.

The terminal T13 is coupled to a first node. The terminal T13 may output a signal to adjust a voltage of the first node. Therefore, the signal output by the terminal T13 may be called a first voltage control signal. The first voltage control signal may pull up or pull down the voltage of the first node according to the control signal obtained from the terminal T12 and the start pulse input signal obtained from the terminal T11. More specifically, the input circuit 110 may include one or more transistors. The control signal obtained from the terminal T12 is used to control states of the transistors. Therefore, the first voltage control signal output by the terminal T13 may correspond to the start pulse input signal obtained from the terminal T11 under the control of the control signal obtained from the terminal T12.

The bootstrapping circuit 120 includes three terminals, that is, a terminal T21, a terminal T22, and a terminal T23.

The terminal T21 is coupled to the first node.

The terminal T22 is used to output a start pulse input signal GA (n) . So, the shift register 100 may obtain a start pulse input signal through the terminal T11 of the input circuit and output a start pulse input signal through the terminal T22 of the bootstrapping circuit 120. For convenience, the start pulse input signal obtained by the input circuit 110 may be referred to as a first start pulse input signal, and the start pulse input signal output by the bootstrapping circuit may be referred to as a second start pulse input signal. The reason for using the term second start pulse “input signal” to describe the signal output from the terminal T22 is that this signal is the start pulse input signal obtained by another shift register in the shift register circuit. For example, if the shift register 100 is the first shift register in the shift register circuit, the shift register 100 may obtain the first start pulse input signal GA (0) from the start pulse input signal line and output the second start pulse input signal GA (1) to the second shift register in the shift register circuit; and if the shift register 100 is the second shift register in the shift register circuit, the shift register 100 may obtain the first start pulse input signal GA (1) from the first shift register and output the second start pulse input signal GA(2) to the third shift register in the shift register circuit, and the like.

The terminal T23 is used to obtain a control signal. In some embodiments, the control signal obtained by the terminal T23 may be different from the control signal obtained by the terminal T12. For convenience, the control signal obtained by the terminal T12 may be referred to as a first control signal, and the control signal obtained by the terminal T23 may be referred to as a second control signal.

In some embodiments, the second start pulse input signal output from the terminal T22 corresponds to the second control signal under the control of the first voltage of the first node.

Furthermore, the bootstrapping circuit 120 may output a second voltage control signal through the terminal T21. The second voltage control signal is used to adjust the voltage of the first node, and the second voltage control signal corresponds to the second start pulse input signal.

The output circuit 130 includes three terminals, that is, a terminal T31, a terminal T32, and a terminal T33.

The terminal T31 is coupled to the first node.

The terminal T32 is used to obtain a control signal. The control signal obtained by the terminal T32 may be different from the control signal obtained by the terminal T12 (that is, the first control signal) and the control signal obtained by the terminal T23 (that is, the second control signal) . For convenience, the control signal obtained by the terminal T32 may be referred to as a third control signal.

The terminal T33 may output an output signal G (n) . The output signal G (n) is a driving signal that is used to drive pixels corresponding to the shift register 100.

In some embodiments, the output signal G (n) corresponds to the third control signal under the control of the voltage of the first node which is obtained from the terminal T31.

FIG. 2 shows schematic structure diagrams of an input circuit.

FIG. 2 (a) shows an embodiment of an input circuit. According to the FIG. 2 (a) , the input circuit only includes one transistor M1.

A source terminal of the transistor M1 is coupled to the terminal T11 of the input circuit; a gate terminal of the transistor M1 is coupled to the terminal T12; and a drain terminal of the transistor M1 is coupled to the terminal T13.

In some embodiments, the wording “is coupled to” may be understood as “is” . For example, for the input circuit shown in FIG. 2 (a) , the source terminal of the transistor M1 is the terminal T11, the gate terminal of the transistor M1 is the terminal T12, and the drain terminal of the transistor M1 is the terminal T13.

FIG. 2 (b) shows another embodiment of an input circuit. According to FIG. 2 (b) , the input circuit includes two transistors, that is, a transistor M1 and a transistor M8.

A source terminal of the transistor M1 is coupled to the terminal T11 of the input circuit, in other words, the source terminal of the transistor M1 is the terminal T11. A drain terminal of the transistor M1 is coupled to a source terminal of the transistor M8. A drain terminal of the transistor M8 is coupled to the terminal T13 of the input circuit. The terminal T12 includes two sub-terminals, one of the sub-terminals, a first sub-terminal T12-1, is coupled to a gate terminal of the transistor M1, and another sub-terminal, a second sub-terminal T12-2, is coupled to a gate terminal of the transistor M8. As shown, in FIG. 2 (b) , a control signal obtained by the first sub-terminal T12-1 is different from a control signal obtained by the second sub-terminal T12-2. The control signal obtained by the first sub-terminal T12-1 may be the above-mentioned the first control signal. The control signal obtained by the second sub-terminal T12-2 may be referred to as a second external scan control signal.

FIG. 3 shows schematic structure diagrams of a bootstrapping circuit.

FIG. 3 (a) shows an embodiment of a bootstrapping circuit. According to FIG. 3 (a) , the bootstrapping circuit includes a capacitor C1 and a transistor M2.

The capacitor C1 has a first terminal and a second terminal. The first terminal of the capacitor C1 is coupled to a gate terminal of the transistor M2, and the second terminal of the capacitor C1 is coupled to a drain terminal of the transistor M2. A source terminal of the transistor M2 is coupled to the terminal T23 of the bootstrapping circuit, in other words, the source terminal of the transistor M2 is the terminal T23. The gate terminal of the transistor M2 is coupled to the terminal T21 of the bootstrapping circuit. The drain terminal of the transistor M2 is coupled to the terminal T22 of the bootstrapping circuit.

FIG. 3 (b) shows another embodiment of the bootstrapping circuit. As shown in FIG. 3 (b) , two capacitors, C11 and C12, are used to replace the capacitor C1 of the bootstrapping circuit shown in FIG. 3 (a) .

FIG. 4 shows a schematic structure diagram of an output circuit. As shown in FIG. 4, the output circuit includes one transistor M3. A gate terminal of the transistor M3 is coupled to the terminal T31 of the output circuit, a source terminal of the transistor M3 is coupled to the terminal T32 of the output circuit, and a drain terminal of the transistor M3 is coupled to the terminal T33 of the output circuit.

FIG. 5 shows a shift register. As shown in FIG. 5, the shift register includes the input circuit shown in FIG. 2 (a) , the bootstrapping circuit shown in FIG. 3 (a) , and the output circuit shown in FIG. 4.

As shown in FIG. 6, a shift register 600 includes an input circuit 610, a bootstrapping circuit 620, an output circuit 630, and a charge-pump circuit 630.

The connection relation between the input circuit 610, the bootstrapping circuit 620 and the output circuit 630 is the same as that of the shift register. For the purpose of convenient and brief description, the details of the connection relation are not described here again.

As shown in FIG. 6, the output circuit further includes a terminal T34 and a terminal T35. The terminal T34 is coupled to the charge-pump circuit, and the terminal T35 is used to obtain a control signal. The control signal obtained by the terminal T35 may be referred to as a fourth control signal.

The charge-pump circuit 640 includes three terminals, that is, a terminal T41, a terminal T42, and a terminal T43.

The terminal T41 is coupled to a second node.

The terminal T42 is used to obtain control signals. The detail of the control signals obtained by the terminal T42 will be described later.

The terminal T43 is coupled to the terminal T34 of the output circuit 630. The terminal T43 outputs a third voltage control signal to the output circuit according to the second start pulse input signal obtained from the terminal T41 and the control signals obtained from the terminal T42.

FIG. 7 shows schematic structure diagrams of a charge-pump circuit.

As shown in FIG. 7 (a) , a charge-pump circuit includes three transistors (that is, a transistor M6, a transistor M4 and a transistor M5) and one capacitor C2.

A drain terminal of the transistor M6 is coupled to a gate terminal of the transistor M4.The gate terminal of the transistor M4 is coupled to the terminal T61 of the charge-pump circuit. A drain terminal of the transistor M5 is coupled to a first terminal of the capacitor C2, and the drain terminal of the transistor M5 is coupled to the terminal T63 of the charge-pump circuit.

The terminal T62 of the charge-pump circuit includes four sub-terminals, that is, a sub-terminal T62-1, a sub-terminal T62-2, a sub-terminal T62-3, and a sub-terminal T62-4.

The sub-terminal T62-1 is coupled to a source terminal of the transistor M6, the sub-terminal T62-2 is coupled to a gate terminal of the transistor M5, the sub-terminal T62-3 is coupled to a second terminal of the capacitor C2, and the sub-terminal T62-4 is coupled to a source terminal of the transistor M5.

As shown in FIG. 7 (a) , different sub-terminals obtain different control signals. More specifically, the sub-terminal T62-1 obtains a fifth control signal, the sub-terminal T62-2 obtains the third control signal, the sub-terminal T62-3 obtains the second control signal, and the sub-terminal T62-4 obtains the fourth control signal.

FIG. 7 (b) shows anther charge-pump circuit. Compared with the charge-pump circuit shown in FIG. 7 (a) , the charge-pump circuit shown in FIG. 7 (b) further includes transistor M8, transistor M9 and capacitor C3. As shown in FIG. 7 (b) , the connection relation of the transistor M4, the transistor M5, the transistor M6 and the capacitor C2 is the same as that of the charge-pump circuit shown in FIG. 7 (a) .

A gate terminal of the transistor M8 is coupled to the second node n2, a source terminal of the transistor M8 is coupled to the terminal T62-1, and a drain terminal is coupled to a fourth node n4. A gate terminal of the transistor M9 is coupled to a drain terminal of the transistor M9, and a source terminal of the transistor M9 is coupled to the fourth node. The first terminal of the capacitor is coupled to the drain terminal of the transistor M9. A first terminal of the capacitor C3 is coupled to the fourth node. Similar to the charge-pump circuit shown in FIG. 7 (a) , the charge-pump circuit shown in FIG. 7 (b) also include the terminal T61, the terminal T63, and the sub-terminals T62-1 to T62-4. The connection relation of the terminal T61, the sub-terminal T62-1, the sub-terminal T62-3 and the sub-terminal T62-4 of the charge-pump circuit shown in FIG. 7 (b) is the same as that of the charge-pump shown in FIG. 7 (a) . The sub-terminal T62-2 of the charge-pump shown in FIG. 7 (b) is coupled to the gate terminal of the transistor M9 and a second terminal of the capacitor C3, and the terminal T63 is coupled to the fourth node n4.

In some embodiments, the transistor M9 in the charge-pump circuit shown in FIG. 7 (b) may be replaced by a diode. A cathode terminal of the diode is coupled to the first terminal of the capacitor C2, and an anode terminal of the diode is coupled to the fourth node n4.

Further, compared to the charge-pump circuit shown in FIG. 7 (a) , the charge-pump circuit shown in FIG. 7 (b) further includes one sub-circuit consisting of the transistor M8, the transistor M9 and the capacitor C3. In some embodiments, the charge-pump circuit may include more than one such sub-circuit. For example, in some embodiment, the charge-pump circuit includes two sub-circuit, a connection relation of the first sub-circuit consisting of the transistor M8, the transistor M9 and the capacitor C3 is the same as the sub-circuit shown in FIG. 7 (b) , and for another sub-circuit consisting of the transistor M10, the transistor M11 and the capacitor C3, a gate terminal of the transistor M10 is coupled to the second node n10, a source terminal of the transistor M10 is coupled to the source terminal of the transistor M8, and a drain terminal of the transistor M10 is coupled to a fifth node. A gate terminal of the transistor M11 is coupled to a drain terminal of the transistor M11, and a source terminal of the transistor M1 is coupled to the fifth node. The first terminal of the capacitor C4 is coupled to the drain terminal of the transistor M11. A first terminal of the capacitor C4 is coupled to the fifth node. The terminal T63 is coupled to the fifth node.

FIG. 8 shows a schematic structure diagram of an output circuit.

As shown in FIG. 8, the output circuit includes two transistors, that is, a transistor M3 and a transistor M7.

A gate terminal of the transistor M3 is coupled to the terminal T31 of the output circuit, a source terminal of the transistor M3 is coupled to the terminal T32 of the output circuit, and a drain terminal of the transistor M3 is coupled to a drain terminal of the transistor M7. A gate terminal of the transistor M7 is coupled to the terminal T34 of the output circuit, and a source terminal of the transistor M7 is coupled to the terminal T35 of the output circuit. The terminal T33 of the output circuit is coupled to the drain terminal of the transistor M3.

In some embodiments, the first control signal to the third control signal may be three different clock signals.

In some embodiments, the first control signal is a first clock signal (hereinafter referred to as “CLK 1” ) , the second control signal is a second clock signal (hereinafter referred to as “CLK 2” ) , and the third control signal is a third clock signal (hereinafter referred to as “CLK 3) .

In some embodiments, the first control signal is the CLK 1, the second control signal is the CLK 2, and the third control signal is a fourth clock signal (hereinafter referred to as “CLK 4” ) which is different from the CLK 3.

In some embodiments, the fourth control signal is a second external control signal, and the fifth control signal is a first external control signal.

In some embodiments, the first external control signal is at a constant high level. Therefore, the first external control signal may be called VGH. The second external control signal is at a constant low level. Therefore, the second external control signal may be called VGL.

FIG. 9 shows a shift register. As shown in FIG. 9, a shift register 900 includes the input circuit shown in FIG. 2 (a) , the bootstrapping circuit shown in FIG. 3 (a) , the charge-pump circuit shown in FIG. 7 (a) , and the output circuit shown in FIG. 8.

FIG. 10 shows a shift register. As shown in FIG. 10, a shift register 1000 includes the input circuit shown in FIG. 2 (b) , the bootstrapping circuit shown in FIG. 3 (a) , the charge-pump circuit shown in FIG. 7 (a) , and the output circuit shown in FIG. 8.

Optionally, in some embodiments of the present application, the above-mentioned transistor may be a thin-film transistor (TFT) . In some embodiments, the TFT may be made through a semiconductor process such as low temperature polysilicon (LTPS) , low temperature polycrystalline oxide (LTPO) , indium gallium zinc oxide (IGZO) , or amorphous silicon (aSi) .

Optionally, in some embodiments of the present application, the above-mentioned transistor may be a P-type metal oxide semiconductor (PMOS) transistor.

Optionally, in some embodiments of the present application, the above-mentioned transistor may be an N-type metal-oxide-semiconductor (NMOS) transistor.

Optionally, in some embodiments of the present application, a width of the transistor M3 shown in FIG. 9 and FIG. 10 may be 50 to 200μm. In some embodiments, the width of the transitory M3 may be 50 to 120μm. In some embodiments, the width of the transistor M3 may be 60 to 80μm. In some embodiments, the width of the transistor M3 may be 70 to 80μm, e.g. 72μm, 75μm, or 77μm.

Optionally, in some embodiments of the present application, a width of the transistor M7 may be 10 to 20μm. In some embodiments, the width of the transistor M7 may be 15 to 20μm e.g. 18μm, or 20μm.

There is no limitation for the length of the transistor M3 and M7. By way of example rather than limitation, the length of the transistor M3 or M7 may be 3μm.

In some embodiments of the present application, the shift register shown in FIG. 1, FIG. 5, FIG. 6, FIG. 9 and FIG. 10 may be a unit in a GOA circuit. Therefore, the shift register shown in the above-mentioned figures may be referred to as a GOA unit.

FIG. 11 shows another shift register. a shift register 1100 include 9 transistors and 2 capacitors (hereinafter referred to as “9T2C” ) .

A high side switch transistor M1 shown in FIG. 11 is only a biased small voltage: Vgs=VGL-VGH-Vth (i.e., VGL=-5V, VGH=7V, Vth=-2V, Vgs=-5-7+2=-10V) . The transistor on resistance during the transistor M1 at on-state is not sufficiently, thereby giving a low driving capability and needing a large transistor width. This is a disadvantage in making narrow border.

However, according to the present application, a voltage of the first node in the shift register according to the present application (e.g., the shift register shown in FIG. 1, FIG. 6, FIG. 9 or FIG. 10) is determined according to both the input circuit and the bootstrapping circuit. Therefore, the voltage of the first node in the shift register according to the present application may be biased to an extra-boosted voltage. The voltage of the first node is used to control the output circuit. Therefore, the voltage that is used to control the state of the transistor in the output circuit may be biased to an extra-boosted voltage.

Referring to FIG. 12, at point A, the capacitor C1 is discharged via the transistor M1.A threshold voltage (hereinafter referred to as “Vth” ) to turn on the transistor M1 remains on the first node n1. For convenience, it is assumed that the threshold voltages of all transistors mentioned in the present application are the same. Therefore, the voltage of the first node n1 is Vn1=VGL-Vth. When CLK 2 goes low (see point B) , the voltage of the first node n1 is further pushed down by the second node n2. The voltage of the first node n1 goes to Vn1= VGL-Vth- (VGH-VGL) . When the CLK 3 goes high (see point C) , the transistor M3 gate bias voltage is given by Vgs=Vn1-VGH=VGL-Vth- (VGH-VGL) -VGH =2(VGL-VGH) -Vth. If VGL=-5V, VGH=7V, Vth=-2V, then the Vgs=2 (-5-7) +2= -22V. Compared with the shift register shown in FIG. 11, the bias voltage of the gate terminal of the transistor M3 is much deeper, thereby making output rising and falling time faster, and allowing smaller transistors to maintain a narrower border. According to the fundamental equation given the transistor on resistance, when the Vgs have got small (small gate bias voltage) , then the transistor channel width should be bigger in order to keep the same Ron value. Therefore, according to the present application, the size of the transistor M3 may be small. For example, under the same voltages and output loading, the channel width of the transistor M3 shown in FIG. 9 or FIG. 10 may be about half of that of the transistor M1 shown in FIG. 11. For example, the size of the transistor M3 shown in FIG. 9 or FIG. 10 may be 70*3 μm (width*length) , and the size of the transistor M1 shown in FIG. 11 may be 140*3μm.

Further, as shown in FIG. 10, the output circuit includes a path-gate structure including the transistor M7 and M3. The transistor M3 contributes both to charging and discharging of the load. The transistor M7 only needs a small driving capability to keep G (n) during a low state to be VGL. The size of the transistor M7 is minimized, thereby maintaining a narrow border.

In some embodiments of the present application, the shift register includes the charge-pump circuit. The charge-pump circuit may generate an extra lower voltage than VGL to drive the low-side buffer transistor M7. The output G (n) is periodically discharged to VGL through the transistor M7. This stabilizes the shift-register function in variable refresh rate (VRR) , especially in 1Hz which is a super low refresh rate drive.

Referring to FIG. 13, at point D, the voltage of the third node n3 is pushed down. Therefore, the voltage of the third node n3 is Vn3=VGL-Vth; at point E, the voltage of the third node n3 is further pushed down to VGL-Vth- (VGH-VEL) . At point F, the transistor M7 gate bias voltage is given by Vgs=Vn3-VGL=VGL-Vth- (VGH-VGL) -VGL=VGL-VGH-Vth. If VGH=+7V, VGL=-5V and Vth=-2V, Vgs= -5-7-2=-14V (>Vth) , and therefore the transistor M7 is on state to discharge the output G (n) to VGL.

The timing chart shown FIG. 13 corresponds to the charge-pump circuit shown in FIG. 7 (a) . The charge-pump circuit shown in FIG. 7 (b) may further push down the voltage of the gate terminal of the transistor M7. According to the charge-pump circuit shown in FIG. 7 (b) , the voltage of the third node n3, the voltage of the fourth node n4, and the bias voltage of the transistor M7 satisfy:

Vn3=VGL-Vth- (VGH-VGL) ,

Vn4=Vn3-Vth- (VGH-VGL) =VGL-Vth- (VGH-VGL) -Vth- (VGH-VGL) =3VGL-2Vth-2VGH

VgsM7=Vn4-VGL=2 (VGL-VGH-Vth) ,

wherein, Vn3 is the voltage of the third node, Vn4 is the voltage of the fourth node, and VgsM7 is the gate bias voltage of the transistor M7. If VGL=-5V, VGH=7V, Vth=-2V, then the VgsM=2 (-5-7+2) =-20V.

FIG. 13 further shows a relation between the control signals. As shown in FIG. 12, a duration of tLine is longer than a duration of tWidth1, a duration of tWidth1 is longer than a duration of tWidth2, and a duration of tWidth2 is longer than a duration of tDelay. For example, tLine=3μs, tWidth1=2.6μs, tWidth2=1.4μs, and tDelay=0.2μs. It should be noted that the above-mentioned values of tLine, tWidth1, tWidth2 and tDelay are examples, and the value of these parameters can be adjusted depending on display resolution, frame rate, loading, and so on.

Further, if GA (n-1) is from the previous shift register, the width is the same as tWidth1. If the GA (0) is the start pulse, the pulse width is wider or the same as tWidth1, which is acceptable.

In some embodiments of the present application, the input circuit includes more than one transistor. Therefore, gate bias voltage stress to each of the transistors may be reduced. For example, the gate bias voltage of the transistor M1 shown in FIG. 9 may satisfy:

VgsM1 = VGH- {VGL-Vth- (VGH-VGL) } = 2 (VGH-VGL) +Vth.

If VGL=-5V, VGH=7V, Vth=-2V, the VgsM1 = 7- (-5+2- (7+5) ) = 22V.

However, according to the input circuit shown in FIG. 10, the gate bias voltage of the transistor M1 satisfies:

VgsM1 = VGH- (VGL-Vth)

The gate bias voltage of the transistor M8 satisfies:

VgsM8 = VGL- {VGL-Vth- (VGH-VGL) }

If VGL=-5V, VGH=7V, Vth=-2V, the VgsM1= 7+5-2 = 10V, and VgsM8=-5+5-2+7+5=10V. The gate bias voltage stress to the transistors M1 and M8 shown in FIG. 10 is only about half of that of the transistor M1 shown in FIG. 9.

Although FIG. 2 shows the input circuit including at most 2 transistors, the input circuit, in some embodiments, may include more than 2 transistors.

FIG 14 (a) shows a shift register 1400. As shown in FIG. 14 (a) , the shift register 1400 includes an input circuit 1401, a bootstrapping circuit 1420 and an output circuit 1403. The input circuit 1401 output a first voltage control signal, a second voltage control signal, and a third voltage control signal. The first voltage control signal is used to adjust a voltage of a first node n1, the second voltage control signal is used to adjust a voltage of a second node n2, and a third voltage control signal is used to adjust a voltage of a third node n3. The bootstrapping circuit 1420 outputs a fourth voltage control signal which is used to adjust the voltage of the second node. The output circuit 1430 outputs an output signal according to input signals including a voltage signal from the second node and a voltage signal from the third node.

In some embodiments, the input circuit 1401 includes an input sub-circuit 1410 and a charge-pump sub-circuit 1440

As shown in FIG. 14 (B) , the shift register 1400 includes the input sub-circuit 1410, the bootstrapping circuit 1420, an output circuit 1430, and the charge-pump sub-circuit 1440.

The input sub-circuit 1410 includes three terminals, that is, a terminal T411, a terminal T412, and a terminal T413.

The terminal T411 is used to obtain a first start pulse input signal EA (n-1) . The terminal T412 is used to obtain a first control signal. The terminal T413 is coupled to a first node n1.

The bootstrapping circuit 1420 includes three terminals, that is, a terminal T421, a terminal T422, and a terminal T423. The terminal T421 is coupled to the first node n1. The terminal T422 is used to obtain a third control signal. The third terminal is coupled to a second node n2. The third terminal is also used to output a third start pulse input signal EA(n) .

The charge-pump sub-circuit 1440 includes 5 terminals, that is, a terminal T441, a terminal T442, a terminal T443, a terminal T444, and a terminal T445. The terminal T441 is used to obtain a second start pulse input signal E (n-1) , the terminal T442 is used to obtain a second control signal; the terminal T443 is used to obtain the first control signal; the terminal T444 is coupled to the second node n2, and the terminal T445 is coupled to the output circuit 1430.

The output circuit 1430 includes several terminals that are used to obtain control signals and one terminal that is used to output an output signal. More specifically, the output circuit 1430 includes a terminal T431, a terminal T432, a terminal T433, a terminal T434, and a terminal T435. The terminal T435 is an output terminal that is used to output a fourth start pulse input signal. The terminal T431 to T434 are used to obtain control signals. The terminal T431 is coupled to the second node n2, the terminal T432 is coupled to the terminal T445 to obtain a fifth control signal, the terminal T433 is used to obtain the second control signal, and the terminal T434 is used to obtain a fourth control signal. The fifth control signal is used to adjust the voltage of the third node n3. Therefore, the fifth control signal may also be called as a third voltage control signal.

The shift register 1400 may be a unit in an emission driver on array (EOA) circuit. Therefore, the shift register 1400 may be referred to as an EOA sub-circuit.

In some embodiments, the first control signal and the third control signal may be different clock signals. For example, the first control signal is a first clock signal (hereinafter referred to as “CLK 1” ) , and the third control signal may be a second clock signal (hereinafter referred to as “CLK 2” ) .

In some embodiments, the second control signal and the fourth control signal may be different constant signals. For example, the second control signal may be at a constant high level (hereinafter referred to as VGH) , and the fourth control signal may be at a constant low level (hereinafter referred to as VGL) . In some embodiment, the second control signal and the fourth control signal may be called an external signal. To differentiate between the second control signal and the fourth control signal, the second control signal may be called a first external control signal, and the fourth control signal may be called a second external control signal.

In some embodiments, the input sub-circuit 1410 may include one or more transistors. The input circuit shown in FIG. 2 may be the input sub-circuit 1410. For example, if the input sub-circuit 1410 only includes one transistor, the input circuit shown in FIG. 2 (a) is the input sub-circuit 1410. Under this condition, the terminal T11 shown in FIG. 2 (a) is the terminal T411, the terminal T12 shown in FIG. 2 (a) is the terminal T412, and the terminal T13 show in FIG. 2 (a) is the terminal T413. If the input sub-circuit 1410 includes two transistors, the input circuit shown in FIG. 2 (b) is the input sub-circuit 1410. The terminal T11 shown in FIG. 2 (a) is the terminal T411, and the terminal T13 show in FIG. 2 (a) is the terminal T413. The terminal T412 may include two sub-terminals, one is the terminal T12-1 shown in FIG. 2 (b) , and another is the terminal T12-2 shown in FGI. 2 (b) . The terminal T12-1 is used to obtain the first control signal (that is, CLK 1) , and the terminal T12-2 is used to obtain the fourth control signal (that is, VGL) .

The bootstrapping circuits shown in FIG. 3 may be the bootstrapping circuit 1420.

The output circuit shown in FIG. 8 may be the output circuit 1430

FIG. 15 is a schematic structure diagram of a charge-pump circuit.

As shown in FIG. 15, the charge-pump circuit includes a transistor M2, a transistor M4, and a capacitor C2. A source terminal of the transistor M2 is the terminal T442, a drain terminal of the transistor M2 is the terminal T444. A gate terminal of the transistor M2 is coupled to a third node n3, a drain terminal of the transistor M4 is coupled to the third node n3, and one terminal of the capacitor C2 (hereinafter referred to as “a first terminal of the capacitor C2” ) is coupled to the third node n3. The terminal T445 is also coupled to the third node n3. In other words, the terminal T445 is coupled to the gate terminal of the transistor M2, and the drain terminal of the transistor M4 and the first terminal of the capacitor C2. Further, the terminal T443 is coupled to a gate terminal of the transistor M4 and another terminal of the capacitor C2, and a source terminal of the transistor is coupled to the terminal T441.

FIG. 16 is a schematic structure diagram of an EOA sub-circuit. As shown in FIG. 16, an EOA sub-circuit 1600 includes the input circuit shown in FIG. 2 (a) , the bootstrapping circuit shown in FIG. 3 (a) , the output circuit shown in FIG. 8, and the charge-pump circuit shown in FIG. 15.

FIG. 18 is a schematic structure diagram of a shift register circuit according to the present application.

As shown in FIG. 18, a shift register circuit 1800 includes at least one stage of the shift register. A first stage of the shift register is coupled to a start pulse input signal line, where the start pulse input signal line is used to supply a start pulse input signal.

Each of remaining stages of shift registers is coupled to a start pulse output terminal of its corresponding previous stage of a shift register, where the start pulse output terminal is used to output a corresponding start pulse input signal. The shift register further includes a first external control signal line, a second external control signal line, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line.

The first external control signal line is used to supply a first external control signal (that is, VGH) to each of stages of shift registers, and the second external control signal line is used to supply a second external control signal (that is, VGL) to each of the stages of the shift registers.

The first clock signal line is used to supply a first clock signal (that is, CLK 1) to each of the stages of the shift registers; the second clock signal line is used to supply a second clock signal (that is, CLK 2) to each of the stages of the shift registers; the third clock signal line is used to supply a third clock signal (that is, CLK 3) to odd-numbered stages of the shift registers; and the fourth clock signal line is used to supply a fourth clock signal (that is, CLK 4) to even-numbered stages of the shift registers.

The shift register in the shift register circuit 1800 shown in FIG. 18 may be the above-mentioned GOA unit. Therefore, the shift register circuit 1800 may be called a GOA circuit. The shift registers in the GOA unit shown in FIG. 18 may be the shift registers shown in FIG. 1, FIG. 5, FIG. 6, FIG. 9 and FIG. 10. More specifically, the shift registers shown in FIG. 1, FIG. 5, FIG. 6, FIG. 9 and FIG. 10 are the odd-numbered stages of the shift registers. FIG. 19 shows an example of the even-numbered stages of the shift registers. As shown in FIG. 9 and FIG. 19, the circuit of the odd unit in the GOA circuit is the same as that of the even unit. The difference between the odd unit and the even unit is that the control signal to some terminals is different.

An embodiment of this application further provides a display panel, the display panel includes the GOA circuit shown in FIG. 18.

In some embodiments, a width of a border of the display panel maybe 0.8 to 1.2mm, e.g., 1.0mm, or 1.1mm.

An embodiment of this application further provides an electronic device. The electronic device includes the above-mentioned display panel. The electronic device may be a smartphone, a tablet, a smart-watch, a television among others.

FIG. 20 is a schematic structure diagram according to the present application.

As shown in FIG. 20, a shift register circuit 2000 includes at least one stage of the shift register. A first stage of the shift register is coupled to two start pulse input signal lines, where the start pulse input signal lines are used to supply start pulse input signals.

Each of remaining stages of shift registers is coupled to start pulse output terminals of its corresponding previous stage of a shift register, where the start pulse output terminals are used to output corresponding start pulse input signals. The shift register further includes a first external control signal line, a second external control signal line, a first clock signal line, and a second clock signal line.

The first clock signal line is used to supply a first clock signal (that is, CLK 1) to each of the stages of the shift registers; the second clock signal line is used to supply a second clock signal (that is, CLK 2) to each of the stages of the shift registers.

An embodiment of this application further provides a display panel, the display panel includes the EOA circuit shown in FIG. 20.

It may be clearly understood by a person skilled in the art that, for the purpose of convenient and brief description, for a detailed working process of the foregoing system, apparatus, and unit, refer to a corresponding process in the foregoing method embodiment. Details are not described herein again.

In the several embodiments provided in this application, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. For example, the described apparatus embodiment is merely an example. For example, the unit division is merely logical function division and may be other division in actual implementation. For example, a plurality of units or components may be combined or integrated into another system, or some features may be ignored or not performed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections may be implemented through some interfaces. The indirect couplings or communication connections between the apparatuses or units may be implemented in electronic, mechanical, or other forms.

The units described as separate parts may be or may not be physically separate, and parts displayed as units may be or may not be physical units, may be located in one position, or may be distributed on a plurality of network units. Some or all of the units may be selected based on actual requirements to achieve the objectives of the solutions of the embodiments.

In addition, functional units in the embodiments of this application may be integrated into one processing unit, or each of the units may exist alone physically, or two or more units are integrated into one unit.

The foregoing descriptions are merely specific implementations of this application, but are not intended to limit the protection scope of this application. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in this application shall fall within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims

A shift register, comprising an input circuit, a bootstrapping circuit, and an output circuit, wherein

the input circuit is configured to obtain a first input signal and output a first voltage control signal according to the first input signal, wherein the first voltage control signal is used to adjust a voltage of a first node connecting to the input circuit;

the bootstrapping circuit is configured to obtain a second input signal and output a second voltage control signal according to the second input signal, wherein the second voltage control signal is used to adjust the voltage of the first node connecting to the bootstrapping circuit;

the output circuit is configured to obtain a third input signal and output an output signal according to the third input signal, wherein the third input signal comprises a voltage signal from the first node, and wherein the voltage signal comprises: a first voltage and a second voltage, and wherein the second voltage is lower than a low voltage of the first input signal and the low voltage of the first input signal is lower than the first voltage.
The shift register according to claim 1, wherein the input circuit comprises a first transistor, and the first input signal comprises a first start pulse input signal and a first control signal, wherein

a source terminal of the first transistor is configured to obtain the first start pulse input signal,

a gate terminal of the first transistor is configured to obtain the first control signal, and

a drain terminal of the first transistor is configured to output the first voltage control signal.
The shift register according to claim 1, wherein the input circuit comprises a first transistor and a second transistor, and the first input signal comprises a first start pulse input signal, a first control signal and a fourth control signal, wherein

a source terminal of the first transistor is configured to obtain the first start pulse input signal,

a gate terminal of the first transistor is configured to obtain the first control signal,

a gate terminal of the second transistor is configured to obtain the fourth control signal;

a drain terminal of the first transistor is coupled to a source terminal of the second transistor; and

a drain terminal of the second transistor is configured to output the first voltage control signal.
The shift register according to any one of claims 1 to 3, wherein the bootstrapping circuit comprises a third transistor and a first capacitor, the second input signal comprises a second control signal and the voltage signal wherein

a first terminal of the first capacitor is coupled to a gate terminal of the third transistor;

a second terminal of the first capacitor is coupled to a drain terminal of the third transistor;

the gate terminal of the third transistor is configured to obtain the voltage signal;

a source terminal of the third transistor is configured to obtain the second control signal.
The shift register according to claim 4, wherein the second terminal of the first capacitor is configured to output a second start pulse input signal.
The shift register according to any one of claims 1 to 5, wherein the output circuit comprises a fourth transistor, and the third input signal further comprises a third control signal, wherein

a gate terminal of the fourth transistor is configured to obtain the voltage signal,

a source terminal of the fourth transistor is configured to obtain the third control signal; and

a drain terminal of the fourth transistor is configured to output the output signal.
The shift register according to any one of claims 1 to 5, wherein the shift register further comprises a charge-pump circuit, wherein

the charge-pump circuit is configured to obtain a fourth input signal and output a third voltage control signal according to the fourth input signal;

the third input signal further comprises the third voltage control signal, the third voltage control signal comprises: a third voltage and a fourth voltage, and wherein the fourth voltage is lower than the low voltage of the first input signal and the low voltage of the first input signal is lower than the third voltage .
The shift register according to claim 7, wherein the output circuit comprises a fourth transistor and a fifth transistor, and the third input signal further comprises a third control signal and a fourth control signal, wherein

a drain terminal of the fourth transistor is coupled to a drain terminal of the fifth transistor,

a gate terminal of the fourth transistor is configured to obtain the voltage signal;

a source terminal of the fourth transistor is configured to obtain the third control signal;

the drain terminal of the fourth transistor is configured to output the output signal;

a gate terminal of the fifth transistor is configured to obtain the third voltage control signal; and

a source terminal of the fifth transistor is configured to obtain the fourth control signal.
The shift register according to claim 7 or 8, wherein the charge-pump circuit comprises: a sixth transistor, a seventh transistor, an eighth transistor, and a second capacitor, and the fourth input signal comprises a second start pulse input signal, a second control signal, a third control signal, a fourth control signal and a fifth control signal: wherein

a gate terminal of the seventh transistor is configured to obtain the second start pulse input signal;

a drain terminal of the sixth transistor is coupled to the gate terminal of the seventh transistor;

a source terminal of the sixth transistor and a source terminal of the seventh transistor are configured to obtain the fifth control signal;

a gate terminal of the eighth transistor is configured to obtain the third control signal;

a first terminal of the second capacitor is configured to obtain the second control signal;

a source terminal of the eighth transistor is configured to obtain the fourth control signal;

a drain terminal of the eighth transistor is coupled to a drain terminal of the seventh transistor and a second terminal of the second capacitor;

the second terminal of the second capacitor is configured to output the third voltage control signal.
A shift register, comprising an input circuit, a bootstrapping circuit, and an output circuit, wherein

the input circuit is configured to obtain a first input signal and output a first voltage control signal, a second voltage control signal and a third voltage control signal according to the first input signal, wherein the first voltage control signal is used to adjust a voltage of a first node, the second voltage control signal is used to adjust a voltage of a second node, and the third voltage control signal is used to adjust a voltage of a third node;

the bootstrapping circuit is configured to obtain a second input signal and output a fourth voltage control signal, wherein the fourth voltage control signal is used to adjust the voltage of the second node; and

the output circuit is configured to obtain a third input signal and output an output signal according to the third input signal, wherein the third input signal comprises a voltage signal from the second node and a voltage signal from the third node.
The shift register according to claim 10, wherein the input circuit comprises a input sub-circuit and a charge-pump sub-circuit, the first input signal comprises a first start pulse input signal and a second start pulse input signal, wherein

the input sub-circuit is configured to output the first voltage control signal according to the first start pulse signal,

the charge-pump sub-circuit is configured to output the second voltage control signal and the third voltage control signal according to the second start pulse input signal.
The shift register according to claim 11, wherein the input sub-circuit comprises a first transistor, the first input signal further comprises a first control signal, wherein

a source terminal of the first transistor is configured to obtain the first start pulse input signal,

a gate terminal of the first transistor is configured to obtain the first control signal, and

a drain terminal of the first transistor is configured to output the first voltage control signal.
The shift register according to claim 11 or 12, wherein the charge-pump sub-circuit comprises: a second transistor, a third transistor, and a first capacitor, and the first input signal further comprises a first control signal and a second control signal: wherein

a source terminal of the second transistor is configured to obtain the second start pulse input signal;

a source terminal of the third transistor is configured to obtain the second control signal;

a gate terminal of the second transistor is configured to obtain the first control signal;

a drain terminal of the third transistor is configured to output the second voltage control signal;

a drain terminal of the second transistor is coupled to a gate terminal of the third transistor and a first terminal of the first capacitor;

the first terminal of the first capacitor is configured to output the third voltage control signal, and

a second terminal of the first capacitor is configured to obtain the first control signal.
The shift register according to any one of claims 11 to 13, wherein the output circuit comprises a fourth transistor and a fifth transistor, and the third input signal further comprises a second control signal and a fourth control signal,

a gate terminal of the fourth transistor is coupled to the second node;

a gate terminal of the fifth transistor is coupled to the third node;

a source terminal of the fourth transistor is configured to obtain the second control signal;

a source terminal of the fifth transistor is configured to obtain the fourth control signal;

a drain source of the fourth transistor is coupled to a drain source of the fifth transistor; and

the drain source of the fourth transistor is configured to output the output signal.
The shift register according to any one of claims 10 to 13, wherein the bootstrapping circuit comprises a sixth transistor and a second capacitor, and the second input signal comprises a voltage signal from the first node and a third control signal, wherein

a first terminal of the second capacitor is coupled to a gate terminal of the sixth transistor;

a second terminal of the second capacitor is coupled to a drain terminal of the sixth transistor;

the gate terminal of the sixth transistor is configured to obtain the voltage signal from the first node;

the drain terminal of the sixth transistor is coupled to the second node; and

a source terminal of the sixth transistor is configured to obtain the third control signal.
A shift register, wherein comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seven transistor, a first capacitor, and a second capacitor, wherein

a first terminal of the first capacitor is coupled to a drain terminal of the first transistor, a gate terminal of the second transistor, and a gate terminal of the third transistor;

a second terminal of the first capacitor is coupled to a drain terminal of the second transistor, a drain terminal of the sixth transistor, and a gate terminal of the fourth transistor;

a first terminal of the second capacitor is coupled to a drain terminal of the fourth transistor, a drain terminal of the fifth transistor, a gate terminal of the sixth transistor, and a gate terminal of the seventh transistor;

a drain terminal of the seventh transistor is coupled to a drain terminal of the third transistor.
The shift register according to claim 16, further comprising an eighth transistor, a drain terminal of the eighth transistor is coupled to a source terminal of the first transistor.
A shift register, comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor, wherein

a first terminal of the first capacitor is coupled to a drain terminal of the first transistor, and a gate terminal of the third transistor;

a second terminal of the first capacitor is coupled to a drain terminal of the third transistor, a drain terminal of the second transistor, and a gate terminal of the fifth transistor;

a first terminal of the second capacitor is coupled to a gate terminal of the second transistor, a drain terminal of the fourth transistor, and a gate terminal of the sixth transistor;

a drain terminal of the fifth transistor is coupled to a drain terminal of the sixth transistor.
A shift register circuit, comprising at least one stage of the shift register according to any one of claims 1 to 9, 16, or 17, wherein a first stage of the shift register is coupled to a start pulse input signal line, and the start pulse input signal line is used to supply a start pulse input signal,

each of remaining stages of shift registers is coupled to a start pulse output terminal of its corresponding previous stage of a shift register, wherein the start pulse output terminal is used to output a corresponding start pulse input signal, and

the shift register circuit further comprising:

a first external control signal line, configured to supply a first external control signal to each of stages of shift registers,

a second external control signal line, configured to supply a second external control signal to each of the stages of the shift registers;

a first clock signal line, configured to supply a first clock signal to each of the stages of the shift registers;

a second clock signal line, configured to supply a second clock signal to each of the stages of the shift registers;

a third clock signal line, configured to supply a third clock signal to odd-numbered stages of the shift registers; and

a fourth clock signal line, configured to supply a fourth clock signal to even-numbered stages of the shift registers.
A display panel comprising the shift register circuit according to claim 19.
An electronic device comprising the display panel according to claim 20.
A shift register circuit, comprising at least one stage of the shift register according to any one of claims 10 to15, or 18, wherein a first stage of the shift register is coupled to start pulse input signal lines, and the start pulse input signal lines are used to supply start pulse input signals,

each of remaining stages of shift registers is coupled to start pulse output terminals of its corresponding previous stage of a shift register, wherein the start pulse output terminals are used to output corresponding start pulse input signals, and

the shift register circuit further comprising:

a first external control signal line, configured to supply a first external control signal to each of stages of shift registers,

a second external control signal line, configured to supply a second external control signal to each of the stages of the shift registers;

a first clock signal line, configured to supply a first clock signal to each of the stages of the shift registers; and

a second clock signal line, configured to supply a second clock signal to each of the stages of the shift registers.
A display panel comprising the shift register circuit according to claim 22.
An electronic device comprising the display panel according to claim 23.