JP2016110684A - Shift register circuit, gate driver, and display apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a shift register circuit comprising a single conductive transistor which performs overlap scanning without increasing the number of clock signals and reduces power consumption by avoiding an ineffective through current, gate driver, and display apparatus.SOLUTION: The shift register circuit comprising a single conductive type transistor includes: a shift register unit having a first output transistor which connects an output terminal and a first power supply; and a first gate control circuit of which an output terminal is connected to a gate terminal of the first output transistor, where the first gate control circuit comprises a timing generation unit and a buffer unit. The buffer unit is a bootstrap circuit, and an output of the timing generation unit to which an input signal is inputted is used as an input of the buffer unit and an output of the buffer unit is used as an output of the first gate control circuit.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a shift register circuit, a gate driver including the shift register circuit, and a display device including the gate driver.

  An active matrix semiconductor device in which transistors are arranged in a matrix as a switch element is widely used because it can realize a small, low power, and highly reliable device. For example, sensor devices equipped with light-receiving elements such as display devices and photodiodes using liquid crystal and EL (electroluminescence) materials are widely used as input / output interfaces for portable information terminal devices due to their thin and lightweight characteristics. Has been. In recent years, a thin film transistor (TFT) is arranged on an array substrate which is an insulating substrate as a switching element for driving a display pixel or an element for amplifying a weak sensitive signal, and a peripheral circuit for driving the TFT arranged in the array. For example, active matrix type devices in which a scanning line driving circuit and a signal line driving circuit are formed of TFTs on the same substrate as a switch element are actively developed. The feature is that by integrating the peripheral circuit on the array substrate, the effective area of the display or sensitive part active matrix can be increased, and the cost required for the peripheral circuit can be reduced.

  The TFTs arranged in the above array are often N-type or P-type single conductive transistors. If the peripheral circuit is composed of only the same single conductive transistor, mask exposure and impurity implantation are performed in the manufacturing process. Such a process can be shared with the TFTs arranged in an array, which leads to a reduction in manufacturing cost. An example in which a scanning line driving circuit (gate driver) among peripheral circuits is realized by linking shift registers each including only a single conductive transistor is disclosed in Patent Document 1.

  With the recent increase in size and definition of the display screen, the load capacity and load resistance of the gate line have increased, while the time for selecting the gate line, generally one horizontal period, has been shortened. There is an increasing demand for driver gate line driving capability. On the other hand, Patent Documents 1 and 2 disclose a method of extending the selection period by performing overlap scanning in which the selection periods are overlapped by a plurality of gate lines, thereby relaxing the driving capability requirement. The method includes a first gate driver that operates with a two-phase clock of non-overlapping clock signals CLK1 and CLK3, and a second gate driver that operates with a two-phase clock of non-overlapping clock signals CLK2 and CLK4. This is realized by providing them independently and providing an overlap section between CLK1, CLK3 and CLK2, CLK4. Here, the gate driver is composed of only N-type transistors. However, in the methods disclosed in Patent Documents 1 and 2, in order to extend the selection period of each gate line by overlapping the selection periods of a plurality of gate lines, the number of clock signals is increased. We have to go.

  In overlap scanning, the start of gate selection, i.e., delaying the rise of the gate line voltage when the single conductivity is N-type, is alleviated by extending the gate selection period. On the other hand, the end of gate selection, that is, the fall of the gate line voltage has no effect of reducing the delay, and if the fall time is delayed beyond the switching time (data idling) time of the data voltage written to the pixel, Talk, that is, a problem that a voltage confused with the data voltage written to the next pixel occurs. Non-Patent Document 1 discloses a gate driver that performs overlap scanning with only two phases of clock signals. FIG. 17 is a circuit diagram of a shift register circuit of this conventional gate driver, and FIG. 18 is a timing chart showing operation waveforms of this shift register circuit. As shown in FIG. 17, the output of the gate driver is lowered by an output transistor N10 and an inverter that controls the output transistor N10 (consisting of transistors N7 and N8). The inverter shown here has a problem that a through current flows from the power supply VDD to VSS via the transistors N7 and N8. In particular, in order to quickly lower the gate driver output, it is necessary to configure all of the transistors N10, N7, and N8 with a large size (transistor channel width) so that a large current can flow. Increase.

JP 2006-106394 A WO2012 / 073467 JP 2009-181612 A JP 2008-299941 A

Eunji Song and Hyoungsik Nam, SID2013 Digest, 35.4 (2013)

  When the number of clock signals increases in order to perform overlap scanning with a gate driver consisting of only a single conductive transistor, the power consumption required to drive the clock bus line increases, the number of terminals increases, and the clock with high amplitude An increase in the level shift circuits that generate signals becomes a problem. In addition, an increase in power consumption for rapidly decreasing the gate line voltage at which the selection of the gate line is completed becomes a problem.

  An object of the present invention is to provide a shift register circuit, a gate driver, and a display device which are configured by a single conductive transistor and can realize high-speed operation and low power consumption. In particular, an object of the present invention is to provide a shift register circuit, a gate driver, and a display device, each of which is composed of a single conductive transistor, which performs overlap scanning without increasing the number of clock signals and avoids an invalid through current. And

  The shift register circuit of the first invention is a shift register circuit composed of a single conductivity type transistor, and includes at least a first output transistor M1 that connects the output terminal of the shift register circuit and the first power supply VSS. And a first gate control circuit having an output terminal connected to the gate terminal of the first output transistor M1, the first gate control circuit comprising: a timing generation unit; a buffer unit; The buffer unit is a bootstrap circuit, the output of the timing generation unit to which the input O [n-2] is input is used as the input of the buffer unit, and the output of the buffer unit is the first gate control circuit. This is a shift register circuit to be output.

  In the shift register circuit of the second invention, the buffer section of the first gate control circuit includes at least a second transistor M11 that connects the first clock signal XCLK and the output Q [n], and the second transistor This is a bootstrap circuit composed of a third transistor M12 connecting the gate terminal of the transistor M11 and the output terminal of the timing generator.

  In the shift register circuit of the third invention, the buffer section of the first gate control circuit includes at least a second transistor M11 that connects the output Q [n] of the buffer section and the first clock signal XCLK. The third transistor M12 that connects the input Q1 of the buffer unit and the gate terminal Q2 of the second transistor M11 and is gate-controlled by the second clock signal CLK, and the output Q [n] of the buffer unit and the second transistor A fourth transistor M13 connected to one power source VSS and gate-controlled by the second clock signal CLK.

  In a shift register circuit according to a fourth aspect of the invention, the timing generator of the first gate control circuit is gate-controlled by the input O [n-2] of the first gate control circuit, and the first power supply VSS and A fifth transistor M14 that connects the input Q1 of the buffer unit, and a first capacitor C1 that connects the input Q1 of the buffer unit and the second clock signal CLK.

  In a shift register circuit according to a fifth aspect of the invention, the timing generator of the first gate control circuit is gate-controlled by the input O [n-2] of the first gate control circuit, and the first power supply VSS and A sixth transistor M15 that connects the input Q1 of the buffer unit and a seventh transistor M16 that connects the input Q1 of the buffer unit and the second power supply VDD and has a gate terminal connected to the second power supply VDD. It consists of.

  In a shift register circuit of a sixth invention, the shift register unit includes an eighth output transistor M2 having a source terminal connected to the output terminal of the shift register circuit and a drain terminal connected to the second power supply VDD. The ninth clock signal is input to the gate terminal of the first clock signal XCLK, the drain terminal is connected to the input O [n−1], and the source terminal is connected to the gate terminal P [n] of the eighth output transistor M2. Transistor M3.

  A shift register circuit according to a seventh aspect of the present invention is a shift register circuit composed of a single conductivity type transistor, and at least a first output transistor M1 that connects an output terminal of the shift register circuit and a first power supply VSS. And a first gate control circuit having an output terminal connected to the gate terminal of the first output transistor M1, the shift register unit including the output terminal of the shift register and the first A second gate control circuit including a tenth output transistor M4 connected to one power supply VSS, the output terminal of which is connected to the gate terminal of the tenth output transistor M4. The timing generation configured by a generation unit and a buffer unit and receiving an input O [n-2] or an input O [n-1]. The output of the input buffer unit, a shift register circuit to the output of the second gate control circuit the output of the buffer unit.

  In the shift register circuit according to an eighth aspect of the present invention, the buffer section that constitutes the first gate control circuit is a bootstrap circuit that outputs the first clock signal, and the buffer section that constitutes the second gate control circuit Is a bootstrap circuit for outputting the second clock signal.

  A gate driver of a ninth invention is a gate driver in which the shift register circuit of the seventh invention is connected in a plurality of stages, and the output O of the shift register circuit in the (n-2) th stage (n is an integer of 3 or more). [N-2] is input to the shift register unit of the (n−1) th stage and the first or second gate control circuit, and the first or second gate control circuit of the (n−1) th stage is input. The output Q [n] is input to the shift register unit at the (n−1) th stage and the shift register unit at the nth stage (the output O [n− of the shift register circuit at the (n−1) th stage). 1] is input to the n-th stage shift register unit and the second or first gate control circuit, and an output Q [n + 1] of the n-th stage second or first gate control circuit is The nth stage shift register section and the (n + 1) th stage Serial input to the shift register unit) is a gate driver.

  In the shift register circuit according to a tenth aspect of the present invention, the buffer section constituting the first gate control circuit has at least a second output Q2 [n], and the output Q2 [n] and the first power supply VSS An eleventh output transistor M17 connecting the output Q2, a twelfth transistor M18 connecting the output Q2 [n] and the output Q [n], a gate terminal of the twelfth transistor M18, and an (n + 2) th stage shift register. The eleventh output transistor M17 is controlled by the second clock signal CLK, and the thirteenth transistor M19 is controlled by the second power supply VDD. This is a bootstrap circuit, and this bootstrap circuit is added to the buffer unit of the third invention.

  In the shift register circuit of the eleventh aspect of the invention, the second output Q2 [n] of the gate control circuit of the tenth aspect of the invention is connected to the gate terminal of the first output transistor M1.

  A gate driver according to a twelfth aspect of the present invention is a gate driver obtained by connecting a plurality of stages of the shift register circuit according to the tenth aspect of the present invention, and the output of the shift register circuit in the (n-2) th stage (n is an integer of 3 or more). O [n-2] is input to the shift register unit of the (n-1) th stage and the gate control circuit of the tenth invention, and the output O [n + 2] of the shift register circuit of the (n + 2) th stage is the above-mentioned The input of the (n-1) th stage gate control circuit is used, and the first output of the (n-1) th stage gate control circuit is used as the shift register unit of the (n-1) th stage and the shift of the nth stage. A gate driver that receives the second output of the gate control circuit of the (n-1) th stage as an input of the register section and inputs of the shift register section of the nth stage.

  A display device according to a thirteenth aspect is a matrix type display device equipped with the gate driver according to the ninth or twelfth aspect, wherein a two-phase clock signal is input to the gate driver, and the first stage shift register of the gate driver is provided. In this display device, the start signal ST is inputted as the input, the selection period of the gate line is controlled by the pulse width of the start signal ST, and at the same time, a plurality of gate lines are overlapped and selected.

  In the shift register circuit of the present invention, the width of the output pulse of each shift register is determined not by the pulse width of the clock signal but by the width of the input pulse, for example, the output pulse of the preceding shift register circuit. Therefore, when a gate driver is configured by connecting a plurality of stages of shift register circuits, the clock signal may be two-phase even in overlap scanning.

  According to the present invention, a gate driver with high speed and low power consumption is realized. This is because the gate control of the output transistor for lowering the potential of the gate line at high speed is performed by a clock-driven bootstrap circuit that is a buffer unit, so that driving of a large load avoids power consumption such as through current. This is because it can be performed at high speed. Further, the area of the gate control circuit can be saved. This is because the bootstrap circuit is used as a buffer unit, so that the transistor size and capacitance size of the timing generation unit constituting the gate control circuit can be reduced. Further, the clock signal for driving the bootstrap circuit is an external input signal, so that high speed operation is possible.

  Further, according to the present invention, the timing margin of the timing generation unit in the gate control circuit can be expanded, and the requirement for high-speed operation can be relaxed. This is because a timing margin of a clock half cycle period is given to the signal transmission of the timing generation unit, and the output rise time of the timing generation unit is not directly reflected in the output fall time of the shift register circuit.

  Further, according to the present invention, it is possible to suppress a decrease in reliability due to a threshold shift of the transistor. This is because a voltage synchronized with the two-phase clock signal is applied to the gate terminal of the output transistor by the gate control circuit, so that the output transistor can be prevented from conducting for a long period of time and the threshold shift can be mitigated.

  Further, according to the present invention, it is possible to suppress the load and power consumption of the clock signal. This is because the inversion of the output Q2 [n] of the gate control circuit is limited to about once per frame in which one gate line is driven. In other words, the number of times of charge / discharge of the gate load capacitance of the output transistor M1 whose gate terminal is controlled by Q2 [n] is limited, and the load and power consumption of the clock signal for performing the charge / discharge are suppressed.

  In the matrix type display device equipped with the gate driver of the present invention, a display device with a narrow frame is possible. This is because the timing generation unit, which is a component of the gate driver arranged around the display screen, can be reduced in area, and since there are two clock signal lines for driving the gate driver, the wiring layout area can be reduced. Because it can.

  In the matrix type display device of the present invention, since there are only two clock signals having a high amplitude of the gate potential, the number of level shift circuits for generating a high amplitude signal can be reduced, and the member cost can be suppressed.

1 is a circuit diagram of a shift register circuit according to a first embodiment of the present invention. FIG. 3 is a timing chart illustrating operation waveforms of the shift register circuit according to the first embodiment of the present invention. 1 is a circuit diagram of a gate control circuit according to a first embodiment of the present invention. It is a timing chart figure which shows the operation | movement waveform of the gate control circuit of the 1st Embodiment of this invention. It is a circuit diagram of the gate control circuit of the 2nd Embodiment of this invention. It is a timing chart figure which shows the operation | movement waveform of the gate control circuit of the 2nd Embodiment of this invention. It is a circuit diagram of the shift register circuit of the 3rd Embodiment of this invention. It is a timing chart figure which shows the operation | movement waveform of the shift register circuit of the 3rd Embodiment of this invention. It is a circuit diagram of the gate driver of the 4th Embodiment of this invention. It is a circuit diagram of the gate control circuit of the 5th Embodiment of this invention. It is a timing chart figure which shows the operation waveform of the gate control circuit of the 5th Embodiment of this invention. It is a circuit diagram of the shift register circuit of the 6th Embodiment of this invention. It is a timing chart figure which shows the operation waveform of the shift register circuit of the 6th Embodiment of this invention. It is a circuit diagram of the gate driver of the 7th Embodiment of this invention. It is a figure which shows the matrix type display apparatus of the 8th Embodiment of this invention. It is a timing chart figure which shows the operation waveform of the gate driver in the matrix type display apparatus of the 8th Embodiment of this invention. It is a circuit diagram of a conventional shift register circuit. It is a timing chart which shows the operation waveform of the conventional shift register circuit.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a diagram illustrating a configuration of a shift register circuit according to the first embodiment. As shown in FIG. 1, the shift register circuit 1 according to the present embodiment is a shift register circuit composed of a single conductivity type (N-type in this embodiment) transistor, and includes a first power supply VSS and a shift register circuit. The output transistor M1 connecting the output O [n] of the register circuit 1, the output transistor M2 connecting the second power supply VDD and the output O [n] of the shift register circuit 1, and the gate terminal of the output transistor M2 A shift register unit 2 composed of a transistor M3 connecting the output P [n] and the output O [n-1] of the preceding shift register circuit, and a gate control circuit 3 having its output connected to the gate terminal of the output transistor M1 Consists of. The gate control circuit 3 includes a timing generation unit 5 and a buffer unit 4.

  In order to explain the operation of the shift register circuit 1, operation waveforms are shown in FIG. If the output O [n−1] of the shift register circuit 1 is at a low level, the output P [n] of the bootstrap node is fixed at a low level by the transistor M3 when the level of the clock signal XCLK is inverted from low to high. The output transistor M2 becomes non-conductive. On the other hand, when the output Q [n] of the gate control circuit 3 becomes a high level, the output transistor M1 becomes conductive, and the output O [n] of the shift register circuit 1 is fixed at a low level (first power supply VSS). .

  After the output O [n−1] of the shift register circuit 1 is inverted to the high level, when the clock signal XCLK is inverted to the high level, the output P [n] of the node rises toward the high level, and the output transistor M2 The voltage between the gate and the source is increased, so that the output transistor M2 becomes conductive. Then, by supplying a current from the second power supply VDD, the level of the output O [n] of the shift register circuit 1 rises to the second power supply VDD. Due to the bootstrap effect, the potential of the node output P [n] is It reaches even more than the second power supply VDD. At this time, the output transistor M1 is preferably in a non-conducting state so as not to disturb an increase in output and to prevent a through current from flowing from the second power supply VDD to the first power supply VSS. The timing generator 5 generates a signal so that the output Q [n] is kept at a low level.

  After the output O [n−1] of the shift register circuit 1 is inverted to the low level again, when the clock signal XCLK is inverted to the high level, the output P [n] of the node is fixed to the low level. It becomes conductive. On the other hand, when the output Q [n] of the gate control circuit 3 is inverted again to the high level, the output O [n] of the shift register circuit 1 falls to the first power supply VSS that is at the low level via the output transistor M1. It is done.

  Next, the gate control circuit 3 of the present embodiment will be described in detail with reference to FIG.

  First, the buffer unit 4 constituting the gate control circuit 3 will be described. The buffer unit 4 connects at least the transistor M11 that connects the output Q [n] of the gate control circuit 3 and the clock signal XCLK, the input terminal Q1 of the buffer unit 4 and the gate terminal Q2 of the transistor M11, and the clock signal CLK. This is a bootstrap circuit that includes a transistor M12 that is gate-controlled, and a transistor M13 that connects the output Q [n] of the gate control circuit 3 and the first power supply VSS and is gate-controlled by a clock signal CLK. Here, the clock signals XCLK and CLK are two-phase clock signals that are opposite to each other. Note that a capacitor C2 may be provided between the gate and the source terminal of the transistor M11 in order to enhance the bootstrap effect of the transistor M11.

  Next, the timing generation unit 5 constituting the gate control circuit 3 will be described. The timing generation unit 5 is gate-controlled by the input O [n−2] of the gate control circuit 3, and includes a transistor M 14 that connects the first power supply VSS and the output Q 1 of the timing generation unit 5, and an output Q 1 of the timing generation unit 5. And a capacitor C1 connecting the clock signal CLK.

  The operation of the gate control circuit 3 shown in FIG. 3 will be described below based on the operation waveform shown in FIG. When the input of the gate control circuit 3, that is, the output O [n-2] of the preceding shift register circuit is at a low level, the output Q1 of the timing generation unit 5 is synchronized with the clock signal CLK by coupling by the capacitor C1. To do. In a period T1 in which the clock signal CLK and the output Q1 of the timing generator 5 are at a high level, the gate Q2 of the transistor M11 is pulled up to a potential lower than the high level by the threshold voltage of the transistor M12 via the transistor M12. This potential is held by the capacitor C2. On the other hand, since the clock signal XCLK is at the low level, the output Q [n] of the gate control circuit 3 is fixed to the low level via the transistor M11. Similarly, the output Q [n] of the gate control circuit 3 is also fixed to the low level by the transistor M13.

  Next, when the clock signal is inverted and a period T2 in which CLK changes to a low level and XCLK changes to a high level, the transistors M12 and M13 are turned off. On the other hand, the transistor M11 is kept conductive by the potential difference held between the capacitor C2 and the gate-source capacitor of the transistor M11, and the potential of the gate Q2 of the transistor M11 rises above the high level of the clock signal due to the bootstrap effect. The output Q [n] of the gate control circuit 3 rises to the high level of the clock signal XCLK. When the clock signal is inverted again during the period T3, the output Q [n] of the gate control circuit 3 is pulled down to a low level by the transistors M11 and M13. That is, the buffer unit 4 functions as a bootstrap circuit that outputs the clock signal XCLK via the transistor M11. This operation is repeated while the output O [n-2] of the preceding shift register circuit is at the low level.

  On the other hand, in the period T4 when the output O [n-2] of the preceding shift register circuit is at a high level, the transistor M14 continues to be conductive, so that the output Q1 of the timing generator 5 is synchronized with the clock signal CLK. Without being fixed at a low level. In the period T5 when the clock signal CLK is at the high level, the node Q2 of the buffer unit 4 is fixed at the low level via the transistor M12. Therefore, the clock signal XCLK that is the drain terminal of the transistor M11 is at the low level and the output Q [n] of the gate control circuit 3 that is the source terminal is also at the low level, but Q2 that is the gate terminal is also at the low level. Keep continuity. In addition, no charge is charged in the gate-source capacitance and the gate-drain capacitance of the transistor M11. For this reason, in the period T6, when the clock signal XCLK is inverted and rises to a high level, the bootstrap effect does not work, and the gate terminal Q2 and the source terminal of the transistor M11 do not follow the clock signal CLK. This operation continues while the output O [n-2] of the preceding shift register is at the high level, and the output Q [n] of the gate control circuit 3 remains at the low level. Further, in the period T5 when the clock signal CLK is inverted to the high level, the node Q1 rises momentarily due to the coupling with the capacitor C1, or the charge charged in the capacitor C2 is discharged, and the node Q2 goes to the low level. Even if the lowering operation is gradual, the bootstrap effect does not work in the period T6 if each is lowered to the low level before the period T6 starts.

  The output Q [n] of the gate control circuit 3 shown in FIG. 3 matches the output Q [n] of the gate control circuit 3 shown in FIG. 1, and the output O [n] of the nth shift register circuit. When the voltage rises to a high level, the output transistor M1 is turned off so that it does not interfere with the desired waveform. Further, the waveform is generated by the timing generator 5 shown in FIG.

  In this way, the gate control of the output transistor to bring down the potential of the gate line at high speed is performed by the clock-driven bootstrap circuit that is a buffer part, so that driving of a large load is avoided and power consumption such as through current is avoided. And can be done at high speed. In addition, since the bootstrap circuit is used as a buffer unit, the transistor size and capacitance size of the timing generation unit 5 constituting the gate control circuit 3 can be reduced, and the gate control circuit 3 can be saved in area. Further, by using a clock signal for driving the bootstrap circuit as an external input signal, high-speed operation is possible.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIG. The difference from the first embodiment is the configuration of the timing generation unit 5. The timing generation unit 5 is gate-controlled by the input O [n−2] of the gate control circuit 3, and includes a transistor M15 that connects the first power supply VSS and the output Q1 of the timing generation unit 5, and an output Q1 of the timing generation unit 5. And a second power supply VDD, and a transistor M16 whose gate terminal is connected to the second power supply VDD.

  The operation of the gate control circuit 3 shown in FIG. 5 will be described below based on the operation waveform shown in FIG. When the input of the gate control circuit 3, that is, the output O [n-2] of the preceding shift register circuit is at the low level, the output Q1 of the timing generation unit 5 is driven from the high level by the diode-connected transistor M15. Is kept at a high level which is lower by the threshold voltage of the transistor M15. On the other hand, when the output O [n-2] of the preceding shift register circuit is at a high level, the output Q1 of the timing generation unit 5 is kept at a low level. That is, the timing generator 5 functions as an inverter that outputs an inverted signal of the input O [n-2] of the gate control circuit 3.

  When the output Q1 of the timing generator 5 is kept at a high level and the clock signal CLK is at a high level, the gate Q2 of the transistor M11 is pulled up to a potential lower than the high level by about the threshold voltage of the transistor M12 via the transistor M12. It is done. On the other hand, since the clock signal XCLK is at the low level, the output Q [n] of the gate control circuit 3 is fixed to the low level via the transistor M11. Similarly, the transistor M13 is also fixed to the low level. Next, when the clock signal is inverted and CLK changes to a low level and XCLK changes to a high level, the transistors M12 and M13 are turned off. On the other hand, the transistor M11 is kept in a conductive state, and due to the bootstrap effect, the potential of the gate Q2 of the transistor M11 rises above the high level of the clock signal, and the output Q [n] of the gate control circuit 3 becomes the high level of the clock signal XCLK. Rise to level. When the clock signal is inverted again, the output Q [n] of the gate control circuit 3 is lowered to the low level by the transistors M11 and M13. This operation is repeated while the output O [n-2] of the preceding shift register circuit 1 is at the low level.

  On the other hand, when the output Q1 of the timing generation unit 5 is kept at the low level, the node Q2 of the buffer unit 4 is fixed to the low level via the transistor M12 when the clock signal CLK is at the high level. Therefore, the clock signal XCLK that is the drain terminal of the transistor M11 is at the low level and the output Q [n] of the gate control circuit 3 that is the source terminal is also at the low level, but Q2 that is the gate terminal is also at the low level. Keep continuity. In addition, no charge is charged in the gate-source capacitance and the gate-drain capacitance of the transistor M11. Therefore, even when the clock signal XCLK is inverted and rises to a high level, the bootstrap effect does not work and the gate terminal Q2 and the source terminal of the transistor M11 do not follow. This operation continues while the output O [n-2] of the preceding shift register circuit 1 is at a high level, and the output Q [n] of the gate control circuit 3 remains at a low level.

  A feature of this embodiment is that a clock-driven bootstrap circuit is provided as a buffer unit 4 in the gate control circuit 3 that controls the gate of the output transistor of the shift register circuit 1. As a result, the gate control circuit 3 can output the clock signal via the transistor M11 without reducing the amplitude and without delay.

  Among the known examples described in the prior art, there is disclosed an example in which the gate control circuit 3 is configured only by the timing generation unit 5 of the present invention. That is, there is an example in which the timing generation unit 5 composed of the capacitor and the transistor shown in FIG. 3 or the timing generation unit 5 using the inverter shown in FIG. 5 is directly connected to the gate of the output transistor of the shift register circuit. Patent Document 3 and Non-Patent Document 1 disclose the above. Driving the output transistor M1 of the shift register circuit 1, especially making it conductive means charging the gate capacitance load Cg and setting the gate potential to a high potential. For high-speed operation, the gate capacitance load Cg has a high speed. In addition, charging to a high potential is required.

  When the output transistor M1 of the shift register circuit 1 is directly driven by the timing generation unit 5 including the capacitor C1 and the transistor M14 shown in Patent Document 3, the potential deterioration of the gate charging voltage becomes a problem. That is, since the gate charging potential is determined by the voltage division ratio of the capacitance C1 of the timing generation unit 5 and the gate capacitance Cg of the output transistor M1, C1 >> Cg is required to obtain a high voltage. In order to obtain the capacitance C1, a layout area larger than that of the output transistor M1 is required.

  In addition, when using the timing generation unit 5 including the inverters (transistors M15 and M16 in FIG. 5) shown in Non-Patent Document 1, current consumption becomes a problem. That is, in order to charge the gate capacitance load Cg at high speed, the transistor M16 needs to be large in size so that a large current can flow. On the other hand, when the transistor M15 is turned on, a through current flows between the second power supply VDD and the first power supply VSS via the transistors M16 and M15. In order to set the gate potential of the output transistor M1 to the low level, the size relationship between the transistors M16 and M15 requires M15> M16. Therefore, it cannot be avoided that a large through current flows through the large-sized transistors M15 and M16.

  Similarly, an example in which the buffer unit 4 is an inverter is shown in FIG. That is, this is an example in which the inverter configured by the transistors T13 and T14 is the buffer unit 4 and the circuit configured by the transistors T11b and T12b is the timing generation unit 5. The problem here is that a large through current flows through the inverter in the same manner as in Non-Patent Document 1, in order to charge the gate capacitive load of the transistor T16 at high speed with an inverter having the output B point connected to the gate terminal of the transistor T16. is there.

  As in a known example, when the gate of the output transistor M1 of the shift register circuit 1 is directly driven by the output of the timing generator 5, there is a problem in the timing margin during high-speed operation in addition to the above. That is, the inversion of the input signal of the timing generation unit 5 directly leads to the inversion of the gate potential of the output transistor of the shift register circuit 1. Therefore, an operation delay is not allowed in the timing generation unit 5.

  On the other hand, in the present invention, the gate potential of the output transistor is inverted by the clock-driven bootstrap buffer unit 4. The timing generation unit 5 performs the inversion operation in the period T5 before the half clock cycle, and it is sufficient that the inversion is completed before moving to the period T6 in which the buffer unit 4 operates. An operating margin is allowed. Thus, since the output rise time of the timing generation unit 5 is not directly reflected in the output fall time of the shift register circuit 1, the requirement for high-speed operation can be relaxed.

[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to FIG. The present embodiment is a shift register circuit configured by a single conductivity type transistor, and is configured as follows. The output transistor M1 that connects the output O [n] of the shift register circuit 1 and the first power supply VSS and the output O [n-2] of the shift register circuit 1 are input, and the output Q [n] is used as the output transistor M1. The first gate control circuit 3 connected to the gate terminal of the first register, the second output transistor M4 that connects the output O [n] of the shift register circuit 1 and the first power supply VSS, and the output O [ n-1] as an input, and a second gate control circuit 3 having an output Q [n + 1] connected to the gate terminal of the output transistor M4. Furthermore, the output transistor M2 that connects the output O [n] of the shift register circuit 1 and the second power supply VDD, the gate terminal P [n], and the output O [n−1] of the shift register circuit 1 are connected, The transistor M3 is gate-controlled by the clock signal XCLK. Here, it is assumed that the shift register circuits 1 of a plurality of stages are connected in the order of outputs O [n-2], O [n-1], and O [n]. The first and second gate control circuits 3 may have the same configuration as the gate control circuit 3 described in the first or second embodiment. The difference between the present embodiment and the first embodiment is that an output transistor M4 and a second gate control circuit 3 for controlling the output transistor M4 are added.

  The operation of the present embodiment will be described using the operation waveforms shown in FIG. The output Q [n] of the first gate control circuit 3 and the output Q [n + 1] of the second gate control circuit 3 are synchronized with the clock signal XCLK while the respective input signals are at the low level, and are shifted by a half cycle. Clock signal. That is, the buffer unit constituting the first gate control circuit 3 serves as a bootstrap circuit that outputs the clock signal XCLK, and the buffer unit constituting the second gate control circuit 3 serves as a bootstrap circuit that outputs the clock signal CLK. . As a result, either one of the output transistors M1 or M4 becomes conductive, and the output O [n] of the shift register circuit 1 is fixed at a low level. On the other hand, when the input signal is inverted to the high level, the outputs Q [n] and Q [n + 1] of the gate control circuit 3 are fixed to the low level, so that the output O [n] of the shift register circuit 1 is the output transistors M1 and M4. Therefore, it is not fixed at the low level. Meanwhile, the output transistors M2 and M3 of the shift register unit 2 function, and the output O [n] of the shift register circuit 1 is inverted to a high level. Details thereof are the same as those in the first embodiment.

  According to the present embodiment, the output O [n] of the shift register circuit 1 is stably fixed at the low level by the two gate control circuits 3 except for the period when the output O [n] of the shift register circuit 1 is set to the high level. A shift register is provided.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described with reference to FIG. This embodiment is a gate driver 10 in which a plurality of stages of the shift register circuit 1 of the third embodiment are connected, and the output O of the shift register circuit 1 in the (n-2) th stage (n is an integer of 3 or more). [N-2] is input to the shift register unit 2 and the gate control circuit 3 in the (n-1) th stage, and the output Q [n] of the gate control circuit 3 in the (n-1) th stage is the (n-1) th. The signals are input to the shift register unit 2 at the stage and the shift register unit 2 at the nth stage. That is, the output Q [n] of the gate control circuit 3 is shared by two consecutive shift register units 2. With this configuration, the circuit scale of the gate driver can be reduced. This is because the one-stage shift register circuit 1 shown in FIG. 7 describes two gate control circuits 3, but by sharing the gate control circuit 3 between a plurality of successive shift register circuits 1, This is because the number of gate control circuits 3 can be reduced.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described with reference to FIG. The present embodiment is a gate control circuit in which a second output Q2 [n] is added to the buffer unit 4 of the gate control circuit 3 shown in the first embodiment. Hereinafter, an additional part of the gate control circuit 3 shown in FIG. 10 will be described. The buffer unit 4 includes at least a transistor M17 that connects the second output Q2 [n] of the gate control circuit 3 and the first power supply VSS, a second output Q2 [n], and a first output Q [n. ], A transistor M19 that connects the gate terminal of the transistor M18 and the output O [n + 2] of the (n + 2) -th shift register is added, and the gate terminal of the transistor M17 is controlled by the clock signal CLK.

  The operation of the gate control circuit 3 shown in FIG. 10 will be described below based on the operation waveform shown in FIG. In the period T0 in which the output O [n + 2] of the later-stage shift register circuit is at the high level, the gate and drain of the transistor M19 are at the high level, so that the source terminal Q3 is lower than the high level by about the threshold voltage. The potential is raised, and the transistor M18 becomes conductive. However, since the first output Q [n] is at a low level during the period T0, the second output Q2 [n] is also at a low level via the transistor M18.

  Next, in a period T1, when the clock signal is inverted and CLK changes to a high level and XCLK changes to a low level, Q [n] and Q2 [n] are connected to the first power supply VSS by the conduction of the transistors M13 and M17. Fixed to low level continues.

  Next, in a period T2, when the clock signal is inverted and CLK changes to a low level and XCLK changes to a high level, the output Q [n] rises to the high level of the clock signal XCLK. Accordingly, the second output Q2 [n], which is the source terminal of the transistor M18 that has been kept conductive, is also raised to a high level. At this time, the level of Q3 which is the gate terminal of the transistor M18 rises to a high level or higher due to the bootstrap effect, but the rise of the transistor M19 cannot be prevented. This is because the source terminal of the transistor M19 is switched to the subsequent shift register output O [n + 2], the drain terminal is switched to Q3, and the gate terminal and the source terminal are at the same high level, so that the transistor M19 becomes non-conductive. Because.

  Next, in a period T3, when the clock signal is inverted and CLK changes to a high level and XCLK changes to a low level, Q [n] and Q2 [n] are connected to the first power supply VSS by the conduction of the transistors M13 and M17. Fixed to low level.

  After the period T3, the output O [n + 2] of the shift register circuit in the subsequent stage becomes low level, so that the transistor M19 is turned on, so that the gate terminal Q3 of the transistor M18 is fixed to the low level, and the transistor M18 is turned off. Therefore, the second output Q2 [n] does not rise to the high level in synchronization with the first output Q [n], and is sequentially reset to the low level by the transistor M17 and the clock signal CLK.

  The second output Q2 [n] of the gate control circuit 3 shown in FIG. 10 can be used instead of Q [n] for the gate of the transistor M1 of the shift register portion shown in FIG. That is, Q2 [n] is a sufficient signal as a gate signal for making the output transistor M1 conductive so that the output O [n] of the nth shift register circuit is inverted to a low level.

  The advantage of using Q2 [n] instead of Q [n] is a reduction in clock signal load and power consumption. An output transistor for rapidly lowering the potential of the gate line is a transistor having a large channel size and a large gate capacitance. Therefore, a large amount of power is required to charge and discharge the gate capacitance load of the output transistor. When Q [n] is used for the gate control of the output transistor, the gate capacitance load is also synchronized with the clock signal at a timing other than when the gate line potential is lowered, that is, when the gate line potential is fixed at a low level. Charge and discharge. Electric power for this purpose is supplied from the clock signal through the gate control circuit 3, and the load on the clock signal increases.

  On the other hand, when Q2 [n] is used for gate control of an output transistor having a large gate capacitance load, charging / discharging of the gate capacitance load is limited to a period T2 during which the potential of the gate line is lowered as shown in FIG. Since it is not synchronized with the clock signal in other periods, the gate capacitance load is not charged / discharged, and no power is supplied from the clock signal. By reducing the number of times of charge / discharge of the large gate capacitance load of the output transistor, the load of the clock signal and the power consumption can be reduced.

[Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described with reference to FIG. In the present embodiment, an output transistor M5 that connects the output O [n] of the shift register circuit 1 and the first power supply VSS is added, and gate control of the output transistors M1, M4, and M5 is performed according to the first embodiment. This is different from the third embodiment in that the gate control circuit according to the fifth embodiment is used instead of the gate control circuit. The gate control of the output transistor M1 is the second output Q2 [n] of the first gate control circuit, the gate control of the output transistor M4 is the first output Q [n + 1] of the second gate control circuit, and the output transistor The gate control of M5 is performed by the first output Q [n] of the first gate control circuit.

  The operation of this embodiment will be described using the operation waveforms shown in FIG. This embodiment is different from the third embodiment in that the output transistor M1 is gate-controlled by the second output Q2 [n] of the first gate control circuit 3. The second output Q2 [n] is characterized in that it is synchronized with the first output Q [n] while the input signal O [n + 2] is at a high level. That is, Q2 [n] is inverted to high level only when the output O [n] of the shift register circuit falls from high level to low level. The output transistor M1 gated by Q2 [n] is turned on only when the output O [n] falls. On the other hand, the output transistors M4 and M5 gated by the first outputs Q [n] and Q [n + 1] of the first and second gate control circuits 3 are periods in which the output O [n] does not output a high level. Is conductive, and the output O [n] is fixed to the low level.

  Regarding the channel size of the output transistor, the output transistor M1 requires a large channel width in order to cause the gate line potential to fall at high speed. However, the output transistors M4 and M5 may fix the gate line potential to a low level. For purposes, a large channel width is not necessary.

[Seventh Embodiment]
Next, a seventh embodiment of the present invention will be described with reference to FIG. The present embodiment is a gate driver 10 in which the shift register circuit 1 of the fifth embodiment is connected in a plurality of stages. The output O [n−2] of the shift register circuit 1 in the (n−2) th stage (n is an integer of 3 or more) is used as the input of the shift register unit 2 and the gate control circuit 3 in the (n−1) th stage. The first output Q [n] of the (n−1) th stage gate control circuit 3 is input to the n−1th stage shift register unit 2 and the nth stage shift register unit 2 respectively. Further, the second output Q2 [n] of the (n−1) th stage gate control circuit 3 is inputted to the nth stage shift register section 2. That is, the output Q [n] of the gate control circuit 3 is shared by two consecutive shift register units 2. With this configuration, the circuit scale of the gate driver can be reduced. This is because, in the shift register circuit 1 for one stage shown in FIG. 12, two gate control circuits 3 are described, but by sharing the gate control circuit 3 among a plurality of successive shift register circuits 1. This is because the number of gate control circuits 3 can be reduced.

[Eighth Embodiment]
Next, an eighth embodiment of the present invention will be described with reference to FIGS. This embodiment is a matrix type display device 15 on which the gate driver 10 of the fourth embodiment or the seventh embodiment is mounted. As shown in FIG. 15, a plurality of gate lines 13 and a plurality of data lines 14 are provided. And a plurality of gate lines G1, G2,... Of a pixel array (display unit) 11 composed of pixel elements arranged at the intersections thereof, outputs O [1] and O [2] of the gate driver 10 described above. , ... are connected. The gate driver 10 receives a two-phase clock signal CLK and XCLK, and inputs a start signal ST as an input to the first-stage shift register circuit 1 of the gate driver 10. The gate driver 10 operates like the waveform shown in FIG. 16, and performs overlap scanning having a period in which a plurality of continuous gate lines 13 are simultaneously selected (becomes high level). The selection period of each gate line 13 is controlled by the pulse width of the start signal ST. The time difference between the gate line selection periods is controlled by the half cycle of the clock signals CLK and XCLK.

  In the matrix display device of this embodiment, since there are only two clock signals having a high amplitude of the gate potential, the number of level shift circuits that generate a high amplitude signal can be reduced, and the member cost can be suppressed. In addition, the wiring layout area of the clock signal line can be reduced, and a display device with a narrow frame is possible.

  Note that the present invention is not limited to the above-described embodiment, and can be modified as appropriate without departing from the spirit of the present invention. For example, the transistors described in the embodiments are limited to N-type transistors, but may be replaced with P-type transistors. Each of the transistors may be a polycrystalline silicon transistor, an amorphous silicon transistor, an oxide semiconductor other than silicon, It may be an organic semiconductor.

  The present invention can be used for a shift register circuit, a gate driver including the shift register circuit, and a display device including the gate driver.

DESCRIPTION OF SYMBOLS 1 Shift register circuit 2 Shift register part 3 Gate control circuit 4 Buffer part 5 Timing generation part 10 Gate driver 11 Pixel array (display part)
12 data driver 13 gate line 14 data line 15 matrix type display device CLK, XCLK clock signal VSS first power supply VDD second power supply M1, M2, M3, M4, M5, M11, M12, M13, M14, M15, M16 , M17, M18, M19 Transistors C1, C2 Capacitance O [n], O [n-1], O [n-2] Shift register output P [n] Bootstrap node Q [n], Q [n + 1] Gate control Circuit output ST Start signal Q2 [n], Q2 [n + 1] Gate control circuit second output

Claims (13)

A shift register circuit composed of a single conductivity type transistor,
A shift register unit having a first output transistor connecting the output terminal and the first power supply;
A first gate control circuit having an output terminal connected to the gate terminal of the first output transistor;
The first gate control circuit includes a timing generation unit and a buffer unit,
The buffer unit is a bootstrap circuit,
An output of the timing generation unit to which an input signal is input is an input of the buffer unit, and an output of the buffer unit is an output of the first gate control circuit. The buffer unit is at least
A second transistor connecting the output of the buffer unit and the first clock signal;
The shift register circuit according to claim 1, wherein the shift register circuit is a bootstrap circuit including a third transistor that connects a gate terminal of the second transistor and an output of the timing generation unit. The buffer unit is at least
The second transistor for connecting the output of the buffer unit and the first clock signal;
A third transistor connected between a gate terminal of the second transistor and an output of the timing generator and gate-controlled by a second clock signal;
3. The shift according to claim 2, wherein the shift is a bootstrap circuit that includes a fourth transistor that connects an output of the buffer unit and the first power supply and is gate-controlled by the second clock signal. Register circuit. The timing generator
A fifth transistor that is gate-controlled by an input of the first gate control circuit and connects the first power supply and the input of the buffer;
The shift register circuit according to claim 3, comprising a first capacitor that connects an input of the buffer unit and the second clock signal. The timing generator
A sixth transistor that is gate-controlled by the input of the gate control circuit and connects the first power supply and the input of the buffer;
4. The shift register circuit according to claim 3, comprising: a seventh transistor that connects an input of the buffer unit to a second power supply and has a gate terminal connected to the second power supply. 5. The shift register unit is
An eighth output transistor having a source terminal connected to the output terminal of the shift register circuit and a drain terminal connected to the second power supply;
And a ninth transistor having a gate terminal for inputting the first clock signal, a drain terminal for inputting an input signal, and a source terminal connected to the gate terminal of the eighth output transistor. Item 4. The shift register circuit according to Item 1. A shift register circuit comprising the single conductivity type transistor according to claim 1,
The shift register unit includes a tenth output transistor that connects the output terminal and the first power source;
A second gate control circuit having an output terminal connected to the gate terminal of the tenth output transistor;
The second gate control circuit includes a timing generation unit and a buffer unit;
An output of the timing generation unit to which an input signal is input is an input of the buffer unit, and an output of the buffer unit is an output of the second gate control circuit. The buffer unit constituting the first gate control circuit is a bootstrap circuit that outputs the first clock signal according to claim 2, and the buffer unit constituting the second gate control circuit is claim 3. The shift register circuit according to claim 7, which is a bootstrap circuit that outputs the second clock signal according to claim 8. A gate driver in which a plurality of stages of the shift register circuit according to claim 7 are connected,
The output of the shift register circuit at the (n-2) th stage (where n is an integer of 3 or more) is used as the input of the shift register unit at the (n-1) th stage and the first or second gate control circuit,
The output of the first or second gate control circuit at the (n−1) th stage is used as the input to the shift register section at the (n−1) th stage and the shift register section at the nth stage. A gate driver. The buffer unit of the gate control circuit has at least a second output;
An eleventh transistor connecting the second output of the buffer unit and the first power supply;
A twelfth transistor connecting the second output of the buffer unit and the first output of the buffer unit;
A thirteenth transistor connecting the gate terminal of the twelfth transistor and the output of the (n + 2) th stage shift register;
The eleventh transistor is controlled by the second clock signal;
The shift register circuit according to claim 3, wherein the thirteenth transistor is a bootstrap circuit controlled by the second power supply. 11. A shift register circuit comprising the gate control circuit according to claim 10, wherein the second output terminal is connected to the gate terminal of the first output transistor. A gate driver in which a plurality of stages of the shift register circuit according to claim 10 are connected,
The output of the shift register circuit of the (n-2) th stage (n is an integer of 3 or more) is used as the input of the shift register unit and the gate control circuit of the (n-1) th stage,
The output of the (n + 2) th stage shift register circuit is used as the input of the (n-1) th stage gate control circuit,
The first output of the (n−1) th stage gate control circuit is used as an input to the (n−1) th stage shift register unit and the nth stage shift register unit,
The gate driver, wherein the second output of the gate control circuit at the (n-1) th stage is used as an input of the shift register unit at the nth stage. A matrix type display device equipped with the gate driver according to claim 9 or 12,
A display portion in which pixel elements are arranged at intersections of a plurality of gate lines and a plurality of data lines,
Connecting the output of the gate driver to the gate line;
Overlap scanning having a period for simultaneously selecting a plurality of gate lines,
The display device, wherein a selection period of the gate line is controlled by a pulse width of a start signal.

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