CN108389545A - Shift register cell, driving method, gate driving circuit and display device - Google Patents
Shift register cell, driving method, gate driving circuit and display device Download PDFInfo
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- CN108389545A CN108389545A CN201810247827.0A CN201810247827A CN108389545A CN 108389545 A CN108389545 A CN 108389545A CN 201810247827 A CN201810247827 A CN 201810247827A CN 108389545 A CN108389545 A CN 108389545A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Shift Register Type Memory (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of shift register cell, driving method, gate driving circuit and display devices, belong to display technology field.The shift register cell includes input module, keeps module, output module, reseting module and pull-down module.Wherein, after input module provides the input signal in the first current potential, it keeps module and can control the current potential of the second pull-up node to be the first current potential, so that when the current potential for the clock signal that clock signal terminal exports is the first current potential, the transistor of output module can keep the state effectively opened under the control of second pull-up node, the clock signal is exported as drive signal to output end in time, and since the current potential of second pull-up node in the output stage is relatively stable, the load of output end will not be increased, therefore it can ensure that the potential change of the drive signal of output module output is shorter to the duration of the first current potential, it can ensure in time to charge to each pixel in display area, improve display quality.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of shift register cell, driving method, gate driving electricity
Road and display device.
Background technology
Shift register generally includes multiple cascade shift register cells, and each shift register cell is for driving
One-row pixels unit, by multiple cascade shift register cell may be implemented in display panel each row pixel unit by
Row turntable driving, to show image.
In the related technology, the input module of the shift register cell can control pull-up under the control of input signal
The current potential of node；Output module can be under the control of the pull-up node, to output end input clock signal.Wherein, the output
Capacitor and driving transistor are usually provided in module, the grid of the driving transistor is connect with pull-up node, the capacitor
Both ends connect respectively with pull-up node and output end, when the current potential of clock signal be high potential when, the capacitor due to bootstrapping
The current potential of pull-up node can be further pulled up by effect, and driving transistor is allow effectively to open, and when being inputted to output end
Clock signal charges as each pixel that drive signal is display area.
But in shift register cell in the related technology, the driving transistor in output module is needed in capacitor
Bootstrap effect under could effectively open, and output drive signal, the bootstrap effect can increase the load of output end, lead to the drive
The rise time of dynamic signal is longer, and then may lead to each pixel undercharge of display area, influences the display of display panel
Quality.
Invention content
The present invention provides a kind of shift register cell, driving method, gate driving circuit and display devices, can solve
Certainly in the related technology the display poor quality of display panel the problem of, the technical solution is as follows：
In a first aspect, providing a kind of shift register cell, the shift register cell includes：Input module, guarantor
Hold module, output module, reseting module and pull-down module；
The input module is connect with input signal end, first control signal end and the first pull-up node respectively, described defeated
Enter module under the control of the input signal from the input signal end, institute to be come to first pull-up node input
State the first control signal at first control signal end；
The holding module is connect with first pull-up node, the first power end and the second pull-up node respectively, described
It keeps module to be used under the control of first pull-up node, first power supply is come to second pull-up node input
First power supply signal at end, and keep the current potential of first pull-up node and second pull-up node；
The output module is connect with clock signal terminal, second pull-up node and output end respectively, the output mould
Block is used under the control of second pull-up node, and the clock letter from the clock signal terminal is inputted to the output end
Number；
The reseting module is connect with reset signal end, second control signal end and first pull-up node respectively,
The reseting module is used under the control of the reset signal from the reset signal end, is inputted to first pull-up node
Second control signal from the second control signal end；
The pull-down module respectively with first power end, second source end, first pull-up node, described second
Pull-up node is connected with the output end, and the pull-down module is used under the control of first power supply signal, respectively to institute
State the second source letter of the first pull-up node, second pull-up node and output end input from the second source end
Number.
Optionally, the holding module, including：The first transistor and capacitor；
The grid of the first transistor is connect with first pull-up node, the first pole of the first transistor and institute
The connection of the first power end is stated, the second pole of the first transistor is connect with second pull-up node；
One end of the capacitor is connect with first pull-up node, on the other end of the capacitor and described second
Draw node connection.
Optionally, the output module includes：Second transistor；
The grid of the second transistor is connect with second pull-up node, the first pole of the second transistor and institute
Clock signal terminal connection is stated, the second pole of the second transistor is connect with the output end.
Optionally, the pull-down module includes：Pull down control submodule and drop-down submodule；
The drop-down control submodule is saved with first power end, the second source end, first pull-up respectively
Point and pull-down node connection, are used under the control of first pull-up node, described in pull-down node input
First power supply signal；
The drop-down submodule respectively with the second source end, first pull-up node, second pull-up node,
The pull-down node and output end connection, under the control from the pull-down node, being pulled up to described first
Node, second pull-up node and the output end input the second source signal.
Optionally, the drop-down control submodule includes：Third transistor and the 4th transistor；The drop-down submodule packet
It includes：5th transistor, the 6th transistor and the 7th transistor；
The grid of the third transistor and first is extremely connect with first power end, and the of the third transistor
Two poles are connect with the pull-down node；
The grid of 4th transistor is connect with first pull-up node, the first pole of the 4th transistor and institute
The connection of second source end is stated, the second pole of the 4th transistor is connect with the pull-down node；
The grid of 5th transistor is connect with the pull-down node, the first pole of the 5th transistor and described the
Two power ends connect, and the second pole of the 5th transistor is connect with second pull-up node；
The grid of 6th transistor is connect with the pull-down node, the first pole of the 6th transistor and described the
Two power ends connect, and the second pole of the 6th transistor is connect with first pull-up node；
The grid of 7th transistor is connect with the pull-down node, the first pole of the 7th transistor and described the
Two power ends connect, and the second pole of the 7th transistor is connect with the output end.
Optionally, the input module, including：8th transistor；
The grid of 8th transistor is connect with the input signal end, the first pole of the 8th transistor with it is described
First control signal end connects, and the second pole of the 8th transistor is connect with first pull-up node.
Optionally, the reseting module includes：9th transistor；
The grid of 9th transistor is connect with the reset signal end, the first pole of the 9th transistor with it is described
Second control signal end connects, and the second pole of the 9th transistor is connect with first pull-up node.
Second aspect, provides a kind of driving method of shift register cell, and the shift register cell includes defeated
Enter module, keep module, output module, reseting module and pull-down module；The method includes：
The current potential of input phase, the input signal of input signal end output is the first current potential, and the input module is described
Under the control of input signal, to the first pull-up node input the first control signal from first control signal end, described first
The current potential for controlling signal is the first current potential, and the holding module is under the control of first pull-up node, to the second pull-up section
The current potential of first power supply signal of the point input from the first power end, first power supply signal is the first current potential, the output
Module inputs the clock signal from clock signal terminal, the clock under the control of second pull-up node, to output end
The current potential of signal is the second current potential；
The jump in potential in output stage, the clock signal is the first current potential, and the holding module is kept on described first
It is the first current potential, control of the output module in second pull-up node to draw the current potential of node and second pull-up node
Under system, the clock signal is inputted to output end；
The current potential of reseting stage, the reset signal of reset signal end output is the first current potential, first power supply signal
Current potential is the first current potential, and the reseting module comes under the control of the reset signal to first pull-up node input
The current potential of the second control signal at second control signal end, the second control signal is the second current potential, and the holding module exists
Under the control of first pull-up node, the current potential for controlling second pull-up node is the second current potential, and the pull-down module exists
Under the control of first power supply signal, respectively to first pull-up node, second pull-up node and the output end
The second source signal from second source end is inputted, the current potential of the second source signal is the second current potential.
The third aspect, provides a kind of gate driving circuit, and the gate driving circuit includes：As described in relation to the first aspect
Shift register cell；
Output end per level-one shift register cell respectively with the reset signal end of upper level shift register cell, with
And the input signal end connection of next stage shift register cell.
Fourth aspect, provides a kind of display device, and the display device includes：Gate driving as described in the third aspect
Circuit.
The advantageous effect that technical solution provided by the invention is brought is：
In conclusion an embodiment of the present invention provides a kind of shift register cell, driving method, gate driving circuit and
Display device, the wherein shift register cell include input module, keep module and output module, are provided in the input module
After input signal in the first current potential, the current potential which can control the second pull-up node is maintained at the first current potential,
So that when the current potential for the clock signal that clock signal terminal export for the first current potential when, transistor in output module can this
The state effectively opened is kept under the control of two pull-up nodes, exports the clock signal as drive signal to output end in time.
And since in the output stage, the current potential of second pull-up node is relatively stable, the load of output end will not be increased, therefore can
Potential change to ensure the drive signal of output module output is shorter to the duration of the first current potential, it is ensured that in time to aobvious
Show each pixel charging in region, to improve the display quality of display panel.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, other are can also be obtained according to these attached drawings
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of shift register cell provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of another shift register cell provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of another shift register cell provided in an embodiment of the present invention；
Fig. 4 is a kind of driving method flow chart of shift register cell provided in an embodiment of the present invention；
Fig. 5 is the sequential of the signal of each signal end output in a kind of shift register cell provided in an embodiment of the present invention
Figure；
Fig. 6 is a kind of structural schematic diagram of gate driving circuit provided in an embodiment of the present invention.
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention is implemented below in conjunction with attached drawing
Mode is described in further detail.
The transistor used in all embodiments of the invention all can be thin film transistor (TFT) or field-effect tube or other characteristics
Identical device is mainly switching transistor according to transistor used by effect the embodiment of the present invention in circuit.By
In the switching transistor used here source electrode, drain electrode be symmetrical, so its source electrode, drain electrode can be interchanged.In this hair
In bright embodiment, wherein it will be known as the first order by source electrode, drain electrode is known as the second level.The centre of transistor is provided by the form in attached drawing
End is grid, signal input part is source electrode, signal output end is drain electrode.In addition, switching crystal used by the embodiment of the present invention
Pipe may include any one of p-type switching transistor and N-type switching transistor, wherein p-type switching transistor is low in grid
Electric conducts end when grid is high level, and N-type switching transistor is connected when grid is high level, are low in grid
End when level.In addition, multiple signals in each embodiment of the present invention are all corresponding with the first current potential and the second current potential, the first electricity
The current potential that position only represents the signal with the second current potential has 2 different quantity of states, does not represent the first current potential or the second electricity in full text
Position has specific numerical value.
Fig. 1 is a kind of structural schematic diagram of shift register cell provided in an embodiment of the present invention, as shown in Figure 1, the shifting
Bit register unit may include：Input module 10 keeps module 20, output module 30, reseting module 40 and pull-down module 50.
The input module 10 can respectively with input signal end IN, first control signal end FW and the first pull-up node PU1
Connection, which can be defeated to the first pull-up node PU1 under the control of the input signal from input signal end IN
Enter the first control signal from first control signal end FW, the current potential of the first control signal is the first current potential, and this first
Current potential is effective current potential.
Exemplary, the current potential for the input signal that IN is exported at the input signal end is the first current potential, which can
Under the control of the input signal, the first control signal of the first current potential is in first pull-up node PU1 inputs.
With reference to figure 1, which can pull up with the first pull-up node PU1, the first power end VGH and second respectively
Node PU2 connections, the holding module 20 can be come under the control of the first pull-up node PU1 to the second pull-up node PU2 inputs
From the first power supply signal of the first power end VGH, and keep the current potential of the first pull-up node PU1 and the second pull-up node PU2.
First power end VGH is DC power supply terminal, and the current potential of first power supply signal is the first current potential.
It is exemplary, first pull-up node PU1 current potential be the first current potential when, the holding module 20 can this first
Under the control of pull-up node PU1, to the second first power supply signal of the pull-up node PU2 inputs in the first current potential.This second
The current potential of pull-up node PU2 is the first current potential, and (i.e. the first pull-up node PU1 is outstanding for the first pull-up node PU1 no signals input
It is empty) when, it is the first current potential which, which can keep the current potential of first pull-up node PU1,.Also, in first pull-up
When the current potential of node PU1 is the second current potential, which can be second in the current potential for making second pull-up node PU2
Current potential.
Output module 30 can be connect with clock signal terminal CLK, the second pull-up node PU2 and output end OUT respectively, this is defeated
The clock from clock signal terminal CLK can be inputted under the control of the second pull-up node PU2 to output end OUT by going out module 30
Signal.
It is exemplary, when the current potential of the second pull-up node PU2 is the first current potential, the output module 30 can this on second
Under the control for drawing node PU2, the clock signal from clock signal terminal CLK is inputted to output end OUT.
With reference to figure 1, the reseting module 40 can respectively with reset signal end RST, second control signal end BW and first
Pull-up node PU1 connections, the reseting module 40 can be under the controls of the reset signal from reset signal end RST, to first
Pull-up node PU1 inputs the second control signal from second control signal end BW, and the current potential of the second control signal is second
Current potential.
It is exemplary, when the current potential for the reset signal that RST is exported at the reset signal end is the first current potential, the reseting module 40
The second control signal of the second current potential can be in first pull-up node PU1 inputs under the control of the reset signal, from
And realize the reset to first pull-up node PU1.
The pull-down module 50 can respectively with the first power end VGH, second source end VGL, the first pull-up node PU1,
Two pull-up node PU2 are connected with output end OUT, which can be under the control of the first power supply signal, respectively to
One pull-up node PU1, the second pull-up node PU2 and output end OUT input the second source signal from second source end VGL,
The current potential of the second source signal is the second current potential.
Exemplary, when the current potential of the first pull-up node PU1 is the second current potential, which can be in first electricity
Under the control of source signal end, respectively to the first pull-up node PU1, the second pull-up node PU2 and output end OUT inputs in the second electricity
The second source signal of position, to realize the noise reduction to the first pull-up node PU1, the second pull-up node PU2 and output end OUT.
In conclusion shift register cell provided in an embodiment of the present invention includes input module, keeps module and output
Module, after the input module provides the input signal in the first current potential, which can control the second pull-up node
Current potential be maintained at the first current potential so that when clock signal terminal output clock signal current potential be the first current potential when, export mould
Transistor in the block can keep the state effectively opened under the control of second pull-up node, in time should to output end output
Clock signal is as drive signal.And since in the output stage, the current potential of second pull-up node is relatively stable, Bu Huizeng
Add the load of output end, therefore the potential change for the drive signal that the output module exports can be ensured to the duration of the first current potential
It is shorter, it is ensured that charge in time to each pixel in display area, to improve the display quality of display panel.
Fig. 2 is the structural schematic diagram of another shift register cell provided in an embodiment of the present invention, as shown in Fig. 2, should
Pull-down module 50 may include：Pull down control submodule 501 and drop-down submodule 502.
The drop-down control submodule 501 can respectively with the first power end VGH, second source end VGL, the first pull-up node
PU1 and pull-down node PD connections, the drop-down control submodule 501 can pull down section under the control of the first power supply signal
Point PD inputs the first power supply signal.
Exemplary, when the current potential of the first pull-up node PU1 is the second current potential, which can be
Under the control of the first power supply signal from the first power end VGH outputs, to pull-down node PD inputs in the first current potential
First power supply signal.
With reference to figure 2, the drop-down submodule 502 can respectively on second source end VGL, the first pull-up node PU1, second
Draw node PU2, pull-down node PD and output end OUT connections, the drop-down submodule 502 can be in the control from pull-down node PD
Under system, second source signal is inputted to the first pull-up node PU1, the second pull-up node PU2 and output end OUT.
Exemplary, which can be when the current potential of pull-down node PD be the first current potential, to the first pull-up
Node PU1, the second pull-up node PU2 and output end OUT input second source signal, to realize to first pull-up node
The noise reduction of PU1, the second pull-up node PU2 and output end OUT.
Fig. 3 is the structural schematic diagram of another shift register cell provided in an embodiment of the present invention, as shown in figure 3, should
Keep module 20 may include：The first transistor M1 and capacitor C.
The grid of the first transistor M1 is connect with the first pull-up node PU1, the first pole of the first transistor M1 and the
One power end VGH connections, the second pole of the first transistor M1 is connect with the second pull-up node PU2.
One end of capacitor C is connect with the first pull-up node PU1, the other end and the second pull-up node of capacitor C
PU2 connections.
In embodiments of the present invention, capacitor C can be the first current potential in the current potential of the second pull-up node PU2, and defeated
In the case of entering the transistor shutdown in module 10, i.e. when the first pull-up node PU1 no signals input, keep the first pull-up node
The current potential of PU1 is the first current potential.So that when the clock signal of clock signal terminal CLK outputs is the first current potential, the output
Module 30 can be under the control of the second pull-up node PU2, to export the clock signal to output end OUT in time.
Optionally, as shown in figure 3, the output module 30 may include：Second transistor M2.
The grid of second transistor M2 is connect with the second pull-up node PU2, the first pole of second transistor M2 and when
The CLK connections of clock signal end, the second pole of second transistor M2 are connect with output end OUT.
It should be noted that in embodiments of the present invention, capacitor, i.e. output end OUT is not arranged in the output module 30
It is not connect with capacitor, so as to avoid the bootstrap effect due to capacitor, the load of output end OUT increases and causes output
The problem of rise time and fall time of clock signal increase reduces the influence that clock signal is loaded to output end OUT.
Optionally, as shown in figure 3, the drop-down control submodule 501 may include：Third transistor M3 and the 4th transistor
M4.The drop-down submodule 502 may include：5th transistor M5, the 6th transistor M6 and the 7th transistor M7.
The grid of third transistor M3 and first extremely can be connect with the first power end VGH, third transistor M3
The second pole connect with pull-down node PD.
The grid of 4th transistor M4 is connect with the first pull-up node PU1, the first pole of the 4th transistor M4 and the
Two power end VGL connections, the second pole of the 4th transistor M4 is connect with pull-down node PD.
The grid of 5th transistor M5 is connect with pull-down node PD, the first pole of the 5th transistor M5 and second source
VGL connections are held, the second pole of the 5th transistor M5 is connect with the second pull-up node PU2.
The grid of 6th transistor M6 is connect with pull-down node PD, the first pole of the 6th transistor M6 and second source
VGL connections are held, the second pole of the 6th transistor M6 is connect with the first pull-up node PU1.
The grid of 7th transistor M7 is connect with pull-down node PD, the first pole of the 7th transistor M7 and second source
VGL connections are held, the second pole of the 7th transistor M7 is connect with output end OUT.
Optionally, as shown in figure 3, the input module 10 may include：8th transistor M8.
The grid of 8th transistor M8 is connect with input signal end IN, the first pole of the 8th transistor M8 and the first control
Signal end FW connections processed, the second pole of the 8th transistor M8 is connect with the first pull-up node PU1.
Optionally, as shown in figure 3, the reseting module 40 may include：9th transistor M9.
The grid of 9th transistor M9 is connect with reset signal end RST, the first pole and second of the 9th transistor M9
Control signal end BW connections, the second pole of the 9th transistor M9 is connect with the first pull-up node PU1.
In conclusion shift register cell provided in an embodiment of the present invention includes input module, keeps module and output
Module, after the input module provides the input signal in the first current potential, which can control the second pull-up node
Current potential be maintained at the first current potential so that when clock signal terminal output clock signal current potential be the first current potential when, export mould
Transistor in the block can keep the state effectively opened under the control of second pull-up node, in time should to output end output
Clock signal is as drive signal.And since in the output stage, the current potential of second pull-up node is relatively stable, Bu Huizeng
Add the load of output end, therefore the potential change for the drive signal that the output module exports can be ensured to the duration of the first current potential
It is shorter, it is ensured that charge in time to each pixel in display area, to improve the display quality of display panel.
Fig. 4 is a kind of driving method of shift register cell provided in an embodiment of the present invention, which can answer
For Fig. 1 to Fig. 3 it is any shown in shift register cell.With reference to figure 1, which includes input module
10, module 20, output module 30, reseting module 40 and pull-down module 50 are kept.With reference to figure 4, this method may include：
The current potential of step 401, input phase, the input signal of input signal end output is the first current potential, and input module exists
Under the control of input signal, the first control signal from first control signal end, the first control are inputted to the first pull-up node
The current potential of signal is the first current potential, keeps module under the control of the first pull-up node, to the input of the second pull-up node from the
The current potential of first power supply signal of one power end, the first power supply signal is the first current potential, and output module is in the second pull-up node
Under control, the clock signal from clock signal terminal is inputted to output end, the current potential of clock signal is the second current potential.
The jump in potential in step 402, output stage, clock signal is the first current potential, and module is kept to keep the first pull-up section
Point and the current potential of the second pull-up node are the first current potential, and output module is defeated to output end under the control of the second pull-up node
Enter clock signal.
In the output stage, the jump in potential of input signal is the second current potential, which inputs, the
The current potential of two pull-up nodes be the first current potential, the holding module can under the control of second pull-up node, control this first
The current potential of pull-up node is maintained at the first current potential, further such that the current potential of second pull-up node is also maintained at the first current potential.
The clock signal transitions are the first current potential at this time, which can be under the control of second pull-up node, to output end
Clock signal of the input in the first current potential, to realize the scanning to one-row pixels unit.
The current potential of step 403, reseting stage, the reset signal of reset signal end output is the first current potential, the first power supply letter
Number current potential be the first current potential, reseting module under the control of reset signal, to the first pull-up node input from second control
The current potential of the second control signal of signal end, second control signal is the second current potential, keeps module in the control of the first pull-up node
Under system, the current potential of the second pull-up node of control is the second current potential, and pull-down module is under the control of the first power supply signal, respectively to the
One pull-up node, the second pull-up node and output end input the second source signal from second source end, second source signal
Current potential be the second current potential.
In embodiments of the present invention, can also include the noise reduction stage after reseting stage, and in the noise reduction stage, under
Drawing-die block can save the first pull-up node, the second pull-up of the shift register cell under the control of the first power supply signal
Point and output end persistently input the second source signal in the second current potential, to realize on first pull-up node, second
Draw the lasting noise reduction of node and output end.And saltus step is the first current potential again in the current potential of the input signal of input signal end output
Before, which can repeat the noise reduction stage.
In conclusion the driving method of shift register cell provided in an embodiment of the present invention, provides in the input module
After input signal in the first current potential, the current potential which can control the second pull-up node is maintained at the first current potential,
So that when the current potential for the clock signal that clock signal terminal export for the first current potential when, transistor in output module can this
The state effectively opened is kept under the control of two pull-up nodes, exports the clock signal as drive signal to output end in time.
And since in the output stage, the current potential of second pull-up node is relatively stable, the load of output end will not be increased, therefore can
Potential change to ensure the drive signal of output module output is shorter to the duration of the first current potential, it is ensured that in time to aobvious
Show each pixel charging in region, to improve the display quality of display panel.
Further, Fig. 5 is each signal end during a kind of shift register cell driving provided in an embodiment of the present invention
Sequence diagram, by taking shift register cell shown in Fig. 3 as an example, and using each transistor in shift register cell as N-type crystalline substance
For high potential, shift register provided in an embodiment of the present invention is discussed in detail relative to the second current potential in body pipe, the first current potential
The driving principle of unit.
As shown in figure 5, in input phase t1, the current potential of the clock signal of clock signal terminal CLK outputs is the second current potential,
The current potential of the input signal of input signal end IN outputs is the first current potential, and the 8th transistor M8 is opened, reset signal end RST outputs
The current potential of reset signal be the second current potential, the 9th transistor M9 shutdown.First control signal end FW passes through the 8th transistor
M8 is in the first control signal of the first current potential to the first pull-up node PU1 inputs so that the current potential of first pull-up node PU1
It is raised, the first transistor M1 and the 4th transistor M4 are opened.First power end VGH is by the first transistor M1 on second
First power supply signal of the node PU2 inputs in the first current potential, second transistor M2 is drawn to open, clock signal terminal CLK is logical
Cross clock signal of the second transistor M2 output end outputs in the second current potential.Meanwhile the second source end VGL passes through
Four transistor M4 pull down second source signal of the node PD inputs in the second current potential, the 5th transistor M5, the 6th transistor
M6 and the 7th transistor M7 shutdowns, can to avoid the first pull-up node PU1 of VGL pairs of second source end, the second pull-up node PU2 and
The influence of output end OUT output signals, ensure that the job stability of shift register cell.
In exporting stage t2, the current potential of the input signal of input signal end IN outputs is the second current potential, the 8th transistor
M8 is turned off, the first pull-up node PU1 no signals input, since the current potential of second pull-up node PU2 at this time is the first current potential,
Therefore it is the first current potential, the first transistor M1 and the 4th transistor that capacitor C, which can keep the current potential of first pull-up node PU1,
M4 is opened, and the first power end VGH is by the first transistor M1 to the of second pull-up node PU2 input in the first current potential
One power supply signal, second transistor M2 are opened, and clock signal terminal CLK is inputted by second transistor M2 to output end OUT
Clock signal in the first current potential, to realize the scanning to one-row pixels unit.The second source end VGL passes through the 4th crystalline substance
Body pipe M4 pulls down second source signal of the node PD input in the second current potential, the 5th transistor M5, the 6th transistor M6,
7th transistor M7 shutdowns；The current potential of the reset signal of reset signal end RST outputs is the second current potential, and the 9th transistor M9 is closed
It is disconnected.
In reseting stage t3, the current potential of the reset signal of reset signal end RST outputs is the first current potential, the 9th transistor
M9 is opened, and second source signal end VGL is in the second current potential by the 9th transistor M9 to first pull-up node PU1 outputs
Second source signal, to discharging first pull-up node PU1.The first transistor M1 and the 4th transistor M4 are closed
It is disconnected.The grid of third transistor M3 is connect with the first power end, and third transistor M3 can be constantly in open state, this
When, first power end VGH can pull down first electricity of the node PD outputs in the first current potential by third transistor M3
Source signal, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7 are opened, and second source end VGL can be by this
5th transistor M5 to second source signal of second pull-up node PU2 output in the second current potential, to realize to this
The noise reduction of two pull-up node PU2.Similarly, second source end VGL can be saved by the 6th transistor M6 to first pull-up
Second source signal of the point PU1 outputs in the second current potential, to realize the noise reduction to first pull-up node PU1；This second
Power end VGL can be in the second source signal of the second current potential by the 7th transistor M7 to output end OUT outputs, from
And realize the noise reduction to output end OUT.The current potential of the input signal of input signal end IN outputs is the second current potential, the 8th crystal
Pipe M8 shutdowns.
Can also include noise reduction stage t4 after reseting stage t3 with reference to figure 5, in noise reduction stage t4, input letter
The current potential of input signal and the current potential of reset signal of reset signal end RST outputs of number end IN outputs are the second current potential,
8th transistor M8 and the 9th transistor M9 shutdowns.Third transistor M3 is kept it turning under the control of the first power end VGH
State, first power end VGH can pull down first of node PD outputs in the first current potential by third transistor M3
Power supply signal, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7 are kept it turned on, second source end VGL
It can continue the second source signal that the second current potential is in the second pull-up node PU2 outputs by the 5th transistor M5, from
And realize the lasting noise reduction to second pull-up node PU2.Similarly, second source end VGL can pass through the 6th transistor
M6 continues to second source signal of first pull-up node PU1 outputs in the second current potential, to realize to first pull-up
The lasting noise reduction of node PU1；Second source end VGL can continue to export to output end OUT by the 7th transistor M7
Second source signal in the second current potential, to realize the lasting noise reduction to output end OUT.
Before saltus step is the first current potential to the current potential for the input signal that input signal end IN is exported again, the shift register
Unit can repeat noise reduction stage t4, i.e. second source end VGL can be to the first pull-up of the shift register cell
Node PU1, the second pull-up node PU2 and output end OUT carry out continuing noise reduction.When the input signal that input signal end IN is exported
Current potential again saltus step be the first current potential when, that is to say that, when next frame scan starts, which can continue to hold
The above-mentioned input phase t1 to noise reduction stage t4 of row.
It should be noted that in input phase t1 and output stage t2, due to the grid of third transistor M3 and first
Power end VGH connections, therefore third transistor M3 is in normally open.When the current potential of the first pull-up node PU1 is the first electricity
When position, the 4th transistor M4 is opened, and second source end VGL can be defeated to pull-down node PD by the 4th transistor M4
Enter to be in the second source signal of the second current potential.Wherein, the breadth length ratio of the 4th transistor M4 can be more than the third transistor
The breadth length ratio of M3, so that when third transistor M3 and the 4th transistor M4 is opened simultaneously, second source end VGL
The current potential of pull-down node PD can also be dragged down by the second source signal of the 4th transistor M4 inputs, thus by lower rock
Mould each transistor shutdown in the block, avoids the current potential to the first pull-up node PU1, the second pull-up node PU2 and output end OUT
Influence.
The potential change schematic diagram of pull-up node PU' in shift register cell in the related technology is also shown in Fig. 5,
With reference to figure 5 it is found that in input phase t1, input signal end IN charges to pull-up node PU', the electricity of pull-up node PU'
Position is raised；In exporting stage t2, since the bootstrap effect of capacitor so that the current potential of pull-up node PU' is further drawn
Height, to driving transistor be allow effectively to open and output drive signal.And in embodiments of the present invention, this first
Electricity of the current potential of first power supply signal of power end VGH outputs relative to the first control signal end FW first control signals exported
Position is higher, with reference to figure 5, in input phase t1, since the current potential of second pull-up node PU2 has just been pulled to the first electricity
Position, so that when the current potential of clock signal is the first current potential, the transistor in output module can be in second pull-up
The state effectively opened is kept under the control of node, therefore can ensure to export the clock signal to output end in time, that is to say
The charging for ensureing each pixel into display area in time, improves display quality.And with reference to figure 3 as can be seen that the present invention is real
It applies in the output module 30 of the shift register cell of example offer and is not provided with capacitor, avoid the bootstrapping effect due to capacitor
It answers, causes the influence for loading clock signal to output end OUT.With reference to figure 5, in exporting stage t2, the output module can and
When to clock signal of the output end OUT output in the first current potential.
It should also be noted that, being using the first transistor to the 9th transistor as N-type crystal in the above embodiments
Pipe, and the explanation that the first current potential is carried out relative to the second current potential for high potential.Certainly, the first transistor is to the 9th transistor
P-type transistor can also be used, when the first transistor to the 9th transistor uses P-type transistor, first current potential is opposite
It is low potential in the second current potential, and the potential change of each signal end and node can be opposite with potential change shown in fig. 5.
In conclusion the driving method of shift register cell provided in an embodiment of the present invention, provides in the input module
After input signal in the first current potential, the current potential which can control the second pull-up node is maintained at the first current potential,
So that when the current potential for the clock signal that clock signal terminal export for the first current potential when, transistor in output module can this
The state effectively opened is kept under the control of two pull-up nodes, exports the clock signal as drive signal to output end in time.
And since in the output stage, the current potential of second pull-up node is relatively stable, the load of output end will not be increased, therefore can
Potential change to ensure the drive signal of output module output is shorter to the duration of the first current potential, it is ensured that in time to aobvious
Show each pixel charging in region, to improve the display quality of display panel.
Fig. 6 is a kind of structural schematic diagram of gate driving circuit provided in an embodiment of the present invention, as shown in fig. 6, the grid
Driving circuit may include：At least two it is cascade as Fig. 1 to Fig. 3 it is any shown in shift register cell.It is exemplary, Fig. 6
In show N number of cascade shift register cell, N can be the integer more than 1.
From fig. 6 it can be seen that can be with upper level shift register per the output end OUT of level-one shift register cell
The reset signal end RST of unit is connected；It can also be with next stage shift LD per the output end OUT of level-one shift register cell
The input signal end IN of device unit is connected.
It is exemplary, such as the reset signal of the output end OUT and shift register cell 1 of the shift register cell 2 in Fig. 6
RST is held to be connected, and the output end OUT of the shift register cell 2 is connected with the input signal end IN of shift register cell 3.
It should be noted that in order to realize the bilateral scanning of shift register, as shown in fig. 6, in the gate driving circuit,
The input signal end IN of first order shift register cell and the reset signal end RST of afterbody shift register cell can
To be connected with open signal end STV.
It should also be noted that, with reference to figure 6, which can be with two clock signal terminal CLK and CLKB phases
Even, also, adjacent two-stage shift register cell can be connected with one of clock signal terminal respectively.Such as in Fig. 6 institutes
In the circuit shown, odd level shift register cell is connected with clock signal terminal CLK, even level shift register cell and clock
Signal end CLKB is connected, and the frequency for the clock signal which exports is identical, opposite in phase.
The embodiment of the present invention also provides a kind of display device, which may include gate driving as shown in FIG. 6
Circuit.The display device can be：Liquid crystal display panel, Electronic Paper, oled panel, AMOLED panel, mobile phone, tablet computer, TV
Any product or component with display function such as machine, display, laptop, Digital Frame, navigator.
It is apparent to those skilled in the art that for convenience and simplicity of description, the grid of foregoing description
The specific work process of driving circuit, shift register cell and each module can refer to the correspondence in preceding method embodiment
Process, details are not described herein.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of shift register cell, which is characterized in that the shift register cell includes：Input module, keep module,
Output module, reseting module and pull-down module；
The input module is connect with input signal end, first control signal end and the first pull-up node respectively, the input mould
Block is used under the control of the input signal from the input signal end, to first pull-up node input from described the
The first control signal of one control signal end；
The holding module is connect with first pull-up node, the first power end and the second pull-up node respectively, the holding
Module is used under the control of first pull-up node, is inputted to second pull-up node from first power end
First power supply signal, and keep the current potential of first pull-up node and second pull-up node；
The output module is connect with clock signal terminal, second pull-up node and output end respectively, and the output module is used
Under the control in second pull-up node, the clock signal from the clock signal terminal is inputted to the output end；
The reseting module is connect with reset signal end, second control signal end and first pull-up node respectively, described
Reseting module is used under the control of the reset signal from the reset signal end, is come to first pull-up node input
The second control signal at the second control signal end；
The pull-down module is pulled up with first power end, second source end, first pull-up node, described second respectively
Node is connected with the output end, and the pull-down module is used under the control of first power supply signal, respectively to described the
One pull-up node, second pull-up node and the output end input the second source signal from the second source end.
2. shift register cell according to claim 1, which is characterized in that the holding module, including：First crystal
Pipe and capacitor；
The grid of the first transistor is connect with first pull-up node, the first pole of the first transistor and described the
One power end connects, and the second pole of the first transistor is connect with second pull-up node；
One end of the capacitor is connect with first pull-up node, and the other end of the capacitor is saved with second pull-up
Point connection.
3. shift register cell according to claim 1, which is characterized in that the output module includes：Second crystal
Pipe；
The grid of the second transistor is connect with second pull-up node, the first pole of the second transistor with it is described when
Clock signal end connects, and the second pole of the second transistor is connect with the output end.
4. shift register cell according to claim 1, which is characterized in that the pull-down module includes：Drop-down control
Submodule and drop-down submodule；
The drop-down control submodule respectively with first power end, the second source end, first pull-up node with
And the pull-down node connection, under the control of first pull-up node, described first to be inputted to the pull-down node
Power supply signal；
The drop-down submodule respectively with the second source end, first pull-up node, second pull-up node, described
Pull-down node and output end connection, under the control from the pull-down node, to first pull-up node,
Second pull-up node and the output end input the second source signal.
5. shift register cell according to claim 4, which is characterized in that the drop-down control submodule includes：The
Three transistors and the 4th transistor；The drop-down submodule includes：5th transistor, the 6th transistor and the 7th transistor；
The grid of the third transistor and first is extremely connect with first power end, the second pole of the third transistor
It is connect with the pull-down node；
The grid of 4th transistor is connect with first pull-up node, the first pole of the 4th transistor and described the
Two power ends connect, and the second pole of the 4th transistor is connect with the pull-down node；
The grid of 5th transistor is connect with the pull-down node, the first pole of the 5th transistor and second electricity
Source connects, and the second pole of the 5th transistor is connect with second pull-up node；
The grid of 6th transistor is connect with the pull-down node, the first pole of the 6th transistor and second electricity
Source connects, and the second pole of the 6th transistor is connect with first pull-up node；
The grid of 7th transistor is connect with the pull-down node, the first pole of the 7th transistor and second electricity
Source connects, and the second pole of the 7th transistor is connect with the output end.
6. shift register cell according to claim 1, which is characterized in that the input module, including：8th crystal
Pipe；
The grid of 8th transistor is connect with the input signal end, the first pole and described first of the 8th transistor
Control signal end connects, and the second pole of the 8th transistor is connect with first pull-up node.
7. shift register cell according to claim 1, which is characterized in that the reseting module includes：9th crystal
Pipe；
The grid of 9th transistor is connect with the reset signal end, the first pole and described second of the 9th transistor
Control signal end connects, and the second pole of the 9th transistor is connect with first pull-up node.
8. a kind of driving method of shift register cell, which is characterized in that the shift register cell include input module,
Keep module, output module, reseting module and pull-down module；The method includes：
The current potential of input phase, the input signal of input signal end output is the first current potential, and the input module is in the input
Under the control of signal, the first control signal from first control signal end, first control are inputted to the first pull-up node
The current potential of signal is the first current potential, and the holding module is defeated to the second pull-up node under the control of first pull-up node
Enter the first power supply signal from the first power end, the current potential of first power supply signal is the first current potential, the output module
Under the control of second pull-up node, the clock signal from clock signal terminal, the clock signal are inputted to output end
Current potential be the second current potential；
The jump in potential in output stage, the clock signal is the first current potential, and the holding module keeps the first pull-up section
Point and the current potential of second pull-up node are the first current potential, control of the output module in second pull-up node
Under, input the clock signal to output end；
The current potential of reseting stage, the reset signal of reset signal end output is the first current potential, the current potential of first power supply signal
For the first current potential, the reseting module comes from second under the control of the reset signal, to first pull-up node input
The current potential of the second control signal of control signal end, the second control signal is the second current potential, and the holding module is described
Under the control of first pull-up node, the current potential for controlling second pull-up node is the second current potential, and the pull-down module is described
Under the control of first power supply signal, inputted respectively to first pull-up node, second pull-up node and the output end
The current potential of second source signal from second source end, the second source signal is the second current potential.
9. a kind of gate driving circuit, which is characterized in that the gate driving circuit includes：At least two is cascade as right is wanted
Seek 1 to 7 any shift register cell；
Output end per level-one shift register cell respectively with the reset signal end of upper level shift register cell, and under
The input signal end of level-one shift register cell connects.
10. a kind of display device, which is characterized in that the display device includes：Gate driving electricity as claimed in claim 9
Road.
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| CN201810247827.0A CN108389545A (en) | 2018-03-23 | 2018-03-23 | Shift register cell, driving method, gate driving circuit and display device |
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| CN201810247827.0A CN108389545A (en) | 2018-03-23 | 2018-03-23 | Shift register cell, driving method, gate driving circuit and display device |
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| CN110223653A (en) * | 2019-06-10 | 2019-09-10 | 京东方科技集团股份有限公司 | A kind of shift register and its driving method, gate driving circuit |
| CN111477193A (en) * | 2020-05-25 | 2020-07-31 | 京东方科技集团股份有限公司 | Shift register and driving method thereof |
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Application publication date: 20180810 |
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