CN111477193A - Shift register and driving method thereof - Google Patents
Shift register and driving method thereof Download PDFInfo
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- CN111477193A CN111477193A CN202010448783.5A CN202010448783A CN111477193A CN 111477193 A CN111477193 A CN 111477193A CN 202010448783 A CN202010448783 A CN 202010448783A CN 111477193 A CN111477193 A CN 111477193A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The invention provides a shift register and a driving method thereof, belongs to the technical field of display, and can at least partially solve the problem of poor display of a liquid crystal display panel caused by electric leakage of a storage capacitor in the conventional shift register. A shift register of the present invention is a shift register for supplying a driving signal to a gate line, the shift register including: the shift register module is used for transmitting the signal of the first voltage end to the output end and the output control end according to the level of the pull-down node, and transmitting the signal of the first clock end to the output end and the output control end according to the level of the pull-up node; and the pull-up node control module is used for transmitting the signal of the third voltage end to the pull-up node according to the signal of the second clock end.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a shift register and a driving method thereof.
Background
The liquid crystal display panel generally comprises pixel units distributed in an array, and grid scanning signals are output to the pixel units line by line through a grid driving circuit in the display process; specifically, the gate driving circuit is formed by a plurality of cascaded shift registers GOA, and each shift register sequentially transfers the gate scanning signal to the next-stage shift register, so that the switching transistors in the pixel units are turned on row by row to complete the data signal input of the pixel units.
As shown in fig. 1a and fig. 1b, in a driving process of a shift register in the prior art, in an output stage, a point of a pull-up node PU is at a high level, and the point is written into a storage capacitor C2, a clock terminal C L k (n) is at a high level, and an output terminal G-Out outputs a scan line number, when the clock terminal C L k (n) of the shift register becomes at a low level, an output signal of the output terminal G-Out needs to be attenuated gradually, however, since channels of transistors (e.g., a ninth transistor M9 and a fourteenth transistor M14) connected to the storage capacitor C2 are relatively small, the storage capacitor C2 leaks electricity, the tenth transistor M10 is not fully opened, and a fall time (Tf) of the output terminal G-Out increases, when the fall time of the output terminal G-Out is too large, the charging of pixel units in a next row is affected, and finally, a display failure of a line liquid crystal display panel is caused (e.g., Mura, etc.).
Disclosure of Invention
The invention at least partially solves the problem of poor display of the line liquid crystal display panel caused by the leakage of the storage capacitor in the existing shift register, and provides the shift register which avoids the poor display of the line liquid crystal display panel caused by the leakage of the second storage capacitor.
The technical scheme adopted for solving the technical problem of the invention is a shift register, which is used for providing a driving signal for a grid line, and comprises:
the shift register module is used for transmitting the signal of the first voltage end to the output end and the output control end according to the level of the pull-down node, and transmitting the signal of the first clock end to the output end and the output control end according to the level of the pull-up node;
and the pull-up node control module is used for transmitting the signal of the third voltage end to the pull-up node according to the signal of the second clock end.
Further preferably, the pull-up node control module includes: a first storage capacitor having a first pole connected to the first node and a second pole connected to the second node; the charging unit is used for writing signals of the input end and the second clock end into the first storage capacitor according to the signals of the input end; the first output unit is used for writing a signal of a third voltage end into a pull-up node according to a signal of a second clock end; the first reset unit is used for transmitting the signal of the first voltage end to the first node and the second node according to the signal of the reset end.
Further preferably, the charging unit includes: a first transistor, wherein a grid electrode of the first transistor is connected with the input end, a first pole of the first transistor is connected with the input end, and a second pole of the first transistor is connected with a first node; and the grid electrode of the second transistor is connected with the first node, the first pole of the second transistor is connected with the second clock end, and the second pole of the second transistor is connected with the second node.
Further preferably, the first output unit includes: a third transistor, wherein the grid electrode of the third transistor is connected with the second clock end, and the first pole of the third transistor is connected with the third voltage end; and the grid electrode of the fourth transistor is connected with the second node, the first pole of the fourth transistor is connected with the second pole of the third transistor, and the second pole of the fourth transistor is connected with the upper pull node.
Further preferably, the first reset unit includes: a fifth transistor, a gate of which is connected to the reset terminal, a first pole of which is connected to the first node, and a second pole of which is connected to the first voltage terminal; a sixth transistor, a gate of which is connected to the pull-down node, a first pole of which is connected to the first node, and a second pole of which is connected to the first voltage terminal; and the grid of the seventh transistor is connected with the pull-down node, the first pole of the seventh transistor is connected with the second node, and the second pole of the seventh transistor is connected with the first voltage end.
Further preferably, the shift register module includes: a first pole of the second storage capacitor is connected with the pull-up node, and a second pole of the second storage capacitor is connected with the output end; the input reset unit is used for writing the signal of the input end or the first voltage end into the pull-up node according to the signals of the input end and the reset end; the second output unit is used for transmitting the signal of the first clock end to the output end and the output control end according to the level of the pull-up node; the pull-down control unit is used for writing a signal of the first voltage end or the second voltage end into the pull-down node according to the level of the pull-up node; and the pull-down unit is used for transmitting the signal of the first voltage end to the output end and the output control end according to the level of the pull-down node.
Further preferably, the input reset unit includes: an eighth transistor having a gate connected to the input terminal and a first terminal, and a second terminal connected to the pull-up node; and a ninth transistor, wherein the grid electrode of the ninth transistor is connected with the reset end, the first pole of the ninth transistor is connected with the upper pull node, and the second pole of the ninth transistor is connected with the first voltage end.
Further preferably, the second output unit includes: a tenth transistor, a gate of which is connected to the pull-up node, a first pole of which is connected to the first clock terminal, and a second pole of which is connected to the output terminal; and the grid electrode of the eleventh transistor is connected with the upper pull node, the first pole of the eleventh transistor is connected with the first clock end, and the second pole of the eleventh transistor is connected with the output control end.
Further preferably, the pull-down control unit includes: a twelfth transistor, a gate of which is connected to the pull-down control node, a first pole of which is connected to the second voltage terminal, and a second pole of which is connected to the pull-down node; and the grid electrode and the first electrode of the thirteenth transistor are connected with the second voltage end, and the second electrode of the thirteenth transistor is connected with the pull-down control node.
Further preferably, the pull-down unit includes: a fourteenth transistor, having a gate connected to the pull-down node, a first pole connected to the pull-up node, and a second pole connected to the first voltage terminal; a fifteenth transistor, a gate of which is connected to the pull-down node, a first pole of which is connected to the output terminal, and a second pole of which is connected to the first voltage terminal; a sixteenth transistor, a gate of which is connected to the pull-down node, a first pole of which is connected to the output control terminal, and a second pole of which is connected to the first voltage terminal; a seventeenth transistor having a gate connected to the pull-up node, a first pole connected to the pull-down control node, and a second pole connected to the first voltage terminal; and the grid electrode of the eighteenth transistor is connected with the pull-up node, the first pole of the eighteenth transistor is connected with the pull-down node, and the second pole of the eighteenth transistor is connected with the first voltage end.
The technical scheme adopted for solving the technical problem of the invention is a driving method of a shift register, wherein the shift register is the shift register, and the method comprises the following steps:
and in the pull-up node control stage and the output signal attenuation stage, the pull-up node control module transmits the signal of the third voltage end to the pull-up node according to the signal of the second clock end.
More preferably, the shift register is the shift register described above; in the method, the first voltage end is continuously provided with turn-off, the second voltage end is continuously provided with a turn-on signal, and the third voltage end is continuously provided with constant voltage; the method specifically comprises the following steps: a charging stage: providing a turn-on signal to the input terminal and providing a turn-off signal to the reset terminal, the first clock terminal and the second clock terminal; an output stage: providing a turn-on signal to the first clock terminal and providing a turn-off signal to the input terminal, the reset terminal and the second clock terminal; and a pull-up node control stage: providing a turn-on signal to the first clock terminal and the second clock terminal, and providing a turn-off signal to the input terminal and the reset terminal; and an output signal attenuation stage: providing a conducting signal to the second clock end and providing a switching-off signal to the input end, the reset end and the first clock end; a reset phase: an on signal is provided to the reset terminal and an off signal is provided to the input terminal, the first clock terminal and the second clock terminal.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1a is a schematic diagram of a conventional shift register;
FIG. 1b is a timing diagram of a shift register of FIG. 1 a;
FIG. 2 is a diagram illustrating a shift register according to an embodiment of the present invention;
FIG. 3 is a timing diagram of a shift register of FIG. 2;
the voltage regulator comprises a reference numeral 1, a shift register module, a 2, a pull-up node control module, an M, a first transistor, an M, a second transistor, an M, a third transistor, an M, a fourth transistor, an M, a fifth transistor, an M, a sixth transistor, an M, a seventh transistor, an M, an eighth transistor, an M, a ninth transistor, an M, a tenth transistor, an M, an eleventh transistor, an M, a twelfth transistor, an M, a thirteenth transistor, an M, a fourteenth transistor, an M, a fifteenth transistor, an M, a sixteenth transistor, an M, a seventeenth transistor, an M ', an auxiliary sixth transistor, an M ', an auxiliary seventh transistor, an M ', an auxiliary twelfth transistor, an M ', an auxiliary thirteenth transistor, an M ', an auxiliary fourteenth transistor, an M ', an auxiliary fifteenth transistor, an M ', an auxiliary sixteenth transistor, an M ', an auxiliary seventeenth transistor, an M ', an auxiliary eighteenth transistor, a C, a first storage capacitor, a C, a second storage capacitor, a PD, a pull-down node, an auxiliary node, a pull-down node control module, a PU, a pull-up node control node, a pull-down node, a PU, a pull-down node control voltage, a PU, a pull-up node, a pull-down node control node, a pull-down node, a pull-up node, a pull-down node control node, a pull-down node, a pull.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Example 1:
as shown in fig. 2 to 3, the present embodiment provides a shift register for providing a driving signal to a gate line, including:
a shift register module 1, configured to transmit a signal of a first voltage terminal L Vss to an output terminal G-Out and an output control terminal Out1 according to a level of a pull-down node PD, and transmit a signal of a first clock terminal C L k (n) to the output terminal G-Out and the output control terminal Out1 according to a level of a pull-up node PU;
the pull-up node control module 2 is configured to transmit a signal of the third voltage terminal Vp to the pull-up node PU according to a signal of the second clock terminal C L K (n + 1).
The pull-up node control module 2 in the shift register of this embodiment can transmit the signal of the third voltage end Vp to the pull-up node PU according to the signal of the second clock end C L K (n +1), and the signal of the third voltage end Vp is a constant voltage signal, so that the voltage of the pull-up node PU is not changed, because one pole of the second storage capacitor C2 is connected to the pull-up node PU and other transistors, and the other pole is connected to the output end G-Out, when the output end G-Out signal is attenuated, the stable voltage of the pull-up node PU can ensure that the second storage capacitor C2 does not leak electricity, thereby avoiding the phenomenon that the falling edge duration of the output end G-Out signal is prolonged due to the electricity leakage of the second storage capacitor C2, so that the charging stage of the next row is not affected, and further ensuring that the liquid crystal display panel corresponding to the shift register can normally display.
Preferably, the pull-up node control module 2 includes:
a first storage capacitor C1 having a first pole connected to the first node PU1 and a second pole connected to the second node PU 2;
a charging unit for writing signals of the Input terminal Input and the second clock terminal C L K (n +1) into the first storage capacitor C1 according to the signal of the Input terminal Input;
a first output unit for writing a signal of the third voltage terminal Vp into the pull-up node PU according to a signal of the second clock terminal C L K (n + 1);
the first Reset unit is configured to transmit a signal of the first voltage terminal L Vss to the first node PU1 and the second node PU2 according to a signal of the Reset terminal Reset PU.
Specifically, the charging unit includes a first transistor M1 having a gate connected to the Input terminal Input, a first pole connected to the Input terminal Input, and a second pole connected to the first node PU1, and a second transistor M2 having a gate connected to the first node PU1, a first pole connected to the second clock terminal C L K (n +1), and a second pole connected to the second node PU 2.
The first output unit includes a third transistor M3 having a gate connected to the second clock terminal C L K (n +1) and a first electrode connected to the third voltage terminal Vp, and a fourth transistor M4 having a gate connected to the second node PU2, a first electrode connected to the second electrode of the third transistor M3 and a second electrode connected to the pull-up node PU.
The first Reset unit includes a fifth transistor M5 having a gate connected to the Reset terminal Reset PU, a first pole connected to the first node PU1, and a second pole connected to the first voltage terminal L Vss, a sixth transistor M6 having a gate connected to the pull-down node PD, a first pole connected to the first node PU1, and a second pole connected to the first voltage terminal L Vss, and a seventh transistor M7 having a gate connected to the pull-down node PD, a first pole connected to the second node PU2, and a second pole connected to the first voltage terminal L Vss.
Further, the first reset unit further includes an auxiliary sixth transistor M6 'having a gate connected to the auxiliary pull-down node PD', a first pole connected to the first node PU1, and a second pole connected to the first voltage terminal L Vss, and an auxiliary seventh transistor M7 'having a gate connected to the auxiliary pull-down node PD', a first pole connected to the second node PU2, and a second pole connected to the first voltage terminal L Vss.
Since the connection relationships between the auxiliary sixth transistor M6 'and the sixth transistor M6, and between the auxiliary seventh transistor M7' and the seventh transistor M7 and other modules are the same, the functions and operating principles of the auxiliary sixth transistor M6 'and the sixth transistor M6 are the same, and the functions and operating principles of the auxiliary seventh transistor M7' and the seventh transistor M7 are the same. In the following description, only the sixth transistor M6 and the seventh transistor M7 are described, and the auxiliary sixth transistor M6 'and the auxiliary seventh transistor M7' are omitted.
Preferably, the shift register module 1 includes:
a first pole of the second storage capacitor C2 is connected with the pull-up node PU, and a second pole is connected with the output end G-Out;
an Input Reset unit for writing a signal of the Input terminal Input or the first voltage terminal L Vss into the pull-up node PU according to signals of the Input terminal Input and the Reset terminal Reset PU;
a second output unit for transmitting a signal of the first clock terminal C L k (n) to the output terminal G-Out and the output control terminal Out1 according to the level of the pull-up node PU;
a pull-down control unit for writing a signal of the first voltage terminal L Vss or the second voltage terminal VDD into the pull-down node PD according to a level of the pull-up node PU;
and the pull-down unit is used for transmitting the signal of the first voltage end L Vss to the output end G-Out and the output control end Out1 according to the level of the pull-down node PD.
Specifically, the Input Reset unit includes an eighth transistor M8 having a gate connected to the first terminal Input and a second terminal connected to the pull-up node PU, and a ninth transistor M9 having a gate connected to the Reset terminal Reset PU, a first terminal connected to the pull-up node PU, and a second terminal connected to the first voltage terminal L Vss.
The second output unit comprises a tenth transistor M10, a first electrode of which is connected with the first clock end C L K (n) and a second electrode of which is connected with the output end G-Out, a tenth transistor M10, a gate of which is connected with the pull-up node PU, a eleventh transistor M11, a first electrode of which is connected with the first clock end C L K (n) and a second electrode of which is connected with the output control end Out 1.
The pull-down control unit includes: a twelfth transistor M12, having a gate connected to the pull-down control node PD-CN, a first pole connected to the second voltage terminal VDD, and a second pole connected to the pull-down node PD; and a thirteenth transistor M13 having a gate and a first pole connected to the second voltage terminal VDD, and a second pole connected to the pull-down control node PD-CN.
The pull-down unit comprises a fourteenth transistor M14, a fifteenth transistor M15, a fifteenth transistor M3578, a sixteenth transistor M17, a seventeenth transistor M17 and a seventeenth transistor M7328, wherein the gate of the fourteenth transistor M14 is connected with the pull-down node PD, the first pole of the fourteenth transistor M is connected with the pull-down node PU, the second pole of the fifteenth transistor M is connected with the first voltage terminal L Vss, the gate of the fifteenth transistor M15 is connected with the pull-down node PD, the first pole of the sixteenth transistor M16 is connected with the pull-down node PD, the first pole of the sixteenth transistor M1 is connected with the output control terminal Out1, the second pole of the fifteenth transistor M18 is connected with the first voltage terminal L Vss, the first pole of the transistor M18 is connected with the pull-down node PD, and the second pole of the transistor M18 is connected with the.
Further, the shift register module 1 further includes an auxiliary pull-down control module and an auxiliary pull-down module.
Wherein the auxiliary pull-down control unit includes: an auxiliary twelfth transistor M12 'having a gate connected to the auxiliary pull-down control node PD-CN', a first pole connected to the auxiliary second voltage terminal VDD ', and a second pole connected to the auxiliary pull-down node PD'; the auxiliary thirteenth transistor M13 ' has a gate and a first pole connected to the auxiliary second voltage terminal VDD ', and a second pole connected to the auxiliary pull-down control node PD-CN '.
The auxiliary pull-down unit comprises an auxiliary fourteenth transistor M14 'with a gate connected to an auxiliary pull-down node PD', a first pole connected to the pull-down node PU and a second pole connected to the first voltage terminal L Vss, an auxiliary fifteenth transistor M15 'with a gate connected to the auxiliary pull-down node PD', a first pole connected to the output terminal G-Out and a second pole connected to the first voltage terminal L Vss, an auxiliary sixteenth transistor M16 'with a gate connected to the auxiliary pull-down node PD-CN', a first pole connected to the output control terminal Out1 and a second pole connected to the first voltage terminal L Vss, an auxiliary seventeenth transistor M17 'with a gate connected to the pull-down node PU, a first pole connected to the auxiliary pull-down control node PD-CN', a second pole connected to the first voltage terminal L, and an auxiliary eighteenth transistor M18 'with a gate connected to the pull-up node PU, a first pole connected to the auxiliary pull-down node PD', and a second pole connected.
It should be noted that, since the structures of the auxiliary pull-down control module and the pull-down control module, and the structures of the auxiliary pull-down module and the pull-down module are respectively the same, and the connection relations with other modules are also respectively the same, the functions and the working principles of the auxiliary pull-down control module and the pull-down control module are the same, and the functions and the working principles of the auxiliary pull-down module and the pull-down module are the same. In the following description, only the pull-down control module and the pull-down module will be described, and the auxiliary pull-down control module and the auxiliary pull-down module will be omitted.
Further preferably, all transistors are N-type transistors (e.g., all N-type thin film transistors); alternatively, all transistors are P-type transistors (e.g., all P-type thin film transistors).
The present embodiment further provides a driving method of the shift register, which includes the step of the pull-up node control module 2 transmitting the signal of the third voltage terminal Vp to the pull-up node PU according to the signal of the second clock terminal C L K (n +1) during the pull-up node PU control phase and the output signal attenuation phase.
The pull-up node control module 2 may transmit the signal of the third voltage end Vp to the pull-up node PU according to the signal of the second clock end C L K (n +1), and the signal of the third voltage end Vp is a constant voltage signal, so that the voltage of the pull-up node PU is not changed.
Further, as shown in fig. 2 and 3, in the method, the first voltage terminal L Vss is continuously provided with a turn-off signal, the second voltage terminal VDD is continuously provided with a turn-on signal, and the third voltage terminal Vp is continuously provided with a constant voltage, and the method specifically includes:
s11, a charging period t1, in which an on signal is provided to the Input terminal, and an off signal is provided to the Reset terminal Reset pu, the first clock terminal C L K (n), and the second clock terminal C L K (n + 1).
The on signal is a signal that can turn on the transistor when applied to the gate of the transistor, and the off signal is a signal that can turn off the transistor when applied to the gate of the transistor.
In the following, all transistors are N-type transistors, so the on signal is a high level signal and the off signal is a low level signal.
In this stage, that is, the Input terminal Input is at a high level, so that the high level of the Input terminal Input is transmitted to the pull-up node PU through the eighth transistor M8, the pull-up node PU is at a high level, and the seventeenth transistor M17 and the eighteenth transistor M18 are turned on, so that even if the second voltage terminal VDD is at a high level, the twelfth transistor M12 and the thirteenth transistor M13 are both turned off, and the pull-down node PD is at a low level, so that the fifteenth transistor M15, the sixteenth transistor M16, the sixth transistor M6, and the seventh transistor M7 are all turned off.
Meanwhile, the high level of the pull-up node PU also turns on the tenth transistor M10, so that the low level of the first clock terminal C L k (n) is introduced into the output control terminal Out1 and the second pole of the second storage capacitor C2, and the second storage capacitor C2 is charged.
In addition, the high level of the Input terminal Input is transmitted to the first node PU1 through the first transistor M1, the second transistor M2 is turned on, and the first storage capacitor C1 is charged.
S12, an output stage t2, providing an ON signal to the first clock terminal C L K (n), and providing an OFF signal to the Input terminal Input, the Reset terminal Reset pu and the second clock terminal C L K (n + 1).
In this stage, i.e. the first clock terminal C L K (n) inputs a high level, and the Input terminal Input, the Reset terminal Reset PU and the second clock terminal C L K (n +1) Input a low level, due to the bootstrap action of the first storage capacitor C1, the level of the pull-up node PU is further pulled up (at this time, the eighth transistor M8 is turned off) and still belongs to a high level, so the pull-down node PD keeps a low level, the fifteenth transistor M15 and the sixteenth transistor M16 are both turned off, and the pull-up node PU turns on the tenth transistor M10 and the eleventh transistor M11, so that the output control terminal Out1 of the shift register outputs a high level of the first clock terminal C L K (n).
Meanwhile, since the second clock terminal C L K (n +1) is still low, the first node PU1 and the second node PU2 have the same point as the previous stage.
S13, the pull-up node PU controls the stage t3 to provide an ON signal to the first clock terminal C L K (n) and the second clock terminal C L K (n +1), and to provide an OFF signal to the Input terminal Input and the Reset terminal Reset PU.
In this stage, that is, the second clock terminal C L K (n +1) inputs a high level, the second node PU2 becomes a high level, the third transistor M3 and the fourth transistor M4 are turned on, and the constant signal of the third voltage terminal Vp is written into the pull-up node PU, so that the pull-up node PU is a constant voltage, and the voltage of the first node PU1 is further increased due to the first storage capacitor C1.
Preferably, the constant signal of the third voltage terminal Vp has a certain difference according to different actual products, and the specific set value is optimal to be as consistent as possible with the bootstrap voltage value of the pull-up node PU.
S14, an output signal attenuation stage t4, which provides an on signal to the second clock terminal C L K (n +1), and provides an off signal to the Input terminal Input, the Reset terminal Reset pu and the first clock terminal C L K (n).
In this stage, i.e. the first clock terminal C L k (n) is at a low level, so as to gradually attenuate the signal at the output terminal G-Out, since the voltage at the pull-up node PU is still constant at the previous stage, the leakage phenomenon of the second storage capacitor C2 due to the too small channel size of the transistors (e.g. the seventeenth transistor M17, the eighteenth transistor M18, etc.) connected thereto can be avoided, and thus the time for the voltage at the output terminal G-Out to change (drop) is not prolonged, so as to ensure that the display of the lcd panel corresponding to the shift register is normal.
S15, a Reset period t5, providing an ON signal to the Reset terminal Reset pu, and providing an OFF signal to the Input terminal Input, the first clock terminal C L K (n), and the second clock terminal C L K (n + 1).
In this stage, that is, the Reset terminal Reset PU inputs a high level, so the fifth transistor M5 and the ninth transistor M9 are turned on, a low level of the first voltage terminal L Vss is introduced into the pull-up node PU and the first node PU1, the first storage capacitor C1 and the second storage capacitor C2 are no longer charged, the second transistor M2, the tenth transistor M10 and the eleventh transistor M11 are turned off, and the output control terminal Out1 and the output terminal G-Out of the shift register output a low level.
The second clock terminal C L K (n +1) in each shift register cascade may be the first clock terminal C L K (n) in the next shift register cascade.
In addition, the time lengths of the charging phase, the output phase, the pull-up node PU control phase, the output signal attenuation phase and the reset phase are shown by the double-arrow line in fig. 3, where H represents the unit of the time length.
Specifically, the display device can be any product or component with a display function, such as a liquid crystal display panel, electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (12)
1. A shift register for supplying a driving signal to a gate line, comprising:
the shift register module is used for transmitting the signal of the first voltage end to the output end and the output control end according to the level of the pull-down node, and transmitting the signal of the first clock end to the output end and the output control end according to the level of the pull-up node;
and the pull-up node control module is used for transmitting the signal of the third voltage end to the pull-up node according to the signal of the second clock end.
2. The shift register of claim 1, wherein the pull-up node control module comprises:
a first storage capacitor having a first pole connected to the first node and a second pole connected to the second node;
the charging unit is used for writing signals of the input end and the second clock end into the first storage capacitor according to the signals of the input end;
the first output unit is used for writing a signal of a third voltage end into a pull-up node according to a signal of a second clock end;
the first reset unit is used for transmitting the signal of the first voltage end to the first node and the second node according to the signal of the reset end.
3. The shift register according to claim 2, wherein the charging unit comprises:
a first transistor, wherein a grid electrode of the first transistor is connected with the input end, a first pole of the first transistor is connected with the input end, and a second pole of the first transistor is connected with a first node;
and the grid electrode of the second transistor is connected with the first node, the first pole of the second transistor is connected with the second clock end, and the second pole of the second transistor is connected with the second node.
4. The shift register according to claim 3, wherein the first output unit includes:
a third transistor, wherein the grid electrode of the third transistor is connected with the second clock end, and the first pole of the third transistor is connected with the third voltage end;
and the grid electrode of the fourth transistor is connected with the second node, the first pole of the fourth transistor is connected with the second pole of the third transistor, and the second pole of the fourth transistor is connected with the upper pull node.
5. The shift register according to claim 4, wherein the first reset unit includes:
a fifth transistor, a gate of which is connected to the reset terminal, a first pole of which is connected to the first node, and a second pole of which is connected to the first voltage terminal;
a sixth transistor, a gate of which is connected to the pull-down node, a first pole of which is connected to the first node, and a second pole of which is connected to the first voltage terminal;
and the grid of the seventh transistor is connected with the pull-down node, the first pole of the seventh transistor is connected with the second node, and the second pole of the seventh transistor is connected with the first voltage end.
6. The shift register of claim 5, wherein the shift register module comprises:
a first pole of the second storage capacitor is connected with the pull-up node, and a second pole of the second storage capacitor is connected with the output end;
the input reset unit is used for writing the signal of the input end or the first voltage end into the pull-up node according to the signals of the input end and the reset end;
the second output unit is used for transmitting the signal of the first clock end to the output end and the output control end according to the level of the pull-up node;
the pull-down control unit is used for writing a signal of the first voltage end or the second voltage end into the pull-down node according to the level of the pull-up node;
and the pull-down unit is used for transmitting the signal of the first voltage end to the output end and the output control end according to the level of the pull-down node.
7. The shift register according to claim 6, wherein the input reset unit comprises:
an eighth transistor having a gate connected to the input terminal and a first terminal, and a second terminal connected to the pull-up node;
and a ninth transistor, wherein the grid electrode of the ninth transistor is connected with the reset end, the first pole of the ninth transistor is connected with the upper pull node, and the second pole of the ninth transistor is connected with the first voltage end.
8. The shift register according to claim 7, wherein the second output unit includes:
a tenth transistor, a gate of which is connected to the pull-up node, a first pole of which is connected to the first clock terminal, and a second pole of which is connected to the output terminal;
and the grid electrode of the eleventh transistor is connected with the upper pull node, the first pole of the eleventh transistor is connected with the first clock end, and the second pole of the eleventh transistor is connected with the output control end.
9. The shift register according to claim 8, wherein the pull-down control unit comprises:
a twelfth transistor, a gate of which is connected to the pull-down control node, a first pole of which is connected to the second voltage terminal, and a second pole of which is connected to the pull-down node;
and the grid electrode and the first electrode of the thirteenth transistor are connected with the second voltage end, and the second electrode of the thirteenth transistor is connected with the pull-down control node.
10. The shift register of claim 9, wherein the pull-down unit comprises:
a fourteenth transistor, having a gate connected to the pull-down node, a first pole connected to the pull-up node, and a second pole connected to the first voltage terminal;
a fifteenth transistor, a gate of which is connected to the pull-down node, a first pole of which is connected to the output terminal, and a second pole of which is connected to the first voltage terminal;
a sixteenth transistor, a gate of which is connected to the pull-down node, a first pole of which is connected to the output control terminal, and a second pole of which is connected to the first voltage terminal;
a seventeenth transistor having a gate connected to the pull-up node, a first pole connected to the pull-down control node, and a second pole connected to the first voltage terminal;
and the grid electrode of the eighteenth transistor is connected with the pull-up node, the first pole of the eighteenth transistor is connected with the pull-down node, and the second pole of the eighteenth transistor is connected with the first voltage end.
11. A method of driving a shift register, the shift register being as claimed in any one of claims 1 to 10, the method comprising:
and in the pull-up node control stage and the output signal attenuation stage, the pull-up node control module transmits the signal of the third voltage end to the pull-up node according to the signal of the second clock end.
12. The bit register driving method according to claim 11, wherein the shift register is the shift register according to claim 10; in the method, the first voltage end is continuously provided with turn-off, the second voltage end is continuously provided with a turn-on signal, and the third voltage end is continuously provided with constant voltage; the method specifically comprises the following steps:
a charging stage: providing a turn-on signal to the input terminal and providing a turn-off signal to the reset terminal, the first clock terminal and the second clock terminal;
an output stage: providing a turn-on signal to the first clock terminal and providing a turn-off signal to the input terminal, the reset terminal and the second clock terminal;
and a pull-up node control stage: providing a turn-on signal to the first clock terminal and the second clock terminal, and providing a turn-off signal to the input terminal and the reset terminal;
and an output signal attenuation stage: providing a conducting signal to the second clock end and providing a switching-off signal to the input end, the reset end and the first clock end;
a reset phase: an on signal is provided to the reset terminal and an off signal is provided to the input terminal, the first clock terminal and the second clock terminal.
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| CN111477193B (en) | 2022-04-26 |
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