CN112951146A

CN112951146A - Shift register, driving method, scanning driving circuit, display panel and device

Info

Publication number: CN112951146A
Application number: CN202110448731.2A
Authority: CN
Inventors: 李东华; 魏晓丽; 伍黄尧
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2021-04-25
Filing date: 2021-04-25
Publication date: 2021-06-11
Anticipated expiration: 2041-04-25
Also published as: CN112951146B

Abstract

The embodiment of the invention discloses a shift register, a driving method, a scanning driving circuit, a display panel and a device, wherein the shift register comprises a first node control module, a second node control module, an output module, a node mutual control module and a pull-down module; the first node control module is respectively electrically connected with the scanning control end and the signal input end, and is also electrically connected with the output module at a first node; the second node control module is respectively electrically connected with the first reference signal end, the first clock signal end and the scanning control end, and is also electrically connected with the output module at a second node; the output module is also electrically connected with a second clock signal end, a second reference signal end and a scanning signal output end respectively; the node mutual control module is respectively electrically connected with the first node, the second node and the second reference signal end; the pull-down module is electrically connected with the pull-down control end, the pull-down signal end and the second node respectively. The technical scheme of the embodiment of the invention can improve the driving capability of the shift register and ensure normal display.

Description

Shift register, driving method, scanning driving circuit, display panel and device

Technical Field

Embodiments of the present invention relate to display technologies, and in particular, to a shift register, a driving method, a scan driving circuit, a display panel, and a display device.

Background

With the continuous development of display technologies, the display panel is also applied more and more widely, for example, the display panel is applied to products such as mobile phones, computers, tablet computers, electronic books and information query machines, and in addition, the display panel can also be applied to instrument displays (such as vehicle-mounted displays) and control panels of smart homes.

The conventional display panel scans pixels of each row line by line through a scanning circuit, thereby displaying a picture. The scanning circuit comprises a plurality of cascaded shift registers, and the shift registers realize the function of line-by-line scanning through the circuit structure of a plurality of thin film transistors and capacitors. However, during the scanning driving, due to an excessively high or low temperature or aging of the device, an abnormal on state of the thin film transistor may occur, which affects an output signal of the shift register, thereby causing an abnormal display.

Disclosure of Invention

The embodiment of the invention provides a shift register, a driving method, a scanning driving circuit, a display panel and a device, which are used for improving the driving capability of the shift register and ensuring normal display.

In a first aspect, an embodiment of the present invention provides a shift register, including: the device comprises a first node control module, a second node control module, an output module, a node mutual control module, a pull-down module, a scanning control end, a signal input end, a first clock signal end, a second clock signal end, a first reference signal end, a second reference signal end, a scanning signal output end, a pull-down control end and a pull-down signal end;

the first node control module is electrically connected with the scanning control end and the signal input end respectively; the first node control module is also electrically connected with the output module to a first node; in the charging stage, the first node control module is used for charging the first node under the control of a scanning control signal of the scanning control end and an input signal of the signal input end;

the second node control module is respectively and electrically connected with the first reference signal terminal, the first clock signal terminal and the scanning control terminal; the second node control module is also electrically connected with the output module to a second node; in a reset phase, the second node control module is used for transmitting the first reference potential of the first reference signal end to the second node under the control of the scanning control signal and the first clock signal of the first clock signal end;

the output module is also electrically connected with a second clock signal end, a second reference signal end and a scanning signal output end respectively; in the charging stage, the output module is used for outputting a second clock signal of the second clock signal end to the scanning signal output end under the control of the electric potential of the first node; in the reset stage, the output module is used for outputting a second reference signal of the second reference signal end to the scanning signal output end under the control of the potential of the second node;

the node mutual control module is respectively electrically connected with the first node, the second node and the second reference signal end; in the charging stage, the node mutual control module is used for controlling a second reference potential of a second reference signal end to be transmitted to a second node according to the potential of the first node; in the reset stage, the node mutual control module is used for controlling a second reference potential of a second reference signal end to be transmitted to the first node according to the potential of the second node;

the pull-down module is electrically connected with the pull-down control end, the pull-down signal end and the second node respectively; in the charging stage, the pull-down module is used for transmitting the non-enabling level of the pull-down signal to the second node under the control of the pull-down control signal.

In a second aspect, an embodiment of the present invention further provides a driving method for a shift register, which is implemented by using the shift register provided in one aspect of the claims, where the driving method includes:

in the charging stage, the scanning control end provides an enabling level of a scanning control signal, the signal input end provides an enabling level of an input signal, and the first node control module is controlled to charge the first node; the node mutual control module controls a second reference potential to be transmitted to a second node according to the potential of the first node; the pull-down control end provides an enabling level of a pull-down control signal, the pull-down signal end provides a non-enabling level of the pull-down signal, and the pull-down module is controlled to pull down the potential of the second node; the output module outputs a second clock signal of a second clock signal end to the scanning signal output end under the control of the electric potential of the first node;

in the signal output stage, the second clock signal end provides the enable level of the second clock signal, and the output module outputs the enable level of the second clock signal under the control of the potential of the first node;

in a reset stage, the scanning control end provides an enabling level of a scanning control signal, the first clock signal end provides an enabling level of a first clock signal, and the second node control module is controlled to transmit a first reference potential of the first reference signal end to the second node; the node mutual control module controls a second reference potential of a second reference signal end to be transmitted to the first node according to the potential of the second node; the output module outputs a second reference signal of the second reference signal terminal to the scanning signal output terminal under the control of the potential of the second node.

In a third aspect, an embodiment of the present invention further provides a scan driving circuit, including: a plurality of shift registers provided in the first aspect; a plurality of shift registers are arranged in cascade.

In a fourth aspect, an embodiment of the present invention further provides a display panel, including: the third aspect provides a scan driving circuit.

In a fifth aspect, an embodiment of the present invention further provides a display device, including: the fourth aspect provides a display panel.

In the shift register provided in the embodiment of the present invention, by additionally providing the pull-down module, in the charging stage, the pull-down module transmits the disable level of the pull-down signal to the second node under the control of the pull-down control signal, so that the potential of the second node can be controlled by the node mutual control module and the pull-down module, and it is ensured that the potential of the second node is the disable level in the charging stage, and thus it is ensured that the second reference potential is not transmitted to the first node, and the influence of the second reference potential on the potential of the first node due to the leakage current of the transistor is avoided, and further, the influence on the output signal of the scan signal output end is avoided, the driving capability of the shift register is improved, and normal display is ensured.

Drawings

Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a specific structure of a shift register according to an embodiment of the present invention;

FIG. 3 is a timing diagram of a shift register according to an embodiment of the present invention;

FIG. 4 is a timing diagram illustrating driving operations of another shift register according to an embodiment of the present invention;

FIG. 5 is a timing diagram illustrating driving operations of another shift register according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another shift register according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of another shift register according to an embodiment of the present invention;

FIG. 8 is a timing diagram of the driving of the shift register during forward scanning according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of another shift register according to an embodiment of the present invention;

fig. 10 is a flowchart illustrating a driving method of a shift register according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a scan driving circuit according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention, and referring to fig. 1, the shift register includes: the first node control module 10, the second node control module 20, the output module 30, the node inter-control module 40, the pull-DOWN module 50, a scan control terminal (e.g., the forward scan control terminal U2D), a signal input terminal (e.g., the forward scan signal input terminal INF), a first clock signal terminal (e.g., the first forward scan clock signal terminal RSTF), a second clock signal terminal OUT, a first reference signal terminal VGH, a second reference signal terminal VGL, a scan signal output terminal GOUT, a pull-DOWN control terminal DC, and a pull-DOWN signal terminal DOWN.

The first node control module 10 is electrically connected to a scan control terminal (e.g., U2D) and a signal input terminal (e.g., INF), respectively; the first node control module 10 is further electrically connected to the output module 30 at a first node N1; in the charging phase, the first node control module 10 is configured to charge the first node N1 under the control of the scan control signal of the scan control terminal and the input signal of the signal input terminal. The second node control module 20 is electrically connected to the first reference signal terminal VGH, the first clock signal terminal (e.g., RSTF), and the scan control terminal (e.g., U2D), respectively; the second node control module 20 is further electrically connected to the output module 30 at a second node N2; in the reset phase, the second node control module 20 is configured to transmit the first reference potential of the first reference signal terminal VGH to the second node N2 under the control of the scan control signal and the first clock signal of the first clock signal terminal. The output module 30 is further electrically connected to the second clock signal terminal OUT, the second reference signal terminal VGL, and the scan signal output terminal GOUT, respectively; in the charging phase, the output module 30 is configured to output the second clock signal of the second clock signal terminal OUT to the scan signal output terminal GOUT under the control of the potential of the first node N1; in the reset phase, the output module 30 is configured to output the second reference signal of the second reference signal terminal VGL to the scan signal output terminal GOUT under the control of the potential of the second node N2. The node mutual control module 40 is electrically connected to the first node N1, the second node N2 and the second reference signal terminal VGL respectively; in the charging phase, the node mutual control module 40 is configured to control the second reference potential of the second reference signal terminal VGL to be transmitted to the second node N2 according to the potential of the first node N1; in the reset phase, the node mutual control module 40 is configured to control the second reference potential of the second reference signal terminal VGL to be transmitted to the first node N1 according to the potential of the second node N2. The pull-DOWN module 50 is electrically connected with a pull-DOWN control terminal DC, a pull-DOWN signal terminal DOWN and a second node N2 respectively; in the charging phase, the pull-down module 50 is configured to transmit the disable level of the pull-down signal to the second node N2 under the control of the pull-down control signal.

Specifically, in the charging phase, the scan control terminal (e.g., U2D) provides an enable level of the scan control signal, and the signal input terminal (e.g., INF) provides an enable level of the input signal, so as to control the first node control module 10 to charge the first node N1, so that the potential of the first node N1 is at the enable level, and thus the node mutual control module 40 can control the second reference potential of the second reference signal terminal VGL to be transmitted to the second node N2 according to the potential of the first node N1, and the potential of the second node N2 is at the disable level, so that the second reference potential is not transmitted to the scan signal output terminal GOUT; the output module 30 can output the second clock signal of the second clock signal terminal OUT to the scan signal output terminal GOUT under the control of the potential of the first node N1, and when the second clock signal terminal OUT provides the enable level, the enable level of the scan signal can be provided to the corresponding gate line. In addition, the embodiment of the present invention further adds the pull-DOWN module 50, in the charging stage, the pull-DOWN control terminal DC provides an enable level of the pull-DOWN control signal, and the pull-DOWN signal terminal DOWN provides a disable level of the pull-DOWN signal, so that the pull-DOWN module 50 can be controlled to pull DOWN the potential of the second node N2, and thus the node mutual control module 40 and the pull-DOWN module 50 can be utilized to perform dual control on the potential of the second node N2, and it is ensured that the potential of the second node N2 is the disable level in the charging stage, and further it is ensured that the second reference potential is not transmitted to the first node N1 in the charging stage, and it is avoided that the second reference potential causes an influence on the potential of the first node N1 due to transistor leakage current, and further, the influence on the output signal of the scanning signal output terminal GOUT is avoided, the driving capability of the shift register is improved, and.

In the reset stage, the scan control terminal (e.g., U2D) provides an enable level of the scan control signal, the first clock signal terminal (e.g., RSTF) provides an enable level of the first clock signal, the second node control module 20 is controlled to transmit the first reference voltage of the first reference signal terminal VGH to the second node N2 to enable the voltage level of the second node N2 to be in an enable level state, so that the node interlock module 40 can control the second reference voltage of the second reference signal terminal VGL to be transmitted to the first node N1 according to the voltage level of the second node N2, the voltage level of the first node N1 is in a non-enable level state, so that the second clock signal of the second clock signal terminal OUT is not transmitted to the scan signal output terminal GOUT, and the output module 30 can output the second reference signal terminal VGL to the scan signal output terminal GOUT under the control of the voltage level of the second node N2, and realizing reset.

For example, the thin film transistor in the shift register may be an N-type transistor, and in this case, the enable level of the output signal of each signal terminal is at a high level, and the disable level is at a low level.

Fig. 2 is a schematic diagram of a specific structure of a shift register according to an embodiment of the present invention, and referring to fig. 2, optionally, the scan control terminal includes a forward scan control terminal U2D, the signal input terminal includes a forward scan signal input terminal INF, and the first clock signal terminal includes a first forward scan clock signal terminal RSTF; the first node control module 10 includes a first transistor M1, a gate of the first transistor M1 is electrically connected to the positive scan signal input terminal INF, a first pole of the first transistor M1 is electrically connected to the positive scan control terminal U2D, and a second pole of the first transistor M1 is electrically connected to the first node N1; the pull-DOWN module 50 includes a third transistor M3, a gate of the third transistor M3 is electrically connected to the pull-DOWN control terminal DC, a first pole of the third transistor M3 is electrically connected to the pull-DOWN signal terminal DOWN, and a second pole of the third transistor M3 is electrically connected to the second node N2; the second node control module 20 includes a fifth transistor M5 and a seventh transistor M7, a gate of the fifth transistor M5 is electrically connected to the forward scan control terminal U2D, a first pole of the fifth transistor M5 is electrically connected to the first forward scan clock signal terminal RSTF, a second pole of the fifth transistor M5 is electrically connected to a gate of the seventh transistor M7, a first pole of the seventh transistor M7 is electrically connected to the first reference signal terminal VGH, and a second pole of the seventh transistor M7 is electrically connected to the second node N2; the node mutual control module 40 comprises an eighth transistor M8 and a ninth transistor M9, a gate of the eighth transistor M8 is electrically connected to the second node N2, a first pole of the eighth transistor M8 is electrically connected to the second reference signal terminal VGL, a second pole of the eighth transistor M8 is electrically connected to the first node N1, a gate of the ninth transistor M9 is electrically connected to the first node N1, a first pole of the ninth transistor M9 is electrically connected to the second reference signal terminal VGL, and a second pole of the ninth transistor M9 is electrically connected to the second node N2; the output module 30 includes a tenth transistor M10, an eleventh transistor M11, a first capacitor C1, and a second capacitor C2; a gate of the tenth transistor M10 and a first end of the first capacitor C1 are both electrically connected to the first node N1; a first pole of the tenth transistor M10 is electrically connected to the second clock signal terminal OUT; a second pole of the tenth transistor M10 and a second end of the first capacitor C1 are both electrically connected to the scan signal output terminal GOUT; a gate of the eleventh transistor M11 and a first end of the second capacitor C2 are both electrically connected to the second node N2; a first pole of the eleventh transistor M11 and a second end of the second capacitor C2 are both electrically connected to the second reference signal terminal VGL; a second pole of the eleventh transistor M11 is electrically connected to the scan signal output terminal GOUT; wherein the eighth transistor M8 has the same channel type as the eleventh transistor M11; the ninth transistor M9 is the same channel type as the tenth transistor M10.

Fig. 2 illustrates the thin film transistors in the shift register as N-type transistors, but the structure is not limited thereto. Fig. 3 is a driving timing diagram of a shift register according to an embodiment of the present invention, and with reference to fig. 2 and fig. 3, the operation process of the shift register is as follows:

in the charging period T1, the forward scan signal input terminal INF inputs a high level, the first transistor M1 is turned on, and the forward scan control terminal U2D inputs a high level to charge the first node N1 and pull it high. Since the first node N1 is at a high level, the tenth transistor M10 is turned on, and the second clock signal of the second clock signal terminal OUT is transmitted to the scan signal output terminal GOUT (the second clock signal may be at a non-enable level during the charging phase). Meanwhile, since the first node N1 is at a high level, the ninth transistor M9 is turned on, so that the second reference potential of the second reference signal terminal VGL is transmitted to the second node N2, the potential of the second node N2 is reduced, and the eighth transistor M8 and the eleventh transistor M11 are turned off, the second reference potential is not transmitted to the scan signal output terminal GOUT and the first node N1, and further, since the pull-DOWN control terminal DC is input at a high level, the third transistor M3 is turned on, and the pull-DOWN signal terminal DOWN is input at a low level to pull DOWN the potential of the second node N2, so that the potential of the second node N2 is further ensured to be at a low level, the second reference potential of the second reference signal terminal VGL is ensured not to be transmitted to the first node N1, and the situation that the tenth transistor M10 cannot be turned on due to the fact that the second reference potential of the first node N1 is pulled DOWN by the leakage current of the eighth transistor M8 is avoided, the potential of the first node N1 is guaranteed to meet the conduction condition of the tenth transistor M10, and the driving capability of the shift register is improved.

In the signal output stage T2, since the first capacitor C1 stores the potential of the first node N1, the potential of the first node N1 is maintained at a high level, and the tenth transistor M10 is in a turned-on state, and in this stage, the second clock signal terminal OUT inputs a high level (enable level) so that the scan signal output terminal GOUT outputs a high level, and the shift register supplies the scan signal to the corresponding gate line.

In the reset period T3, the forward scan control terminal U2D inputs a high level, the fifth transistor M5 is turned on, and the first forward scan clock signal terminal RSTF inputs a high level, so that the seventh transistor M7 is turned on, the first reference potential of the first reference signal terminal VGH is transmitted to the second node N2, and the potential of the second node N2 is pulled up. Since the second node N2 is at a high level, the eighth transistor M8 and the eleventh transistor M11 are turned on, the second reference signal of the second reference signal terminal VGL is transmitted to the first node N1, the potential of the first node N1 is pulled down, so that the tenth transistor M10 is turned off, the second clock signal of the second clock signal terminal OUT is not transmitted to the scan signal output terminal GOUT, and since the eleventh transistor M11 is turned on, the second reference signal of the second reference signal terminal VGL is transmitted to the scan signal output terminal GOUT, and the shift register resets the signal on the gate line.

As shown in fig. 3, the signals output by the forward scan signal input terminal INF and the pull-DOWN control terminal DC are the same, so in other embodiments, the forward scan signal input terminal INF can be multiplexed into the pull-DOWN control terminal DC, and in addition, the second reference signal terminal VGL can be multiplexed into the pull-DOWN signal terminal DOWN, so as to avoid adding pins required by the driver chip and ensure the practicability of the existing driver chip.

For example, fig. 4 is a timing diagram of driving another shift register according to an embodiment of the present invention, referring to fig. 4, alternatively, the scan control terminal (e.g., the forward scan control terminal U2D) provides the enable level of the scan control signal during the charging period T1 and the reset period T3, and provides the disable level of the scan control signal during the pause period T4; the signal input terminal (e.g., the positive direction scan signal input terminal INF) provides the enable level of the input signal during the charging period T1, and provides the disable level of the input signal during the rest period T4 and the reset period T3; in the intermittent period T4, the first node control module 10 is configured to be in a non-biased state under the control of the scan control signal and the input signal.

Specifically, the scan control terminal of each shift register of the scan driving circuit is usually connected to the same scan control line, and the scan control line is used for transmitting the enable level of the scan control signal to the scan control terminal thereof in the charging stage and the reset stage of each shift register.

As shown in FIG. 2, after the charging of the first node N1 of the shift register is completed, the first node control module 10 is in the negative bias state until the next charging of the first node N1 of the shift register. Taking the first node control module including the first transistor M1 as an example, during the period from the end of the charging phase to the start of the next charging phase, if the gate potential Vg of the first transistor M1 is at a low level and the source potential Vs of the first transistor M1 is at a high level, the first transistor M1 will be in a negative bias state for a long time because Vg < Vs, and the long-time negative bias state may affect the performance of the first transistor M1, so that the threshold of the first transistor M1 may drift, and when the charging phase is entered again, the first transistor M1 cannot be controlled to meet the conduction condition of Vgs > Vth in an accurate time period, so that the first node control module 10 in the charging phase is abnormally turned on, or even cannot be turned on. Referring to fig. 2 and 4, in this embodiment, the scan control terminal is set to provide the non-enable level of the scan control signal in the intermittent stage, so that the first node control module 10 is in a non-biased state in this stage, thereby avoiding adverse effects caused by long-term negative bias, and further enabling the shift register to output an accurate scan signal. Still taking the example that the first node control module includes the first transistor M1, in the intermittent period T4, the gate potential of the first transistor M1 is at a low level, and the source potential of the first transistor M1 is at a low level, so that the first transistor M1 is in a non-biased state.

Illustratively, as shown in fig. 4, the intermittent phase T4 may be located after the reset phase T3. Therefore, in the whole scanning process, the first node control module 10 of any shift register is alternately in the negative bias state and the non-bias state after the charging stage is finished until the next charging stage is started, so that the situation that the subsequent charging stage cannot be normally conducted due to long-term negative bias can be avoided.

With continued reference to fig. 4, further optionally, the second clock signal terminal OUT is used for providing the disable level of the second clock signal during the charging phase T1, the reset phase T3 and the pause phase T4, and providing the enable level of the second clock signal during the signal output phase T2; the scan control terminal (e.g., the forward scan control terminal U2D) is further used for providing an enable level of the scan control signal during the signal output period T2; the signal input terminal (e.g., the positive scan signal input terminal INF) is further used for providing a non-enable level of the input signal during the signal output stage T2; the signal output phase T2 is between the charging phase T1 and the reset phase T3.

In the charging phase T1, the first node control module 10 charges the first node N1, and the first node N1 is maintained at the enable level for a period of time after the charging phase is ended, so that the first node N1 has a relatively stable potential; at this time, the signal output stage T2 can be entered, and the second clock signal terminal OUT provides the enable level of the second clock signal, which is output by the output module 30, so as to ensure that the enable level of the scan signal output by the output module 30 to the scan signal output terminal GOUT is more stable. In addition, in the signal output stage T2, the scan control terminal (e.g., the forward scan control terminal U2D) provides the enable level of the scan control signal, so that the potentials at the two ends of the first node control module 10 are relatively balanced, thereby preventing the first node control module 10 (e.g., the first transistor M1) from leaking to affect the potential of the first node N1, and ensuring the driving capability of the shift register.

In the driving sequence shown in fig. 4, the positions of the intermittent stages in the driving period of the shift register are only illustrative and not limiting. Exemplarily, fig. 5 is a driving timing diagram of another shift register provided by the embodiment of the invention, referring to fig. 5, and optionally, the intermittent phase includes a first intermittent phase T41, a second intermittent phase T42, and a third intermittent phase T43; the first intermittent phase T41 is located between the charging phase T1 and the signal output phase T2; the second intermittent phase T42 is located between the signal output phase T2 and the reset phase T3; the third intermittent phase T43 is located after the reset phase T3, or the third intermittent phase T43 is located before the charging phase T1.

Fig. 5 illustrates the third intermittent phase T43 after the reset phase T3. As shown in fig. 5, during the driving period of the shift register, the positive direction scan control terminal U2D provides the disable level during the first intermittent period T41, the second intermittent period T42 and the third intermittent period T43, so that the duration of the negative bias of the first node control module 10 can be further shortened, and the first node control module 10 is alternately in the negative bias state (such as the signal output period T2 and the reset period T3) for a shorter time and in the non-bias state (such as the intermittent periods T41, T42 and T43) for a shorter time, thereby ensuring that the first node control module 10 in the shift register can be normally turned on in the subsequent charging period.

In summary, on the basis that the pull-down module 50 is configured to pull down the potential of the second node N2 to ensure that the potential of the first node N1 is not affected by the second reference potential of the second reference signal terminal VGL, the output signal of the scan control terminal is set to be a pulse signal to ensure that the first node control module 10 can be normally turned on in the charging stage, so as to ensure the charging capability of the first node N1, further improve the driving capability of the shift register, and ensure normal display.

It should be noted that, in the above embodiment, the scan control terminal includes the forward scan control terminal U2D, the signal input terminal includes the forward scan signal input terminal INF, and the first clock signal terminal includes the first forward scan clock signal terminal RSTF, which is only an example, so that forward scanning (scanning from the first row to the nth row in sequence, where N is a positive integer greater than 1) can be implemented on the pixels of the display area, and the structure is not limited. In other embodiments, referring to the schematic structural diagram of another shift register provided in the embodiment of the present invention shown in fig. 6, optionally, the scan control terminal includes a forward scan control terminal U2D and a reverse scan control terminal D2U; the signal input end comprises a forward scanning signal input end INF and a reverse scanning signal input end INB; the first clock signal terminal includes a first forward scan clock signal terminal RSTF and a first reverse scan clock signal terminal RSTB.

The forward direction scan control terminal U2D is used for providing an enable level of a forward direction scan control signal in a charging phase and a reset phase of a forward direction scan; the reverse scan control terminal D2U is used for providing an enable level of a reverse scan control signal in a charge phase and a reset phase of a reverse scan; the positive scanning signal input terminal INF is used for providing an enabling level of a positive input signal in a charging phase of positive scanning; the reverse scanning signal input terminal INB is used for providing an enable level of a reverse input signal in a charging phase of the reverse scanning; the first forward direction scanning clock signal end RSTF is used for providing an enabling level of the first forward direction scanning clock signal in a reset phase of forward direction scanning; the first reverse scan clock signal terminal RSTB is for providing an enable level of the first reverse scan clock signal during a reset phase of the reverse scan. In addition, the forward direction scan control terminal U2D is further used for providing the enable level of the forward direction scan control signal during the signal output phase of the forward direction scan, and the reverse direction scan control terminal D2U is further used for providing the enable level of the reverse direction scan control signal during the signal output phase of the reverse direction scan.

With such an arrangement, the display area can be scanned in a forward direction or a reverse direction (sequentially scanned from the nth row to the 1 st row, where N is a positive integer greater than 1) as required. Specifically, during forward scanning, signals required by corresponding modules are provided through a forward scanning control end U2D, a forward scanning signal input end INF and a first forward scanning clock signal end RSTF; in the reverse scan, the signals required by the corresponding blocks are provided through the reverse scan control terminal D2U, the reverse scan signal input terminal INB, and the first reverse scan clock signal terminal RSTB.

Further, with continued reference to fig. 6, optionally, the pull-down signal terminal includes a forward pull-down signal terminal and a reverse pull-down signal terminal; the pull-down control end comprises a forward pull-down control end and a reverse pull-down control end; the forward scanning signal input end INF is multiplexed as a forward pull-down control end, and the reverse scanning signal input end INB is multiplexed as a reverse pull-down control end; the forward scanning control end U2D is multiplexed as a reverse pull-down signal end, and the reverse scanning control end D2U is multiplexed as a forward pull-down signal end; in the charge phase of the forward scan, the pull-down module 50 is configured to transmit the disable level of the forward pull-down signal terminal (i.e., D2U) to the second node N2 under the control of the forward pull-down control signal of the forward pull-down control terminal (i.e., INF); in the charge phase of the reverse scan, the pull-down module 50 is configured to transmit the disable level of the reverse pull-down signal terminal (i.e., U2D) to the second node N2 under the control of the reverse pull-down control signal of the reverse pull-down control terminal (i.e., INB).

Specifically, during the charging phase of the forward scan, the enable level provided by the forward scan signal input terminal INF controls the first node control module 10 to be turned on, so that the forward scan signal input terminal INF can be multiplexed as the forward pull-down control terminal to control the pull-down module 50 to be turned on during the charging phase, so that the disable level of the forward pull-down signal terminal is transmitted to the second node N2, and the potential of the second node N2 is at the disable level. In addition, during the forward scan phase, a signal opposite to the forward scan control terminal U2D may be provided through the reverse scan control terminal D2U, for example, during the charge phase of the forward scan, the reverse scan control terminal D2U provides a disable level, so that the reverse scan control terminal D2U may be multiplexed as a forward pull-down signal terminal. Similarly, the inverse scan signal input terminal INB may be multiplexed as an inverse pull-down control terminal, and the forward scan control terminal U2D may be multiplexed as an inverse pull-down signal terminal. Therefore, pins required by the driving chip can be prevented from being added, and the practicability of the existing driving chip is guaranteed.

Correspondingly, fig. 7 is a schematic diagram of a specific structure of another shift register according to an embodiment of the present invention, and referring to fig. 7, optionally, the first node control module 10 includes a first transistor M1 and a second transistor M2; the pull-down module 50 includes a third transistor M3 and a fourth transistor M4; the gate of the first transistor M1 and the gate of the third transistor M3 are both electrically connected to the forward scan signal input terminal INF; the gate of the second transistor M2 and the gate of the fourth transistor M4 are both electrically connected to the reverse scan signal input terminal INB; a first pole of the first transistor M1 and a first pole of the fourth transistor M4 are both electrically connected to the forward scan control terminal U2D; a first pole of the second transistor M2 and a first pole of the third transistor M3 are both electrically connected to the reverse scan control terminal D2U; a second pole of the first transistor M1 and a second pole of the second transistor M2 are both electrically connected to the first node N1; a second pole of the third transistor M3 and a second pole of the fourth transistor M4 are both electrically connected to the second node N2; wherein, the channel type of the first transistor M1 is the same as the channel type of the third transistor M3, and the channel type of the second transistor M2 is the same as the channel type of the fourth transistor M4.

With continued reference to FIG. 7, optionally, the second node control module 20 includes a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7; a gate of the fifth transistor M5 is electrically connected to the forward scan control terminal U2D, and a first pole of the fifth transistor M5 is electrically connected to the first forward scan clock signal terminal RSTF; a gate of the sixth transistor M6 is electrically connected to the reverse scan control terminal D2U, and a first pole of the sixth transistor M6 is electrically connected to the first reverse scan clock signal terminal RSTB; a second pole of the fifth transistor M5 and a second pole of the sixth transistor M6 are both electrically connected to the gate of the seventh transistor M7; a first pole of the seventh transistor M7 is electrically connected to the first reference signal terminal VGH, and a second pole of the seventh transistor M7 is electrically connected to the second node N2.

For example, fig. 7 illustrates that the thin film transistors in the shift register are all N-type transistors. Fig. 8 is a driving timing diagram of the shift register during forward scanning according to an embodiment of the present invention, and with reference to fig. 7 and 8, the operation process of the shift register is as follows:

in the charging period T1, the forward scan signal input terminal INF inputs a high level, the first transistor M1 and the third transistor M3 are turned on, so that the high level input from the forward scan control terminal U2D charges the first node N1 through the first transistor M1, thereby pulling up the potential of the first node N1, and the low level input from the reverse scan control terminal D2U is transmitted to the second node N2 through the third transistor M3, thereby lowering the potential of the second node N2. In addition, since the potential of the first node N1 rises, the ninth transistor M9 and the tenth transistor M10 are turned on, so that the second clock signal of the second clock signal terminal OUT is transmitted to the scan signal output terminal GOUT through the tenth transistor M10, and the second clock signal may be at a low level; the low level of the second reference signal end VGL input is transmitted to the second node N2 through the ninth transistor M9, the potential of the second node N2 is also pulled down, so that the potential of the second node N2 is controlled doubly through the node mutual control module 40 and the pull-down module 50, and it is ensured that the potential of the second node N2 is low level in the charging stage, so that it is ensured that the second reference signal of the second reference signal end VGL does not affect the potential of the first node N1, and the driving capability of the shift register is ensured.

In the first intermittent period T41, the forward direction scan signal input terminal INF inputs a low level, and the forward direction scan control terminal U2D inputs a low level, so that the first transistor M1 is in a non-biased state.

In the signal output stage T2, the potential of the first node N1 is at a high level, so that the tenth transistor M10 is turned on, the high level signal inputted from the second clock signal terminal OUT is transmitted to the scan signal output terminal GOUT through the tenth transistor M10, and the shift register provides the scan signal to the corresponding gate line. At this stage, since the positive direction scan signal input terminal INF is at a low level and the positive direction scan control terminal U2D is at a high level, the first transistor M1 is in a negative bias state.

In the second intermittent period T42, the forward direction scan signal input terminal INF inputs a low level, and the forward direction scan control terminal U2D inputs a low level, so that the first transistor M1 is in a non-biased state.

In the reset period T3, the forward scan control terminal U2D inputs a high level, the fifth transistor M5 is turned on, and the first forward scan clock signal terminal RSTF inputs a high level, so that the seventh transistor M7 is turned on, the high level input by the first reference signal terminal VGH is transmitted to the second node N2, and the potential of the second node N2 is pulled up. Since the second node N2 is at a high level, the eighth transistor M8 and the eleventh transistor M11 are turned on, the low level of the second reference signal terminal VGL is transmitted to the first node N1, the potential of the first node N1 is pulled down, so that the tenth transistor M10 is turned off, the second clock signal of the second clock signal terminal OUT is not transmitted to the scan signal output terminal GOUT, and since the eleventh transistor M11 is turned on, the low level signal of the second reference signal terminal VGL is transmitted to the scan signal output terminal GOUT, so as to reset the signal on the gate line. At this stage, since the positive direction scan signal input terminal INF is at a low level and the positive direction scan control terminal U2D is at a high level, the first transistor M1 is in a negative bias state.

In the third intermittent period T43, the forward direction scan signal input terminal INF inputs a low level, and the forward direction scan control terminal U2D inputs a low level, so that the first transistor M1 is in a non-biased state.

Therefore, after the charging stage T1 is finished, the first transistor M1 is alternately in the non-biased state and the negative biased state, and in the working process of the next stage shift register, the first transistor M1 of the stage shift register is also alternately in the non-biased state and the negative biased state until the stage shift register enters the next charging stage, so that the situation that the first transistor M1 is in the negative biased state for a long time to cause conduction abnormality can be avoided, the charging capability of the first node N1 is ensured, and the driving capability of the shift register is further ensured.

On the basis of any of the above embodiments, fig. 9 is a schematic diagram of a specific structure of another shift register provided in the embodiment of the present invention, referring to fig. 9, optionally, the first node includes a first a node N1a and a first b node N1 b; the first node control module 10 is electrically connected with a first node A N1a, and the output module 30 is electrically connected with a first node B N1 b; the shift register further comprises a voltage stabilization protection module 60; the voltage stabilizing protection module 60 is electrically connected to the first reference signal terminal VGH, the first node a N1a and the first node b N1b, respectively; the voltage regulation protection module 60 is configured to maintain the voltage level of the first node a N1a to be less than or equal to a predetermined voltage value under the control of the first reference signal terminal VGH and the first node b N1 b.

Since the output module 30 is electrically connected to the scanning signal output terminal GOUT, and the scanning signal output terminal GOUT is electrically connected to the gate line in the display area, if the potential of the scanning signal output terminal GOUT is suddenly increased due to static electricity or other reasons, the potential is conducted to the first node through the first capacitor, and then flows back to the driving chip through the first node control module 10, thereby damaging the driving chip. In the embodiment of the invention, the voltage stabilization protection module 60 is arranged between the first node N1a and the first second node N1b, so that the voltage stabilization protection module 60 is electrically connected with the first reference signal terminal VGH, and thus, when the potential of the first second node N1b suddenly rises due to static electricity and the like, the voltage stabilization protection module 60 can be controlled to be closed, so that the potential of the first node N1a is smaller than or equal to a preset voltage value, and the high potential is prevented from flowing back to the driving chip. In addition, when the potential of the scanning signal output terminal GOUT is not abnormal, the voltage stabilization protection module 60 can be continuously turned on under the control of the first reference signal terminal VGH, and the normal operation of the shift register is not affected.

For example, referring to fig. 9, the regulated protection module 60 includes a twelfth transistor M12, a gate of the twelfth transistor M12 is electrically connected to the first reference signal terminal VGH, a source of the twelfth transistor M12 is electrically connected to the first second node N1b, and a drain of the twelfth transistor M12 is electrically connected to the first node N1 a.

With continued reference to fig. 9, optionally, the shift register further includes a first node potential adjusting module 70, a second node potential adjusting module 80, and a start control terminal GAS; the start control terminal GAS is used for providing an enabling level of a start control signal in a start phase; the first node potential adjusting module 70 is electrically connected to the start control terminal GAS, the first reference signal terminal VGH and the scanning signal output terminal GOUT, respectively; in the start-up phase, the first node potential adjusting module 70 is configured to transmit the first reference potential to the scanning signal output terminal GOUT under the control of the start-up control signal; the second node potential adjusting module 80 is electrically connected to the start control terminal GAS, the second reference signal terminal VGL and the second node N2 respectively; in the start-up phase, the second node potential adjusting module 80 is configured to transmit a second reference potential to the second node N2 under the control of the start-up control signal; wherein the start-up phase precedes the charge phase and the reset phase.

Specifically, during the start-up phase, the scan signal output terminals GOUT of all the shift registers are required to output high level signals simultaneously. To achieve this, the present embodiment provides a first node potential adjusting block 70 and a second node potential adjusting block 80, the first node potential adjusting module 70 is electrically connected to the start control terminal GAS, the first reference signal terminal VGH and the scan signal output terminal GOUT, respectively, the second node potential adjusting module 80 is electrically connected to the start control terminal GAS, the second reference signal terminal VGL and the second node N2, respectively, in this way, in the start-up phase, the start-up control terminal GAS provides the enable level of the start-up control signal to turn on the first node potential adjusting module 70 and the second node potential adjusting module 80, so that the first reference potential is transmitted to the scanning signal output terminal GOUT, the high level signals are simultaneously outputted to all the gate lines, and at the same time, the second reference potential is transmitted to the second node N2, the potential of the second node N2 is pulled down, the eleventh transistor M11 is turned off, and the second reference potential is not transmitted to the scan signal output terminal GOUT.

For example, referring to fig. 9, the first node potential adjusting module 70 includes a thirteenth transistor M13, the second node potential adjusting module 80 includes a fourteenth transistor M14, a gate of the thirteenth transistor M13 and a gate of the fourteenth transistor M14 are electrically connected to the start control terminal GAS, a first pole of the thirteenth transistor M13 is electrically connected to the first reference signal terminal VGH, a second pole of the thirteenth transistor M13 is electrically connected to the scan signal output terminal GOUT, a first pole of the fourteenth transistor M14 is electrically connected to the second reference signal terminal VGL, and a second pole of the thirteenth transistor M13 is electrically connected to the second node N2.

Based on the same inventive concept, an embodiment of the present invention further provides a driving method of a shift register, which is implemented by using the shift register provided in any of the above embodiments, and fig. 10 is a schematic flow chart of the driving method of the shift register provided in the embodiment of the present invention, and referring to fig. 10, the driving method includes:

s101, in a charging stage, a scanning control end provides an enabling level of a scanning control signal, a signal input end provides an enabling level of an input signal, and a first node control module is controlled to charge a first node; the node mutual control module controls a second reference potential to be transmitted to a second node according to the potential of the first node; the pull-down control end provides an enabling level of a pull-down control signal, the pull-down signal end provides a non-enabling level of the pull-down signal, and the pull-down module is controlled to pull down the potential of the second node; the output module outputs a second clock signal of the second clock signal terminal to the scanning signal output terminal under the control of the potential of the first node.

S102, in the signal output stage, the second clock signal end provides the enabling level of the second clock signal, and the output module outputs the enabling level of the second clock signal under the control of the potential of the first node.

S103, in a reset stage, the scanning control end provides an enabling level of a scanning control signal, the first clock signal end provides an enabling level of a first clock signal, and the second node control module is controlled to transmit a first reference potential of the first reference signal end to the second node; the node mutual control module controls a second reference potential of a second reference signal end to be transmitted to the first node according to the potential of the second node; the output module outputs a second reference signal of the second reference signal terminal to the scanning signal output terminal under the control of the potential of the second node.

In the driving method of the shift register provided in the embodiment of the present invention, in the charging stage, the node mutual control module controls the second reference potential to be transmitted to the second node according to the potential of the first node, meanwhile, the pull-down control end provides an enable level of the pull-down control signal, the pull-down signal end provides a non-enable level of the pull-down signal, the pull-down module is controlled to pull down the potential of the second node, thereby the potential of the second node can be controlled by the node mutual control module and the pull-down module to ensure that the potential of the second node is a non-enabling level in the charging stage, thereby ensuring that the second reference potential is not transmitted to the first node, avoiding the second reference potential from affecting the potential of the first node due to the leakage current of the transistor, therefore, the influence on the output signal of the scanning signal output end is avoided, the driving capability of the shift register is improved, and normal display is ensured.

On the basis of the above embodiment, the driving method may further include: in the intermittent stage, the scan control terminal provides a non-enable level of the scan control signal, and the signal input terminal provides a non-enable level of the input signal to control the first node control module to be in a non-bias state. Therefore, the adverse effect caused by the first node control module being in the negative bias for a long time can be avoided.

Illustratively, the batch phase may include a first batch phase, a second batch phase, and a third batch phase; the first intermittent stage is positioned between the charging stage and the signal output stage; the second intermittent stage is positioned between the signal output stage and the reset stage; the third intermittent phase is after the reset phase or the third intermittent phase is before the charge phase.

Based on the same inventive concept, an embodiment of the present invention further provides a scan driving circuit, where the scan driving circuit 100 includes a plurality of shift registers (ASGs) provided in any of the above embodiments; a plurality of shift registers are arranged in cascade. The scan driving circuit provided in the embodiment of the present invention also has the beneficial effects of the shift register in the foregoing embodiments, and the same points can be understood by referring to the explanation of the shift register in the foregoing, and are not described in detail below.

Fig. 11 is a schematic structural diagram of a scan driving circuit according to an embodiment of the present invention, which exemplarily shows 4 stages of shift registers, namely, a shift register ASG1 of a first stage, a shift register ASG2 of a second stage, a shift register ASG3 of a third stage, and a shift register ASG4 of a fourth stage, where the four stages of shift registers are arranged in cascade.

Specifically, referring to fig. 11, a forward scanning signal input terminal INF of the shift register ASG1 of the first stage is electrically connected to a forward start signal input terminal STVF of the scan driving circuit, a scanning signal output terminal GOUT i of the shift register of the i-th stage is electrically connected to a forward scanning signal input terminal INF of the shift register of the i + 1-th stage, and i is a positive integer, so that forward scanning can be realized. The reverse scan signal input terminal INB of the last stage shift register (for example, ASG4) is electrically connected to the reverse start signal input terminal STVB of the scan driving circuit, and the scan signal output terminal GOUT (i +1) of the (i +1) th stage shift register is electrically connected to the reverse scan signal input terminal INB of the i-th stage shift register, where i is a positive integer, so that reverse scan can be achieved.

The internal working process of each shift register stage can be understood by referring to the above, and is not described herein. On the basis, taking forward scanning as an example, the shift register ASG1 of the first stage is triggered by a signal input from the forward start signal input terminal STVF to start working; when the scanning signal output end of the ith-stage shift register outputs the scanning signal, the positive scanning signal input end INF of the (i +1) th-stage shift register is triggered to start working.

Optionally, referring to fig. 11, when applied to a display panel, the display panel is provided with 4 clock signal lines, which are CKV1, CKV2, CKV3 and CKV4, and further provided with a first reference signal line VGH, a second reference signal line VGL, a forward scan control line U2D and a reverse scan control line D2U. Taking four cascaded shift registers of the scan driving circuit as an example, the forward scan control end U2D of each shift register is electrically connected to the forward scan control line U2D (the forward scan control line and the forward scan control end are marked by the same sign); the forward scan control line U2D is used to provide a forward scan control signal to the forward scan control terminal U2D. The reverse scanning control terminals D2U of the shift registers of each stage are electrically connected to a reverse scanning control line D2U (the reverse scanning control line and the reverse scanning control terminals are labeled the same); the reverse scan control line D2U is used to provide a reverse scan control signal to the reverse scan control terminal D2U. The first reference signal end VGH of the shift register of each stage is electrically connected with the first reference signal line VGH (the first reference signal line and the first reference signal end adopt the same mark); the second reference signal terminals VGL of the shift registers of each stage are electrically connected to the second reference signal lines VGL (the second reference signal lines and the second reference signal terminals are marked by the same numerals). The first forward direction scan clock signal terminal RSTF of the first stage shift register is electrically connected to the CKV3, the first reverse direction scan clock signal terminal RSTB is electrically connected to the CKV1, and the second clock signal terminal OUT is electrically connected to the CKV 2. The first forward direction scan clock signal terminal RSTF of the second stage shift register is electrically connected to CKV4, the first reverse direction scan clock signal terminal RSTB is electrically connected to CKV2, and the second clock signal terminal OUT is electrically connected to CKV 3. The first forward direction scan clock signal terminal RSTF of the third stage shift register is electrically connected to the CKV1, the first reverse direction scan clock signal terminal RSTB is electrically connected to the CKV3, and the second clock signal terminal OUT is electrically connected to the CKV 4. The first forward direction scan clock signal terminal RSTF of the fourth stage shift register is electrically connected to the CKV2, the first reverse direction scan clock signal terminal RSTB is electrically connected to the CKV4, and the second clock signal terminal OUT is electrically connected to the CKV 1. The signals input by the same clock signal ends of two cascaded shift registers have a clock pulse difference.

Based on the same inventive concept, an embodiment of the present invention further provides a display panel, fig. 12 is a schematic structural diagram of the display panel provided by the embodiment of the present invention, and referring to fig. 12, the display panel 200 includes the scan driving circuit 100 provided by the above embodiment. Specifically, as shown in fig. 12, the display panel 200 includes a display area AA and a non-display area NA at least partially surrounding the display area AA, the scanning driving circuit 100 is disposed in the non-display area NA, the pixel circuit 201 is disposed in the display area NA, and the gate lines 202 and the data lines 203 are disposed in the display area NA, and the shift register ASG of the scanning driving circuit 100 may be electrically connected to at least one gate line 202.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, and fig. 13 is a schematic structural diagram of the display device provided in the embodiment of the present invention, and the display device 300 includes the display panel 200. The display device 300 provided in the embodiment of the present invention may be a mobile phone shown in fig. 13, and may also be any electronic product with a display function, including but not limited to the following categories: the touch screen display system comprises a television, a notebook computer, a desktop display, a tablet computer, a digital camera, an intelligent bracelet, intelligent glasses, a vehicle-mounted display, medical equipment, industrial control equipment, a touch interaction terminal and the like, and the embodiment of the invention is not particularly limited in this respect.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A shift register, comprising: the device comprises a first node control module, a second node control module, an output module, a node mutual control module, a pull-down module, a scanning control end, a signal input end, a first clock signal end, a second clock signal end, a first reference signal end, a second reference signal end, a scanning signal output end, a pull-down control end and a pull-down signal end;

the first node control module is electrically connected with the scanning control end and the signal input end respectively; the first node control module is also electrically connected with the output module to a first node; in a charging phase, the first node control module is configured to charge the first node under the control of a scan control signal of the scan control terminal and an input signal of the signal input terminal;

the second node control module is electrically connected with the first reference signal terminal, the first clock signal terminal and the scanning control terminal respectively; the second node control module is also electrically connected with the output module to a second node; in a reset phase, the second node control module is configured to transmit a first reference potential of the first reference signal terminal to the second node under the control of the scan control signal and a first clock signal of the first clock signal terminal;

the output module is also electrically connected with the second clock signal end, the second reference signal end and the scanning signal output end respectively; in the charging stage, the output module is configured to output a second clock signal of the second clock signal terminal to the scan signal output terminal under the control of the potential of the first node; in the reset stage, the output module is configured to output a second reference signal of the second reference signal terminal to the scan signal output terminal under the control of the potential of the second node;

the node mutual control module is respectively electrically connected with the first node, the second node and the second reference signal terminal; in the charging stage, the node mutual control module is configured to control a second reference potential of the second reference signal terminal to be transmitted to the second node according to the potential of the first node; in the reset stage, the node mutual control module is configured to control a second reference potential of the second reference signal terminal to be transmitted to the first node according to a potential of the second node;

the pull-down module is electrically connected with the pull-down control end, the pull-down signal end and the second node respectively; in the charging stage, the pull-down module is configured to transmit a disable level of the pull-down signal to the second node under the control of the pull-down control signal.

2. The shift register of claim 1, wherein the scan control terminal provides an enable level of the scan control signal in the charge phase and the reset phase, and provides a scan control signal disable level in an intermittent phase;

the signal input end provides an enable level of an input signal in the charging phase and provides a non-enable level of the input signal in the intermittence phase and the reset phase;

in the intermittent phase, the first node control module is configured to be in a non-biased state under the control of the scan control signal and the input signal.

3. The shift register according to claim 2, wherein the second clock signal terminal is configured to provide a non-enable level of the second clock signal during the charging phase, the resetting phase, and the intermitting phase, and provide an enable level of the second clock signal during the signal outputting phase;

the scanning control end is also used for providing an enabling level of the scanning control signal in the signal output stage;

the signal input end is also used for providing a non-enabling level of the input signal in the signal output stage;

wherein the signal output phase is located between the charging phase and the reset phase.

4. A shift register according to claim 3, wherein the intermittent stages include a first intermittent stage, a second intermittent stage and a third intermittent stage; the first intermittent phase is located between the charging phase and the signal output phase; the second intermittent phase is located between the signal output phase and the reset phase; the third intermittent phase is after the reset phase or the third intermittent phase is before the charge phase.

5. The shift register according to claim 1, wherein the scan control terminal includes a forward scan control terminal and a reverse scan control terminal; the signal input end comprises a forward scanning signal input end and a reverse scanning signal input end; the first clock signal end comprises a first forward scanning clock signal end and a first reverse scanning clock signal end;

the forward scanning control end is used for providing an enabling level of a forward scanning control signal in a charging stage and a resetting stage of forward scanning; the reverse scanning control end is used for providing an enabling level of a reverse scanning control signal in a charging stage and a resetting stage of reverse scanning;

the forward scanning signal input end is used for providing an enabling level of a forward input signal in a charging phase of the forward scanning; the reverse scanning signal input end is used for providing an enabling level of a reverse input signal in a charging phase of the reverse scanning.

6. The shift register of claim 5, wherein the pull-down signal terminal comprises a forward pull-down signal terminal and a reverse pull-down signal terminal; the pull-down control end comprises a forward pull-down control end and a reverse pull-down control end;

in a charging phase of the forward scan, the pull-down module is configured to transmit a disable level of a forward pull-down signal of the forward pull-down signal terminal to the second node under the control of a forward pull-down control signal of the forward pull-down control terminal; in a charging stage of the reverse scan, the pull-down module is configured to transmit a disable level of a reverse pull-down signal of the reverse pull-down signal terminal to the second node under the control of a reverse pull-down control signal of the reverse pull-down control terminal;

the forward scanning signal input end is multiplexed as the forward pull-down control end, and the reverse scanning signal input end is multiplexed as the reverse pull-down control end; the forward scanning control end is multiplexed as the reverse pull-down signal end, and the reverse scanning control end is multiplexed as the forward pull-down signal end.

7. The shift register according to claim 6, wherein the first node control module includes a first transistor and a second transistor; the pull-down module comprises a third transistor and a fourth transistor;

the grid electrode of the first transistor and the grid electrode of the third transistor are electrically connected with the positive scanning signal input end; the grid electrode of the second transistor and the grid electrode of the fourth transistor are electrically connected with the reverse scanning signal input end; the first electrode of the first transistor and the first electrode of the fourth transistor are both electrically connected with the forward scanning control end; the first electrode of the second transistor and the first electrode of the third transistor are both electrically connected with the reverse scanning control end; a second pole of the first transistor and a second pole of the second transistor are both electrically connected to the first node; a second pole of the third transistor and a second pole of the fourth transistor are both electrically connected to the second node;

wherein a channel type of the first transistor is the same as a channel type of the third transistor, and a channel type of the second transistor is the same as a channel type of the fourth transistor.

8. The shift register according to claim 5, wherein the second node control module includes a fifth transistor, a sixth transistor, and a seventh transistor;

a grid electrode of the fifth transistor is electrically connected with the forward scanning control end, and a first electrode of the fifth transistor is electrically connected with the first forward scanning clock signal end; a grid electrode of the sixth transistor is electrically connected with the reverse scanning control end, and a first electrode of the sixth transistor is electrically connected with the first reverse scanning clock signal end; a second pole of the fifth transistor and a second pole of the sixth transistor are both electrically connected to the gate of the seventh transistor;

a first electrode of the seventh transistor is electrically connected to the first reference signal terminal, and a second electrode of the seventh transistor is electrically connected to the second node.

9. The shift register of claim 1, wherein the node mutual control module comprises an eighth transistor and a ninth transistor;

a gate of the eighth transistor is electrically connected to the second node, a first electrode of the eighth transistor is electrically connected to the second reference signal terminal, and a second electrode of the eighth transistor is electrically connected to the first node;

a gate of the ninth transistor is electrically connected to the first node, a first electrode of the ninth transistor is electrically connected to the second reference signal terminal, and a second electrode of the ninth transistor is electrically connected to the second node.

10. The shift register according to claim 9, wherein the output block includes a tenth transistor, an eleventh transistor, a first capacitor, and a second capacitor;

a gate of the tenth transistor and a first end of the first capacitor are both electrically connected to the first node; a first electrode of the tenth transistor is electrically connected to the second clock signal terminal; a second pole of the tenth transistor and a second end of the first capacitor are both electrically connected with the scanning signal output end;

a gate of the eleventh transistor and a first end of the second capacitor are both electrically connected to the second node; a first electrode of the eleventh transistor and a second end of the second capacitor are both electrically connected to the second reference signal terminal; a second pole of the eleventh transistor is electrically connected to the scan signal output terminal;

wherein the eighth transistor is of the same channel type as the eleventh transistor; the ninth transistor is of the same channel type as the tenth transistor.

11. The shift register according to any one of claims 1 to 10, wherein the first node includes a first a node and a first b node; the first node control module is electrically connected with the first node A, and the output module is electrically connected with the first node B;

the shift register also comprises a voltage stabilization protection module; the voltage stabilization protection module is electrically connected with the first reference signal end, the first node A and the first node B respectively; the voltage stabilization protection module is used for maintaining the electric potential of the first node A to be less than or equal to a preset voltage value under the control of the first reference signal end and the first node B.

12. The shift register according to any one of claims 1 to 10, further comprising: the system comprises a first node potential adjusting module, a second node potential adjusting module and a starting control end;

the starting control end is used for providing an enabling level of a starting control signal in a starting stage;

the first node potential adjusting module is electrically connected with the starting control end, the first reference signal end and the scanning signal output end respectively; in the starting stage, the first node potential adjusting module is configured to transmit the first reference potential to the scan signal output end under the control of the starting control signal;

the second node potential adjusting module is electrically connected with the starting control end, the second reference signal end and the second node respectively; in the starting stage, the second node potential adjusting module is configured to transmit the second reference potential to the second node under the control of the starting control signal;

wherein the start-up phase precedes the charge phase and the reset phase.

13. A method for driving a shift register, which is performed by using the shift register according to any one of claims 1 to 12, comprising:

in a charging stage, the scan control terminal provides an enable level of a scan control signal, the signal input terminal provides an enable level of an input signal, and the first node control module is controlled to charge the first node; the node mutual control module controls the second reference potential to be transmitted to the second node according to the potential of the first node; the pull-down control end provides an enabling level of a pull-down control signal, the pull-down signal end provides a non-enabling level of the pull-down signal, and the pull-down module is controlled to pull down the potential of the second node; the output module outputs a second clock signal of the second clock signal end to the scanning signal output end under the control of the potential of the first node;

in a signal output stage, the second clock signal terminal provides an enable level of the second clock signal, and the output module outputs the enable level of the second clock signal under the control of the potential of the first node;

in a reset stage, the scan control terminal provides an enable level of a scan control signal, the first clock signal terminal provides an enable level of a first clock signal, and the second node control module is controlled to transmit a first reference potential of the first reference signal terminal to the second node; the node mutual control module controls a second reference potential of the second reference signal end to be transmitted to the first node according to the potential of the second node; the output module outputs a second reference signal of the second reference signal terminal to the scan signal output terminal under the control of the potential of the second node.

14. The driving method according to claim 13, further comprising:

in the intermittent stage, the scan control terminal provides a non-enable level of the scan control signal, and the signal input terminal provides a non-enable level of the input signal to control the first node control module to be in a non-bias state.

15. A scan driving circuit, comprising: a plurality of shift registers according to any one of claims 1 to 12; a plurality of the shift registers are arranged in cascade.

16. A display panel, comprising: the scan driver circuit of claim 15.

17. A display device, comprising: the display panel of claim 16.